From: Wasim Khan <wasim.k...@nxp.com>
PCIe Layerscape controller in LX2160A-Rev2 is not completely
ECAM-compliant. It is non-ECAM only for the root bus (bus 0)
and for any other bus underneath the root bus it does support
ECAM access.
One approach can be to setup the controller in firmware and
expose bus[0x1-0xff] to OS via MCFG and DSDT table.
Introduce PcdPciHideRootPort PCD and set it for LX2160A-Rev2 for this.
Limit the size of CFG0 iATU window (for type0 config transactions)
to 32KB to avoid enumuration of unwanted devices in OS.
Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 +
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
Silicon/NXP/Include/Pcie.h | 1 +
Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 7 +++++++
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 6 +++++-
6 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index d09a1ae194be..188a9fe1f382 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -40,3 +40,4 @@ [PcdsFixedAtBuild.common]
[PcdsDynamic.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601
+ gNxpQoriqLsTokenSpaceGuid.PcdPciHideRootPort|FALSE|BOOLEAN|0x00000602
diff --git a/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
b/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 2514adf1d69d..674ba3b298f3 100644
--- a/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -30,6 +30,7 @@ [LibraryClasses]
[Pcd]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl
+ gNxpQoriqLsTokenSpaceGuid.PcdPciHideRootPort
[Depex]
TRUE
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 6003da708698..3726ec15317f 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -42,3 +42,4 @@ [FixedPcd]
[Pcd]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl
+ gNxpQoriqLsTokenSpaceGuid.PcdPciHideRootPort
diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
index b5bf0ff5d1d4..4bc99bb53025 100755
--- a/Silicon/NXP/Include/Pcie.h
+++ b/Silicon/NXP/Include/Pcie.h
@@ -31,6 +31,7 @@
#define PCI_SEG_PORTIO_MIN 0x0
#define PCI_SEG_PORTIO_MAX 0xffff
#define SEG_CFG_SIZE 0x00001000
+#define ECAM_DEVICE_SIZE SIZE_32KB
#define ECAM_BUS_SIZE SIZE_1MB
#define ECAM_CFG_REGION_SIZE SIZE_256MB
#define SEG_MEM_BASE 0x40000000
diff --git a/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
b/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
index 0caabb448ec0..0c013dd01009 100644
--- a/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -53,6 +53,13 @@ SetPciControllerPcdOptions (
// PCIe controller and program the iATU windows accordingly.
//
PcdSetBoolS (PcdPciCfgShiftEnable, TRUE);
+
+ //
+ // PCIe controller in LX2160-Rev2 is not ECAM-compliant for bus0.
+ // Set PcdPciHideRootPort for LX2160-Rev2, which will be used by
+ // PciHostBridgeLib and PciSegmentLib to program iATU windows
accordingly.
+ //
+ PcdSetBoolS (PcdPciHideRootPort, TRUE);
break;
default:
DEBUG ((DEBUG_ERROR, "%a: Invalid SoC Version 0x%x \n", __FUNCTION__,
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 8bbbaaa6e24d..7f11d7a60256 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -432,7 +432,11 @@ PcieLsSetupAtu (
Cfg0BusAddress = SIZE_1MB;
Cfg1BusAddress = SIZE_2MB;
// Region for type0 CFG transactions (only for bus1)
- Cfg0Size = ECAM_BUS_SIZE;
+ if (PcdGetBool (PcdPciHideRootPort)) {
+ Cfg0Size = ECAM_DEVICE_SIZE;
+ } else {
+ Cfg0Size = ECAM_BUS_SIZE;
+ }
// Region for type1 CFG transactions (for bus > 1)
Cfg1Size = (ECAM_CFG_REGION_SIZE - ECAM_BUS_SIZE); // 255MB
} else {
--
2.7.4
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