From: Wasim Khan <wasim.k...@nxp.com>
Dump ATU windows for PCIe LsGen4 controller.
Co-authored-by: Vabhav Sharma <vabhav.sha...@nxp.com>
Co-authored-by: Wasim Khan <wasim.k...@nxp.com>
Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
---
Notes:
V2:
- Removed Signed-off and added Co-authored-by for co-author
- Drop PcdPciDebug and use DEBUG_CODE_BEGIN/DEBUG_CODE_END
- Passing Max window number as argument to LsGen4DumpAtu()
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 36
++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 339a3d9bffa6..53b93e2b6f23 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -399,6 +399,38 @@ PcieLsSetupAtu (
}
/**
+ Dump PCIe LsGen4 ATU
+
+ @param Pcie Address of PCIe host controller.
+ @param Count Number of Windows
+**/
+VOID LsGen4DumpAtu (
+ IN EFI_PHYSICAL_ADDRESS Pcie,
+ IN UINT32 Count
+ )
+{
+ UINT32 Cnt;
+ for (Cnt = 0; Cnt < Count; Cnt++) {
+ DEBUG ((DEBUG_INFO,"APIO WINDOW%d:\n", Cnt));
+ DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_AXI_WIN (Cnt))));
+ DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_AXI_WIN (Cnt))));
+ DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_L (Cnt))));
+ DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_H (Cnt))));
+ DEBUG ((DEBUG_INFO,"\tSIZE 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt)) &
+ (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT)));
+ DEBUG ((DEBUG_INFO,"\tEXT_SIZE 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_SIZE (Cnt))));
+ DEBUG ((DEBUG_INFO,"\tCTRL: 0x%08x\n",
+ PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt))));
+ }
+}
+
+/**
Function to set-up ATU windows for PCIe LayerscapeGen4 controller
@param Pcie Address of PCIe host controller
@@ -462,6 +494,10 @@ PcieLsGen4SetupAtu (
Mem64Base += SIZE_4GB;
}
+
+ DEBUG_CODE_BEGIN ();
+ LsGen4DumpAtu (Pcie, Index);
+ DEBUG_CODE_END ();
}
/**
--
2.7.4
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#60258): https://edk2.groups.io/g/devel/message/60258
Mute This Topic: https://groups.io/mt/74474416/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
