> -----Original Message-----
> From: Leif Lindholm <l...@nuviainc.com>
> Sent: Wednesday, June 17, 2020 8:24 PM
> To: Wasim Khan (OSS) <wasim.k...@oss.nxp.com>
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com>; Varun Sethi <v.se...@nxp.com>;
> ard.biesheu...@arm.com; Wasim Khan <wasim.k...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 2/8] Silicon/NXP: Chassis2: define SVR
> macros
>
> On Wed, Jun 10, 2020 at 02:50:53 +0530, Wasim Khan wrote:
> > From: Wasim Khan <wasim.k...@nxp.com>
> >
> > Define macros to retrieve System Version Register(SVR) related
> > information
> >
> > Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
> > ---
> > Silicon/NXP/Chassis2/Include/Chassis.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
> > b/Silicon/NXP/Chassis2/Include/Chassis.h
> > index e5edd80134a4..7e8bf224884b 100644
> > --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> > @@ -12,6 +12,10 @@
> >
> > #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> >
> > +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
> > +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > +
> > /* SMMU Defintions */
> > #define SMMU_BASE_ADDR 0x09000000
> > #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
>
> These macros are identical between Chassis2 and Chassis3V2, and they also look
> like exactly the sort of thing you want identical across different chassis.
> Is there
> a common header file they can use?
Thank you Leif for the review.
These MACROS are chassic specific. Upper 24 bits representation is different in
Chassis2 and Chassis3V2 (although not used currently and masked for SVR
calculation but we may need it in future).
SVR representation may further change for future SoC, so we would like to keep
them in chassis specific header file.
>
> (The set is straightforward, I have no other comments on it.)
>
> /
> Leif
>
> > --
> > 2.7.4
> >
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