From: Wasim Khan <wasim.k...@nxp.com>
PCIe Layerscape Gen4 controller is not ECAM complaint and have
different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For config transactions for Bus[0x1-0xff]:
- PCIe IP requires target BDF to be written at bit[31:16] of PCIe
outbound configuration window.
PCIe LsGen4 controller uses paging mechanism to access registers.
To access PCIe CCSR registers which are above 3KB offset, page number
must be set in Bridge Control Register.
Signed-off-by: Vabhav Sharma <vabhav.sha...@nxp.com>
Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
---
.../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 1 +
Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 60 +++++++++++++++++++++-
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
index 936213dc8a9d..d6d7ea6e3b6b 100755
--- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
@@ -33,3 +33,4 @@ [FixedPcd]
[Pcd]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
index 552a425c6832..02a1525ef308 100755
--- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
@@ -35,6 +35,58 @@ typedef enum {
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
static BOOLEAN CfgShiftEnable;
+static BOOLEAN PciLsGen4Ctrl;
+
+STATIC
+VOID
+PcieCfgSetTarget (
+ IN EFI_PHYSICAL_ADDRESS Dbi,
+ IN UINT32 Target)
+{
+ PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_L(0), Target);
+ PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
+}
+
+/**
+ Function to return PCIe Physical Address(PCIe view) or Controller
+ Address(CPU view) for NXP Layerscape Gen4 SoC
+
+ @param Address Address passed from bus layer.
+ @param Segment Segment number for Root Complex.
+ @param Offset Config space register offset.
+ @param Bus PCIe Bus number.
+
+ @return Return PCIe CPU or Controller address.
+
+**/
+STATIC
+UINT64
+PciLsGen4GetConfigBase (
+ IN UINT64 Address,
+ IN UINT16 Segment,
+ IN UINT16 Offset,
+ IN UINT8 Bus
+ )
+{
+ UINT32 Target;
+
+ if (Bus) {
+ Target = ((((Address >> 20) & 0xFF) << 24) |
+ (((Address >> 15) & 0x1F) << 19) |
+ (((Address >> 12) & 0x7) << 16));
+
+ PcieCfgSetTarget ((PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF* Segment),
Target);
+ return PCI_SEG0_MMIO_MEMBASE + Offset + PCI_BASE_DIFF * Segment;
+ } else {
+ if (Offset < INDIRECT_ADDR_BNDRY) {
+ PciLsGen4SetPg (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment, 0);
+ return (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + Offset);
+ }
+ PciLsGen4SetPg (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment,
OFFSET_TO_PAGE_IDX (Offset));
+ Offset = OFFSET_TO_PAGE_ADDR (Offset);
+ return (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + Offset);
+ }
+}
STATIC
UINT64
@@ -129,7 +181,12 @@ PciSegmentLibGetConfigBase (
UINT8 Bus;
Bus = ((UINT32)Address >> 20) & 0xff;
- return PciLsGetConfigBase (Address, Segment, Offset, Bus);
+
+ if (PciLsGen4Ctrl) {
+ return PciLsGen4GetConfigBase (Address, Segment, Offset, Bus);
+ } else {
+ return PciLsGetConfigBase (Address, Segment, Offset, Bus);
+ }
}
/**
@@ -620,5 +677,6 @@ PciSegLibInit (
)
{
CfgShiftEnable = CFG_SHIFT_ENABLE;
+ PciLsGen4Ctrl = PCI_LS_GEN4_CTRL;
return EFI_SUCCESS;
}
--
2.7.4
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