preames wrote:
> I am not sue about the acceptance of the "tt" naming here given we use full
> names for all other vendors in this context. Can you raise that point
> specifically at the next RISCV sync up call for discussion?
Just to close the loop. We did briefly touch on this in the sync u
https://github.com/mshockwave closed
https://github.com/llvm/llvm-project/pull/115100
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github-actions[bot] wrote:
@ppenzin Congratulations on having your first Pull Request (PR) merged into the
LLVM Project!
Your changes will be combined with recent changes from other authors, then
tested by our [build bots](https://lab.llvm.org/buildbot/). If there is a
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ppenzin wrote:
If we are all good, can someone merge this? I don't have write access.
https://github.com/llvm/llvm-project/pull/115100
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/115100
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https://github.com/mshockwave approved this pull request.
LGTM.
I don't have any strong opinion on the CPU name
https://github.com/llvm/llvm-project/pull/115100
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ppenzin wrote:
Are there still open questions for the sync call?
https://github.com/llvm/llvm-project/pull/115100
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ppenzin wrote:
We would take `ascalon-d8`, but `tt-ascalon-d8` is just as good.
https://github.com/llvm/llvm-project/pull/115100
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
camel-cdr wrote:
Ventana's Veyron V1 is called `veyron-v1` not `ventana-veyron-v1`, Qualcomm's
oryon is `oryon-1`.
>From existing names, it seems like just `ascalon-d8` would be expected. The
>company prefixes seem to mostly be used for very short processor names:
>`apple-m1`, `spacemit-x60`,
preames wrote:
I am not sue about the acceptance of the "tt" naming here given we use full
names for all other vendors in this context. Can you raise that point
specifically at the next RISCV sync up call for discussion?
https://github.com/llvm/llvm-project/pull/115100
_
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/ppenzin updated
https://github.com/llvm/llvm-project/pull/115100
>From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001
From: Petr Penzin
Date: Tue, 5 Nov 2024 13:11:48 -0600
Subject: [PATCH 1/4] [RISCV] Add TT-Ascalon-d8 processor
Ascalon is an out-of-order
@@ -104,6 +104,62 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max |
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalo
@@ -104,6 +104,62 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max |
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalo
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/115100
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https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/115100
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@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/ppenzin updated
https://github.com/llvm/llvm-project/pull/115100
>From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001
From: Petr Penzin
Date: Tue, 5 Nov 2024 13:11:48 -0600
Subject: [PATCH 1/3] [RISCV] Add TT-Ascalon-d8 processor
Ascalon is an out-of-order
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/topperc edited
https://github.com/llvm/llvm-project/pull/115100
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
https://github.com/ppenzin updated
https://github.com/llvm/llvm-project/pull/115100
>From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001
From: Petr Penzin
Date: Tue, 5 Nov 2024 13:11:48 -0600
Subject: [PATCH 1/2] [RISCV] Add TT-Ascalon-d8 processor
Ascalon is an out-of-order
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
ppenzin wrote:
> Hi @ppenzin! Is this core used in many-cores products like wormhole?
This is separate from AI accelerator cores.
https://github.com/llvm/llvm-project/pull/115100
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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVP
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