[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

[Petr Penzin via cfe-commits]

================
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
                                                FeatureStdExtZkn],
                                               [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
 
+def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
+                                              NoSchedModel,
----------------
ppenzin wrote:

Do you mean between the name and feature flags?

https://github.com/llvm/llvm-project/pull/115100
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits