================ @@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", ---------------- wangpc-pp wrote:
Yeah I agree it is shorter. I don't know if this is a de-facto policy here, we seem to use full name for all CPUs. For example, we don't use `sf` for SiFive, etc. https://github.com/llvm/llvm-project/pull/115100 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits