================ @@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", ---------------- ppenzin wrote:
We'd prefer `tt` as it would be shorter :smile: https://github.com/llvm/llvm-project/pull/115100 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits