https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/115100
>From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001 From: Petr Penzin <ppen...@tenstorrent.com> Date: Tue, 5 Nov 2024 13:11:48 -0600 Subject: [PATCH 1/3] [RISCV] Add TT-Ascalon-d8 processor Ascalon is an out-of-order CPU core from Tenstorrent. Overview: https://tenstorrent.com/ip/tt-ascalon Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be added in a separate PR. Co-authored-by: Anton Blanchard <ant...@tenstorrent.com> --- clang/test/Driver/riscv-cpus.c | 54 +++++++++++++++++++ .../test/Misc/target-invalid-cpu-note/riscv.c | 2 + llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 48 +++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index d36639d16ad4cb..468e01c8d934da 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -104,6 +104,60 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s +// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s +// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" "-target-feature" "+a" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" "-target-feature" "+d" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" "-target-feature" "+v" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" "-target-feature" "+zicbom" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" "-target-feature" "+zcb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" + // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1" // MCPU-VEYRON-V1: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 7bbf3574af3c35..8c5df5884cd791 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -41,6 +41,7 @@ // RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // RISCV64-SAME: {{^}}, syntacore-scr7 +// RISCV64-SAME: {{^}}, tt-ascalon-d8 // RISCV64-SAME: {{^}}, veyron-v1 // RISCV64-SAME: {{^}}, xiangshan-nanhu // RISCV64-SAME: {{$}} @@ -87,6 +88,7 @@ // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7 +// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8 // TUNE-RISCV64-SAME: {{^}}, veyron-v1 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu // TUNE-RISCV64-SAME: {{^}}, generic diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 290473cdb46f4c..d7d2beb846fb3e 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -185,6 +185,7 @@ Changes to the RISC-V Backend * The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally. * Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. +* `-mcpu=tt-ascalon-d8` was added. * The `Zacas` extension is no longer marked as experimental. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 5277752a38ad9e..fb50ea2ac22b50 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtZicsr, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZihintpause, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtV, + FeatureStdExtZvl256b, + FeatureStdExtZfh, + FeatureStdExtZvfh, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtH, + FeatureStdExtZihintntl, + FeatureStdExtZfhmin, + FeatureStdExtZfa, + FeatureStdExtZkt, + FeatureStdExtZcb, + FeatureStdExtZvbb, + FeatureStdExtZvbc, + FeatureStdExtZawrs, + FeatureStdExtZvkng, + FeatureStdExtZicond, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem, + FeatureStdExtSvnapot, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtZfbfmin, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma], + [TuneNoDefaultUnroll, + TuneOptimizedZeroStrideLoad, + TuneNoSinkSplatOperands, + FeaturePostRAScheduler]>; + def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, [Feature64Bit, >From 6f980c735b19e4e5e3f9d04b2e27e23b07c9ec27 Mon Sep 17 00:00:00 2001 From: Petr Penzin <ppen...@tenstorrent.com> Date: Wed, 6 Nov 2024 18:38:53 -0600 Subject: [PATCH 2/3] Fix ident and features Add Zimop, remove redundant definition, remove NoSinkSplat. --- clang/test/Driver/riscv-cpus.c | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 91 ++++++++++++------------ 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 468e01c8d934da..69c63ae112b7b6 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -122,6 +122,7 @@ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index fb50ea2ac22b50..6ff7067cd2bea0 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -408,52 +408,51 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", - NoSchedModel, - [Feature64Bit, - FeatureStdExtI, - FeatureStdExtZifencei, - FeatureStdExtZicsr, - FeatureStdExtZicntr, - FeatureStdExtZihpm, - FeatureStdExtZihintpause, - FeatureStdExtM, - FeatureStdExtA, - FeatureStdExtF, - FeatureStdExtD, - FeatureStdExtC, - FeatureStdExtV, - FeatureStdExtZvl256b, - FeatureStdExtZfh, - FeatureStdExtZvfh, - FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbs, - FeatureStdExtZicbom, - FeatureStdExtZicbop, - FeatureStdExtZicboz, - FeatureStdExtH, - FeatureStdExtZihintntl, - FeatureStdExtZfhmin, - FeatureStdExtZfa, - FeatureStdExtZkt, - FeatureStdExtZcb, - FeatureStdExtZvbb, - FeatureStdExtZvbc, - FeatureStdExtZawrs, - FeatureStdExtZvkng, - FeatureStdExtZicond, - FeatureUnalignedScalarMem, - FeatureUnalignedVectorMem, - FeatureStdExtSvnapot, - FeatureStdExtSvpbmt, - FeatureStdExtSvinval, - FeatureStdExtZfbfmin, - FeatureStdExtZvfbfmin, - FeatureStdExtZvfbfwma], - [TuneNoDefaultUnroll, - TuneOptimizedZeroStrideLoad, - TuneNoSinkSplatOperands, - FeaturePostRAScheduler]>; + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtZicsr, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZihintpause, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtV, + FeatureStdExtZvl256b, + FeatureStdExtZfh, + FeatureStdExtZvfh, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZimop, + FeatureStdExtH, + FeatureStdExtZihintntl, + FeatureStdExtZfa, + FeatureStdExtZkt, + FeatureStdExtZcb, + FeatureStdExtZvbb, + FeatureStdExtZvbc, + FeatureStdExtZawrs, + FeatureStdExtZvkng, + FeatureStdExtZicond, + FeatureStdExtSvnapot, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtZfbfmin, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem], + [TuneNoDefaultUnroll, + TuneOptimizedZeroStrideLoad, + FeaturePostRAScheduler]>; def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, >From 34cc9f8cbbeae6f617b47047c4fb5f7ccb8aea0a Mon Sep 17 00:00:00 2001 From: Petr Penzin <ppen...@tenstorrent.com> Date: Fri, 8 Nov 2024 19:09:07 -0600 Subject: [PATCH 3/3] Rewrite extension list using RVA23 --- clang/test/Driver/riscv-cpus.c | 3 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 47 ++++++------------------ 2 files changed, 13 insertions(+), 37 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 69c63ae112b7b6..72f98f19aa8fa1 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -112,7 +112,8 @@ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" "-target-feature" "+a" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" "-target-feature" "+d" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" "-target-feature" "+v" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" "-target-feature" "+zicbom" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 6ff7067cd2bea0..6b43fe2cfcf555 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -409,47 +409,22 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", NoSchedModel, - [Feature64Bit, - FeatureStdExtI, - FeatureStdExtZifencei, - FeatureStdExtZicsr, - FeatureStdExtZicntr, - FeatureStdExtZihpm, - FeatureStdExtZihintpause, - FeatureStdExtM, - FeatureStdExtA, - FeatureStdExtF, - FeatureStdExtD, - FeatureStdExtC, - FeatureStdExtV, - FeatureStdExtZvl256b, + !listconcat(RVA23S64Features, + [FeatureStdExtSmaia, + FeatureStdExtSsaia, + FeatureStdExtSscofpmf, + FeatureStdExtSsstrict, + FeatureStdExtZfbfmin, FeatureStdExtZfh, - FeatureStdExtZvfh, - FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbs, - FeatureStdExtZicbom, - FeatureStdExtZicbop, - FeatureStdExtZicboz, - FeatureStdExtZimop, - FeatureStdExtH, - FeatureStdExtZihintntl, - FeatureStdExtZfa, - FeatureStdExtZkt, - FeatureStdExtZcb, - FeatureStdExtZvbb, + FeatureStdExtZicsr, FeatureStdExtZvbc, - FeatureStdExtZawrs, - FeatureStdExtZvkng, - FeatureStdExtZicond, - FeatureStdExtSvnapot, - FeatureStdExtSvpbmt, - FeatureStdExtSvinval, - FeatureStdExtZfbfmin, FeatureStdExtZvfbfmin, FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvkng, + FeatureStdExtZvl256b, FeatureUnalignedScalarMem, - FeatureUnalignedVectorMem], + FeatureUnalignedVectorMem]), [TuneNoDefaultUnroll, TuneOptimizedZeroStrideLoad, FeaturePostRAScheduler]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
