This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
v2: use idx
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
since we loop through the queues |= the errors.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu
Add helpers to unmap and map user queues on suspend and
resume.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git
Unmap user queues on suspend and map them on resume.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu
Track this to align with KFD for enforce isolation
handling.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
index
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
v2: free idr as well (Sunil)
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu
On Fri, Apr 11, 2025 at 1:18 PM Khatri, Sunil wrote:
>
> A small comment otherwise it looks great.
> Reviewed-by: Sunil Khatri
>
> On 4/11/2025 12:23 AM, Alex Deucher wrote:
> > Enable users to create queues at different priority levels.
> > The highest level
ferent IP versions, using
> PACKET3_RUN_CLEANER_SHADER_9_0 for the versions 9.0.1, 9.1.0,
> 9.2.1, 9.2.2, 9.3.0, and 9.4.0, while retaining
> PACKET3_RUN_CLEANER_SHADER for version 9.4.2.
>
> v2: Simplify logic (Alex).
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-b
do not
> interfere with subsequent workloads.
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/soc15d.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/d
use they are no longer KFD specific and then the change to add the
new function calls for userqs.
Alex
>
> Looks good in general if the above understanding is correct. Some one
> with better understanding of isolation should review.
> Acked-by: Sunil Khatri
>
> On 4/10/202
On Fri, Apr 11, 2025 at 1:26 PM Khatri, Sunil wrote:
>
>
> On 4/11/2025 10:22 PM, Alex Deucher wrote:
> > On Fri, Apr 11, 2025 at 12:17 PM Khatri, Sunil wrote:
> >>
> >> On 4/11/2025 7:42 PM, Alex Deucher wrote:
> >>> This will be used to stop/start
On Fri, Apr 11, 2025 at 12:17 PM Khatri, Sunil wrote:
>
>
> On 4/11/2025 7:42 PM, Alex Deucher wrote:
> > This will be used to stop/start user queue scheduling for
> > example when switching between kernel and user queues when
> > enforce isolation is enabled.
> >
ferent IP versions, using
> PACKET3_RUN_CLEANER_SHADER_9_0 for the versions 9.0.1, 9.1.0,
> 9.2.1, 9.2.2, 9.3.0, and 9.4.0, while retaining
> PACKET3_RUN_CLEANER_SHADER for version 9.4.2.
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> Sugges
On Fri, Apr 11, 2025 at 4:37 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> Register stop/start/soft_reset queue functions for SDMA IP versions
> v4.4.2, v5.0 and v5.2.
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
Might want
ngine_reset_funcs` function, which was
> used to register the callbacks.
>- Removed the `sdma_v4_4_2_engine_reset_funcs` structure, which contained
> the pre-reset and post-reset callback functions.
>
> Signed-off-by: Jesse Zhang
> Reviewed-by: Alex Deucher
Reviewed-by: Alex Deu
cing the previous call to `amdgpu_dpm_reset_sdma`.
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 38 +++-
> 1 file changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/
uot; last.
> E.g. longest lines first and short lasts. (Chritian)
>
> Signed-off-by: Jesse Zhang
> Acked-by: Alex Deucher
Might want to split this per IP? Either way:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 31 --
&
On Fri, Apr 11, 2025 at 4:30 AM jesse.zh...@amd.com wrote:
>
> From: "jesse.zh...@amd.com"
>
> Replace old callback mechanism with direct calls to stop/start functions.
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
Reviewed-by: Alex Deucher
>
to use ring pointer
> instead of device/instance(Chritian)
> v3: move stop_queue/start_queue to struct amdgpu_sdma_instance and rename
> them. (Alex)
> v4: rework the ordering a bit (Alex)
>
> Suggested-by: Alex Deucher
> Signed-off-by: Jesse Zhang
Reviewed-by:
Unmap user queues on suspend and map them on resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
Not techincally wrong, but I think a semicolon was
intended here.
Fixes: 6cc6e61788f7 ("drm/amdgpu: use a dummy owner for sysfs triggered cleaner
shaders v3")
Cc: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 inser
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
On Fri, Apr 11, 2025 at 9:05 AM Sunil Khatri wrote:
>
> add process and pid information in the userqueue error
> logging to make it more useful in resolving the error
> by logs.
>
> Sample log:
> [ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
> out waiting for fence
On Fri, Apr 11, 2025 at 9:05 AM Sunil Khatri wrote:
>
> add process and pid information in the userqueue error
> logging to make it more useful in resolving the error
> by logs.
>
> Sample log:
> [ 42.444297] [drm:amdgpu_userqueue_wait_for_signal [amdgpu]] *ERROR* Timed
> out waiting for fence
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
v2: free idr as well (Sunil)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
Add helpers to unmap and map user queues on suspend and
resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd
since we loop through the queues |= the errors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 68
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1
On Fri, Apr 11, 2025 at 8:42 AM Lijo Lazar wrote:
>
> Except HDP v5.2 all use a common logic for HDP flush. Use a generic
> function. HDP v5.2 forces NO_KIQ logic, revisit it later.
>
> Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amd
r_submission.
>
> The mismatch caused UBSAN to report an array bounds violation since
> it was accessing the GFX ring array with SDMA instance indices.
>
> Fix the commit: a245daf3d7a143fb2df(drm/amdgpu: cleanup HW_IP query).
Fixes: 4310acd4464b ("drm/amdgpu: add ring flag for
On Fri, Apr 11, 2025 at 4:07 AM Emily Deng wrote:
>
> For VF, it doesn't have the permission to clear overflow, clear the bit
> by reset.
>
> Signed-off-by: Emily Deng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 10 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 1 +
> drivers/gpu/d
Copy paste typo. Use the flag from the sdma structure.
Fixes: 4310acd4464b ("drm/amdgpu: add ring flag for no user submissions")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
off-by: Lijo Lazar
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++--
> dr
On Tue, Apr 8, 2025 at 4:47 AM jesse.zh...@amd.com wrote:
>
> Since KFD no longer registers its own callbacks for SDMA resets, and only KGD
> uses the reset mechanism,
> we can simplify the SDMA reset flow by directly calling the ring's
> `stop_queue` and `start_queue` functions.
> This patch re
On Wed, Apr 2, 2025 at 8:11 AM Sunil Khatri wrote:
>
> mes_userq_unmap could fail due to MES fw unable to
> unmap the queue and the return value needs is not
> to be ignored and handled on first step itself.
>
> Also queue->queue_active set to false in this function
> but only when the queue is re
Guo Yin
>
> At least from my point that patch seems to make a lot of sense, so feel free
> to add Reviewed-by: Christian König .
>
> But I would at least give Alex a chance to take a loop and double check.
Looks correct.
Acked-by: Alex Deucher
>
> Regards,
> Christia
ngine_reset_funcs` function, which was
> used to register the callbacks.
>- Removed the `sdma_v4_4_2_engine_reset_funcs` structure, which contained
> the pre-reset and post-reset callback functions.
>
> Signed-off-by: Jesse Zhang
Reviewed-by: Alex Deucher
> ---
> driver
On Wed, Apr 2, 2025 at 5:28 AM jesse.zh...@amd.com wrote:
>
> Since KFD no longer registers its own callbacks for SDMA resets, and only KGD
> uses the reset mechanism,
> we can simplify the SDMA reset flow by directly calling the ring's
> `stop_queue` and `start_queue` functions.
> This patch re
The structures are large and they do not require continuous
memory so use vzalloc.
Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4126
Cc: Aurabindo Pillai
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/displ
earing GPU
> memory between processes and maintains a consistent GPU state across KGD
> and KFD workloads.
>
> Cc: Mario Sopena-Novales
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/a
Use this to track the whether we want TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b818ad63dc84f..364a65524cfdb 100644
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 2474006b1a340..da67f27d65a33 100644
--- a/drivers/gpu/drm
Set up TMZ for queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 91d29f482c3ca..b204d0e6e816d 100644
--- a/drivers/gpu/drm
So we can track this when we create user queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
index fd0542f60433b
So that we initialize the MQD as a secure queue.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index f406a9a29bda5
Enable users to create secure GFX/compute queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu
Enable users to create queues at different priority levels.
The highest level is restricted to drm master.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
Handle the queue priority set by the user.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
If the queues needs to access TMZ surfaces, it must
be set up as secure.
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8719754c777b4..0ca4b3b961eb3 100644
Convert driver priority levels to MES11 priority levels.
At the moment they are the same, but they may not always
be.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Reuse the _pad field for flags.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 4 ++--
include/uapi/drm/amdgpu_drm.h | 5 -
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b
Convert driver priority levels to MES11 priority levels.
At the moment they are the same, but they may not always
be.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
compositors) (maps to MES AMD_PRIORITY_LEVEL_HIGH)
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 1a451907184cc..8719754c777b4 100644
--- a/include/uapi/drm
Move some userq fence handling code into amdgpu_userq_fence.c.
This matches the other code in that file.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 26 +++
.../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 +
drivers/gpu/drm/amd/amdgpu
Enforce isolation serializes access to the GFX IP. User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
Rename to map and umap to better align with what is happening
at the firmware level and remove the extra level of indirection
in the MES userq code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 10 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 8
This is unused so remove it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index abd32415d7343..e3c3fc160b799 100644
--- a
Add helpers to unmap and map user queues on suspend and
resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h | 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd
If userq creation fails, we need to properly unwind and free the
user queue fence driver.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd
Split out the queue map from the mqd create call and split
out the queue unmap from the mqd destroy call. This splits
the queue setup and teardown with the actual enablement
in the firmware.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 17
This will be used to stop/start user queue scheduling for
example when switching between kernel and user queues when
enforce isolation is enabled.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 66
since we loop through the queues |= the errors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index
Unmap user queues on suspend and map them on resume.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
Applied. Thanks!
Alex
On Mon, Apr 7, 2025 at 1:52 AM Alexandre Demers
wrote:
>
> The defines, shifts and masks are already available in dce_6_0_d.h,
> dce_6_0_sh_mask.h.
>
> Signed-off-by: Alexandre Demers
> ---
> drivers/gpu/drm/amd/amdgpu/si.c | 26 +-
> drivers/gpu
On Mon, Apr 7, 2025 at 4:15 PM Rodrigo Siqueira wrote:
>
> On 04/07, Alex Deucher wrote:
> > On Sun, Apr 6, 2025 at 7:07 PM Rodrigo Siqueira wrote:
> > >
> > > This patchset was inspired and made on top of the below series:
> > >
> > > https://
On Thu, Apr 10, 2025 at 1:33 PM Mario Limonciello
wrote:
>
> These have been announced so add them to the table.
>
> Link:
> https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-7-350.html
> Signed-off-by: Mario Limonciello
Acke
ons directly.
> v3: Firmware version checks only for Navi3x(by Alex).
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Cc: Shashank Sharma
> Cc: Sunil Khatri
> Signed-off-by: Arvind Yadav
Acked-by: Alex Deucher
For some reason I haven't gotten any of the 2/2 patches for a
On Thu, Apr 10, 2025 at 11:56 AM Yadav, Arvind wrote:
>
>
> On 4/10/2025 8:50 PM, Alex Deucher wrote:
> > On Thu, Apr 10, 2025 at 10:57 AM Arvind Yadav wrote:
> >> This patch is load usermode queue based on FW support for gfx11.
> >> CP Ucode FW version: [PFP =
s directly.
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Cc: Shashank Sharma
> Cc: Sunil Khatri
> Signed-off-by: Arvind Yadav
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/driv
On Thu, Apr 10, 2025 at 7:48 AM Arvind Yadav wrote:
>
> This patch is load usermode queue based on FW support for gfx12.
> CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Cc: Shashank Sharma
> Cc: Sunil
ops and checks by directly using the `ring->me` field
> to identify the SDMA instance.
>- Reused the `sdma_v5_0_gfx_stop` function to stop the queue, reducing code
> duplication.
>
> Signed-off-by: Jesse Zhang
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/am
Acked-by: Alex Deucher
On Wed, Apr 9, 2025 at 1:06 PM wrote:
>
> From: Roman Li
>
> [Why]
> htmldocs build warning: "Function parameter or struct member 'fused_io'
> not described in 'amdgpu_display_manager'".
>
> [How]
> Add missing des
possible division by 0 in fan handling
amdkfd:
- Queue reset fixes
Alex Deucher (5):
drm/amdgpu/mes11: optimize MES pipe FW version fetching
drm/amdgpu/pm: add workload profile pause helper
drm/amdgpu/pm/swsmu: implement
possible division by 0 in fan handling
amdkfd:
- Queue reset fixes
Alex Deucher (5):
drm/amdgpu/mes11: optimize MES pipe FW version fetching
drm/amdgpu/pm: add workload profile pause helper
drm/amdgpu/pm/swsmu: implement
On Wed, Apr 9, 2025 at 10:36 AM SRINIVASAN SHANMUGAM
wrote:
>
>
> On 4/8/2025 9:30 PM, Alex Deucher wrote:
> > Switch from a bool to an enum and allow more options
> > for enforce isolation. There are now 3 modes of operation:
> > - Disabled (0)
> > - Enabled
On Tue, Apr 8, 2025 at 11:30 AM Christian König
wrote:
>
> Otherwise triggering sysfs multiple times without other submissions in
> between only runs the shader once.
>
> v2: add some comment
> v3: re-add missing cast
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_g
.org/drm/amd/-/issues/4093
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --
On Fri, Mar 28, 2025 at 7:52 AM Prike Liang wrote:
>
> The MES queue deactivation and active status are already set in
> mes_userq_unmap|map(), so the caller needn't set the queue_active
> bit again.
>
> Signed-off-by: Prike Liang
Acked-by: Alex Deucher
> ---
>
Use the local setting rather than the global parameter.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 06b51867c9aac
.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 22 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++---
drivers/gpu/drm/amd
Use the local setting rather than the global parameter.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 8892858cfd9ae
Oh, sorry, I've picked it up now. Thanks!
Alex
On Tue, Apr 8, 2025 at 4:16 AM Denis Arefev wrote:
>
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > b/dr
Oh, sorry, I've picked it up now. Thanks!
Alex
On Tue, Apr 8, 2025 at 4:16 AM Denis Arefev wrote:
>
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > b/dr
- Removed redundant loops and checks by directly using the `ring->me`
> field
> to identify the SDMA instance.
> - Reused the `sdma_v5_2_gfx_stop` function to stop the queue,
> reducing code
> duplication.
>
> Signed-off-by: Jesse Zhang
Ac
tly manipulates the `GRBM_SOFT_RESET`
> register to reset the specified SDMA instance.
>
> 2. **Integration into `amdgpu_sdma_reset_engine`**:
>- The `amdgpu_sdma_soft_reset` function is called during the SDMA reset
> process, replacing the previous call to `amdgpu_dpm_reset_sdm
Applied. Thanks!
On Mon, Apr 7, 2025 at 10:42 AM Christian König
wrote:
>
> Am 07.04.25 um 16:18 schrieb Matthew Auld:
> > The page_link lower bits of the first sg could contain something like
> > SG_END, if we are mapping a single VRAM page or contiguous blob which
> > fits into one sg entry. R
Applied. Thanks!
On Fri, Apr 4, 2025 at 1:48 AM Alexandre Demers
wrote:
>
> Typos were found in DCE, where hpd should have been used.
>
> DCE6/8: standardize the "interrupt" vs "irq" usage in function names
> with DCE10/11.
>
> Alexandre Demers (2):
> drm/amdgpu: fix typos in DCEs
> drm/amdg
Applied. Thanks!
On Fri, Apr 4, 2025 at 1:43 AM Alexandre Demers
wrote:
>
> First patch moves some DCE files around so they are distributed as are
> other DCE files
>
> Second patch implements gmc_v6_0_set_clockgating_state(), which was mostly
> there, but commented out. A few tweeks were needed
On Sun, Apr 6, 2025 at 7:07 PM Rodrigo Siqueira wrote:
>
> This patchset was inspired and made on top of the below series:
>
> https://lore.kernel.org/amd-gfx/20250319162225.3775315-1-alexander.deuc...@amd.com/
>
> In the above series, there is a bug fix in many functions named
> gfx_vX_0_get_csb_
Ping on this series?
Alex
On Wed, Mar 26, 2025 at 1:52 PM Alex Deucher wrote:
>
> KIQ is replaced with MES on GFX 11 and newer.
>
> Signed-off-by: Alex Deucher
> ---
> Documentation/gpu/amdgpu/driver-core.rst | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletio
Ping?
Alex
On Fri, Mar 28, 2025 at 9:09 AM Alex Deucher wrote:
>
> Don't fetch it again if we already have it. It seems the
> registers don't reliably have the value at resume in some
> cases.
>
> Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block sup
On Mon, Apr 7, 2025 at 9:27 AM Khatri, Sunil wrote:
>
>
> On 4/7/2025 6:26 PM, Alex Deucher wrote:
>
> On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil wrote:
>
> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>
> ping on this series?
>
> Alex
>
> On Thu, Mar 20,
On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil wrote:
>
>
> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher
> wrote:
>
> In dev core dump, dump the full header fifo for
> each que
1 - 100 of 2085 matches
Mail list logo
