On Mon, Apr 7, 2025 at 9:27 AM Khatri, Sunil <sukha...@amd.com> wrote:
>
>
> On 4/7/2025 6:26 PM, Alex Deucher wrote:
>
> On Mon, Apr 7, 2025 at 6:14 AM Khatri, Sunil <sukha...@amd.com> wrote:
>
> On 3/25/2025 1:18 AM, Alex Deucher wrote:
>
> ping on this series?
>
> Alex
>
> On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <alexander.deuc...@amd.com>
> wrote:
>
> In dev core dump, dump the full header fifo for
> each queue. Each FIFO has 8 entries.
>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f4dfa1418b740..64342160ff7d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry
> gc_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> - /* cp header registers */
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> /* SE status registers */
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
> - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
> + /* packet headers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
>
> Reading this register in a loop will give value of each queue or we are
> reading same register again and again ?
>
> The register is an accessor for the header FIFO in the queue hardware.
> The FIFO is 8 entries deep so if you read the register 8 times, you
> can dump the full FIFO.
>
> Thanks for this information. I was kind of thinking the same but dint know it
> works directly and need not to change the way we read like setting grbm etc.
>
> for (i = 0; i < reg_count; i++)
> adev->gfx.ip_dump_core[i] =
> RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); With above loop arent we
> reading same offset again for
>
> mmCP_CE_HEADER_DUMP,mmCP_PFP_HEADER_DUMP and mmCP_ME_HEADER_DUMP 8 times. How
> are we making sure we are reading from different queues ?
>
> The me/pipes/queues are indexed via soc15_grbm_select().
>
> Alex
>
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)
> };
>
> static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
> @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry
> gc_cp_reg_list_9[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)
> };
>
> enum ta_ras_gfx_subblock {
> @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block
> *ip_block, struct drm_printer
> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe;
> k++) {
> drm_printf(p, "\nmec %d, pipe %d, queue
> %d\n", i, j, k);
> for (reg = 0; reg < reg_count; reg++) {
> - drm_printf(p, "%-50s \t 0x%08x\n",
> -
> gc_cp_reg_list_9[reg].reg_name,
> -
> adev->gfx.ip_dump_compute_queues[index + reg]);
> + if (i &&
> gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> + drm_printf(p, "%-50s \t
> 0x%08x\n",
> +
> "mmCP_MEC_ME2_HEADER_DUMP",
> +
> adev->gfx.ip_dump_compute_queues[index + reg]);
> + else
> + drm_printf(p, "%-50s \t
> 0x%08x\n",
> +
> gc_cp_reg_list_9[reg].reg_name,
> +
> adev->gfx.ip_dump_compute_queues[index + reg]);
> }
> index += reg_count;
> }
> @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block
> *ip_block)
> soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
>
> for (reg = 0; reg < reg_count; reg++) {
> -
> adev->gfx.ip_dump_compute_queues[index + reg] =
> - RREG32(SOC15_REG_ENTRY_OFFSET(
> -
> gc_cp_reg_list_9[reg]));
> + if (i &&
> gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
> +
> adev->gfx.ip_dump_compute_queues[index + reg] =
> +
> RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
> + else
> +
> adev->gfx.ip_dump_compute_queues[index + reg] =
> +
> RREG32(SOC15_REG_ENTRY_OFFSET(
> +
> gc_cp_reg_list_9[reg]));
>
> When value of (i != 0), arent we reading same register i.e
> mmCP_MEC_ME1_HEADER_DUMP 8 times, how are we making sure when we read it
> again its reading for another queue ?
>
> Regards
> Sunil Khatri
>
> I am assuming here also same explanation applies that when we read the same
> register again we are getting the next value in the queue but why use this
> value of offset mmCP_MEC_ME1_HEADER_DUMP but read the register
> mmCP_MEC_ME2_HEADER_DUMP ??
>
>
> For i=0, we are dumping mmCP_MEC_ME2_HEADER_DUMP but for value of i >0 we are
> dumping mmCP_MEC_ME1_HEADER_DUMP ? Is that because mmCP_MEC_ME1_HEADER_DUMP
> belongs to MEC1 i.e for mec0 and for i > 0 i.e MEC2 we need to read
> mmCP_MEC_ME2_HEADER_DUMP ?
>
Yes. There are different registers for each ME. ME0 uses
mmCP_[CE|PFP|ME]_HEADER_DUMP, ME1 uses mmCP_MEC_ME1_HEADER_DUMP and
ME2 uses mmCP_MEC_ME2_HEADER_DUMP.
Alex
> }
> index += reg_count;
> }
> --
> 2.49.0
>
