[PATCH 10/13] drm/amdgpu/gfx11: add support for TMZ queues to mqd_init

[Alex Deucher]

Set up TMZ for queues.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 91d29f482c3ca..b204d0e6e816d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4114,6 +4114,8 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device 
*adev, void *m,
 #ifdef __BIG_ENDIAN
        tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
 #endif
+       if (prop->tmz_queue)
+               tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
        mqd->cp_gfx_hqd_cntl = tmp;
 
        /* set up cp_doorbell_control */
@@ -4268,6 +4270,8 @@ static int gfx_v11_0_compute_mqd_init(struct 
amdgpu_device *adev, void *m,
                            prop->allow_tunneling);
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
+       if (prop->tmz_queue)
+               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-- 
2.49.0