On Fri, Apr 11, 2025 at 8:42 AM Lijo Lazar <lijo.la...@amd.com> wrote:
>
> Except HDP v5.2 all use a common logic for HDP flush. Use a generic
> function. HDP v5.2 forces NO_KIQ logic, revisit it later.
>
> Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | 21 +++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 13 +------------
> drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 13 +------------
> drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 13 +------------
> drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c | 13 +------------
> 6 files changed, 27 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
> index b6cf801939aa..7fd8f09c28e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
> @@ -22,6 +22,7 @@
> */
> #include "amdgpu.h"
> #include "amdgpu_ras.h"
> +#include <uapi/linux/kfd_ioctl.h>
>
> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
> {
> @@ -46,3 +47,23 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
> /* hdp ras follows amdgpu_ras_block_late_init_default for late init */
> return 0;
> }
> +
> +void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
> + struct amdgpu_ring *ring)
> +{
> + if (!ring || !ring->funcs->emit_wreg) {
> + WREG32((adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
> + 2,
> + 0);
> + RREG32((adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
> + 2);
> + } else {
> + amdgpu_ring_emit_wreg(ring,
> + (adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
> + 2,
> + 0);
> + }
> +}
> \ No newline at end of file
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
> index 7b8a6152dc8d..4cfd932b7e91 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
> @@ -44,4 +44,6 @@ struct amdgpu_hdp {
> };
>
> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);
> +void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
> + struct amdgpu_ring *ring);
> #endif /* __AMDGPU_HDP_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> index f1dc13b3ab38..e6c0d86d3486 100644
> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> @@ -36,17 +36,6 @@
> #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
> #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
>
> -static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
> - struct amdgpu_ring *ring)
> -{
> - if (!ring || !ring->funcs->emit_wreg) {
> - WREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - RREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
> - } else {
> - amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - }
> -}
> -
> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
> struct amdgpu_ring *ring)
> {
> @@ -180,7 +169,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {
> };
>
> const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
> - .flush_hdp = hdp_v4_0_flush_hdp,
> + .flush_hdp = amdgpu_hdp_generic_flush,
> .invalidate_hdp = hdp_v4_0_invalidate_hdp,
> .update_clock_gating = hdp_v4_0_update_clock_gating,
> .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
> b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
> index 43195c079748..8bc001dc9f63 100644
> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
> @@ -27,17 +27,6 @@
> #include "hdp/hdp_5_0_0_sh_mask.h"
> #include <uapi/linux/kfd_ioctl.h>
>
> -static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
> - struct amdgpu_ring *ring)
> -{
> - if (!ring || !ring->funcs->emit_wreg) {
> - WREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - RREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
> - } else {
> - amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - }
> -}
> -
> static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
> struct amdgpu_ring *ring)
> {
> @@ -217,7 +206,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device
> *adev)
> }
>
> const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
> - .flush_hdp = hdp_v5_0_flush_hdp,
> + .flush_hdp = amdgpu_hdp_generic_flush,
> .invalidate_hdp = hdp_v5_0_invalidate_hdp,
> .update_clock_gating = hdp_v5_0_update_clock_gating,
> .get_clock_gating_state = hdp_v5_0_get_clockgating_state,
> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
> index a88d25a06c29..ec20daf4272c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
> @@ -30,17 +30,6 @@
> #define regHDP_CLK_CNTL_V6_1 0xd5
> #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
>
> -static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
> - struct amdgpu_ring *ring)
> -{
> - if (!ring || !ring->funcs->emit_wreg) {
> - WREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - RREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
> - } else {
> - amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - }
> -}
> -
> static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> @@ -149,7 +138,7 @@ static void hdp_v6_0_get_clockgating_state(struct
> amdgpu_device *adev,
> }
>
> const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
> - .flush_hdp = hdp_v6_0_flush_hdp,
> + .flush_hdp = amdgpu_hdp_generic_flush,
> .update_clock_gating = hdp_v6_0_update_clock_gating,
> .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
> index 49f7eb4fbd11..ed1debc03507 100644
> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
> @@ -27,17 +27,6 @@
> #include "hdp/hdp_7_0_0_sh_mask.h"
> #include <uapi/linux/kfd_ioctl.h>
>
> -static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
> - struct amdgpu_ring *ring)
> -{
> - if (!ring || !ring->funcs->emit_wreg) {
> - WREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - RREG32((adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
> - } else {
> - amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset +
> KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> - }
> -}
> -
> static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> @@ -137,7 +126,7 @@ static void hdp_v7_0_get_clockgating_state(struct
> amdgpu_device *adev,
> }
>
> const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
> - .flush_hdp = hdp_v7_0_flush_hdp,
> + .flush_hdp = amdgpu_hdp_generic_flush,
> .update_clock_gating = hdp_v7_0_update_clock_gating,
> .get_clock_gating_state = hdp_v7_0_get_clockgating_state,
> };
> --
> 2.25.1
>
