Re: [PATCH v8 03/12] tools: mkeficapsule: add firmwware image signing

2022-01-17 Thread AKASHI Takahiro
Heinrich,

On Sat, Jan 01, 2022 at 10:50:40PM +0100, Heinrich Schuchardt wrote:
> On 12/20/21 06:02, AKASHI Takahiro wrote:
> 
> nits:
> There is a typo in the patch subject.
> 
> > With this enhancement, mkeficapsule will be able to sign a capsule
> > file when it is created. A signature added will be used later
> > in the verification at FMP's SetImage() call.
> > 
> > To do that, We need specify additional command parameters:
> 
> nits:
> %s/We/we/
> 
> >-monotonic-cout  : monotonic count
> >-private-key  : private key file
> >-certificate  : certificate file
> > Only when all of those parameters are given, a signature will be added
> > to a capsule file.
> > 
> > Users are expected to maintain and increment the monotonic count at
> > every time of the update for each firmware image.
> > 
> > Signed-off-by: AKASHI Takahiro 
> > Reviewed-by: Simon Glass 
> > Acked-by: Ilias Apalodimas 
> > ---
> >   tools/Makefile   |   4 +
> >   tools/eficapsule.h   | 115 +
> >   tools/mkeficapsule.c | 401 +++
> >   3 files changed, 484 insertions(+), 36 deletions(-)
> >   create mode 100644 tools/eficapsule.h
> > 
> > diff --git a/tools/Makefile b/tools/Makefile
> > index 766c0674f4a0..afca08e2941a 100644
> > --- a/tools/Makefile
> > +++ b/tools/Makefile
> > @@ -238,6 +238,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
> >   hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
> >   HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
> > 
> > +ifeq ($(CONFIG_TOOLS_LIBCRYPTO),y)
> > +HOSTLDLIBS_mkeficapsule += \
> > +   $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl 
> > -lcrypto")
> > +endif
> >   hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
> > 
> >   # We build some files with extra pedantic flags to try to minimize things
> > diff --git a/tools/eficapsule.h b/tools/eficapsule.h
> > new file mode 100644
> > index ..8c1560bb0671
> > --- /dev/null
> > +++ b/tools/eficapsule.h
> > @@ -0,0 +1,115 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2021 Linaro Limited
> > + * Author: AKASHI Takahiro
> > + *
> > + * derived from efi.h and efi_api.h to make the file POSIX-compliant
> 
> What is not POSIX compliant in efi.h and efi_api.h?
> Why can't you extract an include to avoid duplicate code?

Please read the past discussions[1] raised by Mark.
He claimed that mkeficapsule (v6 or earlier) didn't compile
on OpenBSD. He explained the root cause in [2].

Then I said that we'd better have a host-only include file
to address the issue[3]. There was no objection from you.

-Takahiro Akashi

[1] https://lists.denx.de/pipermail/u-boot/2021-November/465859.html
[2] https://lists.denx.de/pipermail/u-boot/2021-November/466163.html
[3] https://lists.denx.de/pipermail/u-boot/2021-November/467234.html

> > + */
> > +
> > +#ifndef _EFI_CAPSULE_H
> > +#define _EFI_CAPSULE_H
> > +
> > +#include 
> > +#include  /* WIN_CERTIFICATE */
> > +
> > +/*
> > + * Gcc's predefined attributes are not recognized by clang.
> > + */
> > +#ifndef __packed
> > +#define __packed   __attribute__((__packed__))
> > +#endif
> > +
> > +#ifndef __aligned
> > +#define __aligned(x)   __attribute__((__aligned__(x)))
> > +#endif
> 
> These defintions exist already in
> include/linux/compiler_attributes.h.
> 
> > +
> > +typedef struct {
> > +   uint8_t b[16];
> > +} efi_guid_t __aligned(8);
> > +
> 
> Please, avoid duplication of definitions.
> 
> Best regards
> 
> Heinrich
> 
> > +#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
> > +   {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \
> > +   ((a) >> 24) & 0xff, \
> > +   (b) & 0xff, ((b) >> 8) & 0xff, \
> > +   (c) & 0xff, ((c) >> 8) & 0xff, \
> > +   (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
> > +
> > +#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
> > +   EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
> > +0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
> > +
> > +#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
> > +   EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
> > +0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
> > +
> > +#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
> > +   EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
> > +0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
> > +
> > +#define EFI_CERT_TYPE_PKCS7_GUID \
> > +   EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \
> > +0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
> > +
> > +/* flags */
> > +#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET  0x0001
> > +
> > +struct efi_capsule_header {
> > +   efi_guid_t capsule_guid;
> > +   uint32_t header_size;
> > +   uint32_t flags;
> > +   uint32_t capsule_image_size;
> > +} __packed;
> > +
> > +struct efi_firmware_management_capsule_header {
> > +   uint32_t version;
> > +   uint16_t embedded_driver_count;
> > +   uint16_t payload_item_count;
> > +   uint32_t item_offset_lis

Re: [PATCH] Revert "net: gem: Disable broadcast setting"

2022-01-17 Thread Michal Simek
pá 14. 1. 2022 v 13:15 odesílatel Michal Simek  napsal:
>
> This reverts commit eafdcda4a854932c0319656de7bf3f017f17ae67.
>
> The main reason is that QEMU is using BOOTP protocol which is sending DHCP
> Offer to a broadcast address that's why it can't be disabled.
> DHCP protocol has no issue because it returns directly to client MAC
> address.
> Both of these options are described in RFC951
> (https://datatracker.ietf.org/doc/html/rfc951#section-4)
>
> Signed-off-by: Michal Simek 
> ---
>
>  drivers/net/zynq_gem.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index f238811786c6..3118d1472669 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -62,7 +62,6 @@
>  #define ZYNQ_GEM_NWCFG_SPEED1000x0001 /* 100 Mbps 
> operation */
>  #define ZYNQ_GEM_NWCFG_SPEED1000   0x0400 /* 1Gbps operation */
>  #define ZYNQ_GEM_NWCFG_FDEN0x0002 /* Full Duplex mode */
> -#define ZYNQ_GEM_NWCFG_NO_BRDC BIT(5) /* No broadcast */
>  #define ZYNQ_GEM_NWCFG_FSREM   0x0002 /* FCS removal */
>  #define ZYNQ_GEM_NWCFG_SGMII_ENBL  0x0800 /* SGMII Enable */
>  #define ZYNQ_GEM_NWCFG_PCS_SEL 0x0800 /* PCS select */
> @@ -80,7 +79,6 @@
>
>  #define ZYNQ_GEM_NWCFG_INIT(ZYNQ_GEM_DBUS_WIDTH | \
> ZYNQ_GEM_NWCFG_FDEN | \
> -   ZYNQ_GEM_NWCFG_NO_BRDC | \
> ZYNQ_GEM_NWCFG_FSREM | \
> ZYNQ_GEM_NWCFG_MDCCLKDIV)
>
> --
> 2.34.1
>

applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs


Re: [PATCH] net: gem: Workaround gmii2rgmii bridge DT node issue

2022-01-17 Thread Michal Simek
pá 14. 1. 2022 v 13:08 odesílatel Michal Simek  napsal:
>
> From: Ashok Reddy Soma 
>
> For configurations with gmii2rgmii and external phy the DT nodes link
> should be gem->gmii2rgmii->phy. But due to limitation in Linux driver
> the DT is mentioned as gem->phy and gmii2rgmii->phy as shown in below DT.
>
> ethernet@ff0c {
> compatible = "cdns,zynqmp-gem\0cdns,gem";
> status = "okay";
> interrupt-parent = <0x04>;
> interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
> reg = <0x00 0xff0c 0x00 0x1000>;
> clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
> #address-cells = <0x01>;
> #size-cells = <0x00>;
> #stream-id-cells = <0x01>;
> iommus = <0x0d 0x875>;
> power-domains = <0x0c 0x1e>;
> clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;
> phy-handle = <0x0e>;
> phy-mode = "gmii";
> xlnx,ptp-enet-clock = <0x00>;
> local-mac-address = [ff ff ff ff ff ff];
> phandle = <0x4d>;
>
> mdio {
> #address-cells = <0x01>;
> #size-cells = <0x00>;
> phandle = <0x4e>;
>
> ethernet-phy@1 {
> reg = <0x01>;
> rxc-skew-ps = <0x708>;
> txc-skew-ps = <0x708>;
> phandle = <0x0e>;
> };
>
> gmii_to_rgmii_0@8 {
> compatible = "xlnx,gmii-to-rgmii-1.0";
> phy-handle = <0x0e>;
> reg = <0x08>;
> phandle = <0x4f>;
> };
> };
> };
>
> Since same DT is used in Linux and U-Boot we need to workaround this
> issue by using the gmii2rgmii node which points to phy and we should
> ignore the gem pointing to phy directly.
>
> Do this workaround by updating priv->phydev->node value with
> priv->phy_of_node only if it is not valid node.
>
> Signed-off-by: Ashok Reddy Soma 
> Signed-off-by: Michal Simek 
> ---
>
>  drivers/net/zynq_gem.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index b751d28e611f..f238811786c6 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -338,7 +338,8 @@ static int zynq_phy_init(struct udevice *dev)
>   ADVERTISED_Asym_Pause;
>
> priv->phydev->advertising = priv->phydev->supported;
> -   priv->phydev->node = priv->phy_of_node;
> +   if (!ofnode_valid(priv->phydev->node))
> +   priv->phydev->node = priv->phy_of_node;
>
> return phy_config(priv->phydev);
>  }
> --
> 2.34.1
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs


Re: [PATCH] MAINTAINERS: Add watchdog maintainers entry

2022-01-17 Thread Harald Seiler
Hi Stefan,

On Thu, 2022-01-13 at 16:57 +0100, Stefan Roese wrote:
> I've been handling "inofficially" the watchdog related patches for a few
> years now. Let's make this official and add a tree for it and also add
> myself here in the MAINTAINERS file.

Your tree is online and you should have maintainer access to it.  Let me
know if you need anything else.

-- 
Harald

> Signed-off-by: Stefan Roese 
> Cc: Tom Rini 
> Cc: Harald Seiler 
> ---
>  MAINTAINERS | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6ae81c565943..b44651673d17 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1297,6 +1297,14 @@ F: include/virtio*.h
>  F:   test/dm/virtio.c
>  F:   doc/develop/driver-model/virtio.rst
>  
> +WATCHDOG
> +M:   Stefan Roese 
> +S:   Maintained
> +T:   git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git
> +F:   cmd/wdt.c
> +F:   drivers/watchdog/
> +F:   include/watchdog*.h
> +
>  X86
>  M:   Simon Glass 
>  M:   Bin Meng 


[PATCH v2] cmd: Add Kconfig option for multiprocessor cmds

2022-01-17 Thread Michal Simek
From: Ashok Reddy Soma 

Add Kconfig option(CONFIG_CMD_MP) to enable or disable multiprocessor
commands. Compile cmd/mp.c based on CONFIG_CMD_MP.

Signed-off-by: Ashok Reddy Soma 
Signed-off-by: Michal Simek 
---

Changes in v2:
- Move config MP to Kconfig (General setup menu)
- Fix description and s/support/Support/ to be consistent with other
  entries which also start with upper letter.
- all reported by trini

 Kconfig  |  6 ++
 cmd/Kconfig  | 11 ++-
 cmd/Makefile |  2 +-
 3 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/Kconfig b/Kconfig
index c46f4fce8625..b0e45cd236f0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -454,6 +454,12 @@ config SYS_SRAM_SIZE
default 0x1 if TARGET_TRICORDER
default 0x0
 
+config MP
+   bool "Support for multiprocessor"
+   help
+ This provides an option to bringup different processors
+ in multiprocessor cases.
+
 config EXAMPLES
bool "Compile API examples"
depends on !SANDBOX
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 5b30b13e438f..5f2668a5b173 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1820,12 +1820,13 @@ config CMD_SLEEP
help
  Delay execution for some time
 
-config MP
-   bool "support for multiprocessor"
+config CMD_MP
+   bool "support for multiprocessor commands"
+   depends on MP
+   default y
help
- This provides an option to brinup
- different processors in multiprocessor
- cases.
+ This enables commands to bringup different processors
+ in multiprocessor cases.
 
 config CMD_TIMER
bool "timer"
diff --git a/cmd/Makefile b/cmd/Makefile
index 891819ae0f6b..9e8074bb7e49 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -101,7 +101,7 @@ obj-$(CONFIG_CMD_MDIO) += mdio.o
 obj-$(CONFIG_CMD_SLEEP) += sleep.o
 obj-$(CONFIG_CMD_MMC) += mmc.o
 obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o
-obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_CMD_MP) += mp.o
 obj-$(CONFIG_CMD_MTD) += mtd.o
 obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
 obj-$(CONFIG_CMD_CLONE) += clone.o
-- 
2.34.1



Re: [PATCH] cmd: Add Kconfig option for multiprocessor cmds

2022-01-17 Thread Michal Simek




On 1/14/22 21:00, Tom Rini wrote:

On Fri, Jan 14, 2022 at 01:07:34PM +0100, Michal Simek wrote:


From: Ashok Reddy Soma 

Add Kconfig option(CONFIG_CMD_MP) to enable or disable multiprocessor
commands. Compile cmd/mp.c based on CONFIG_CMD_MP.

Signed-off-by: Ashok Reddy Soma 
Signed-off-by: Michal Simek 
---

  cmd/Kconfig  | 8 
  cmd/Makefile | 2 +-
  2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 5b30b13e438f..1e3eef4437b5 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1827,6 +1827,14 @@ config MP
  different processors in multiprocessor
  cases.
  
+config CMD_MP

+   bool "support for multiprocessor commands"
+   depends on MP
+   default y
+   help
+ This enables commands to bringup different processors
+ in multiprocessor cases.
+
  config CMD_TIMER
bool "timer"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 891819ae0f6b..9e8074bb7e49 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -101,7 +101,7 @@ obj-$(CONFIG_CMD_MDIO) += mdio.o
  obj-$(CONFIG_CMD_SLEEP) += sleep.o
  obj-$(CONFIG_CMD_MMC) += mmc.o
  obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o
-obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_CMD_MP) += mp.o
  obj-$(CONFIG_CMD_MTD) += mtd.o
  obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
  obj-$(CONFIG_CMD_CLONE) += clone.o


The problem is that there's already an entry for MP in cmd/Kconfig.  So
yes, it should be fixed for consistency, but the current entry
renamed/moved.  Thanks!


Consistency is one part. Second part is that MP code can be called without any 
command that's why having two symbols make sense.

Anyway I have sent v2 with moving MP to Kconfig.

Thanks,
Michal



Re: [RFC 1/1] efi_loader: rename 'efidebug boot' 'bootefi'

2022-01-17 Thread Heinrich Schuchardt

On 1/17/22 08:58, Ilias Apalodimas wrote:

On Mon, Jan 17, 2022 at 10:16:51AM +0900, AKASHI Takahiro wrote:

On Sat, Jan 15, 2022 at 01:49:07AM +0100, Heinrich Schuchardt wrote:

The efidebug command was conceived for testing purposes.


Well, I initially implemented the command as an alternative of
"EFI shell" as the shell was not able to run on EFI U-Boot at that time.


The manipulation of boot options does better fit to the bootefi command
that is used to invoke the boot manager.


I believe that it would be best to have those two features
in separate commands(/applications) since the bootefi/bootmgr be focused
on booting EFI images while efidebug/EFI shell provides a kind of
user interfaces for manipulating the system.

*If* you dare to move the code to bootefi/bootmgr, I'd ask you to honor
and add my copyright to the file as "efidebug boot" feature is a core part
of efidebug. Or export sub-command functions from efidebug.c and import
them in bootefi.c.


I think renaming the efidebug command is overall good idea,  since it does
way more that debugging.  OTOH I think moving it to 'bootefi' is the wrong
way to go.  I'd be much happier if we kept bootefi for booting related
commands and purposes and rename 'efidebug' to 'efi'.  Then we could split
off the debug related commands to 'efi debug x' and put it under a
Kconfig option.


For me the important thing is that we should be able enable boot options 
related commands without the rest of efidebug to limit code size increase.


efidebug boot is only needed if CONFIG_CMD_BOOTEFI_BOOTMGR=y.

efidebug capsule is only needed for testing on QEMU, Sandbox if capsules 
are enabled. I can't see that a normal user would ever use it.


efidebug devices, drivers, dh, images, memmap, query, tables is only 
needed for debugging and should be disabled by default.


efidebug test is only needed on the Sandbox.

All commands lack documentation in /doc/usage/

Best regards

Heinrich


Re: [RFC 1/1] efi_loader: rename 'efidebug boot' 'bootefi'

2022-01-17 Thread Ilias Apalodimas
Hi Heinrich

On Mon, Jan 17, 2022 at 10:25:01AM +0100, Heinrich Schuchardt wrote:
> On 1/17/22 08:58, Ilias Apalodimas wrote:
> > On Mon, Jan 17, 2022 at 10:16:51AM +0900, AKASHI Takahiro wrote:
> > > On Sat, Jan 15, 2022 at 01:49:07AM +0100, Heinrich Schuchardt wrote:
> > > > The efidebug command was conceived for testing purposes.
> > > 
> > > Well, I initially implemented the command as an alternative of
> > > "EFI shell" as the shell was not able to run on EFI U-Boot at that time.
> > > 
> > > > The manipulation of boot options does better fit to the bootefi command
> > > > that is used to invoke the boot manager.
> > > 
> > > I believe that it would be best to have those two features
> > > in separate commands(/applications) since the bootefi/bootmgr be focused
> > > on booting EFI images while efidebug/EFI shell provides a kind of
> > > user interfaces for manipulating the system.
> > > 
> > > *If* you dare to move the code to bootefi/bootmgr, I'd ask you to honor
> > > and add my copyright to the file as "efidebug boot" feature is a core part
> > > of efidebug. Or export sub-command functions from efidebug.c and import
> > > them in bootefi.c.
> > 
> > I think renaming the efidebug command is overall good idea,  since it does
> > way more that debugging.  OTOH I think moving it to 'bootefi' is the wrong
> > way to go.  I'd be much happier if we kept bootefi for booting related
> > commands and purposes and rename 'efidebug' to 'efi'.  Then we could split
> > off the debug related commands to 'efi debug x' and put it under a
> > Kconfig option.
> 
> For me the important thing is that we should be able enable boot options
> related commands without the rest of efidebug to limit code size increase.
> 

Yes,  but isn't that doable by what I suggested?

> efidebug boot is only needed if CONFIG_CMD_BOOTEFI_BOOTMGR=y.
> 
> efidebug capsule is only needed for testing on QEMU, Sandbox if capsules are
> enabled. I can't see that a normal user would ever use it.
> 
> efidebug devices, drivers, dh, images, memmap, query, tables is only needed
> for debugging and should be disabled by default.


Yes,  those would be the options we could place under a new Kconfig, which 
enables
debugging capabilities on the command

Cheers
/Ilias
> 
> efidebug test is only needed on the Sandbox.
> 
> All commands lack documentation in /doc/usage/
> 
> Best regards
> 
> Heinrich


Re: [PATCH] env: fat: Add new lines at the end of print statements

2022-01-17 Thread AKASHI Takahiro
On Sun, Jan 02, 2022 at 11:38:35AM +, Peter Robinson wrote:
> Add some new line feeds at the end of print messages to make things
> easier to read on the console. The other env options do this so
> this is just an omission for FAT env.
> 
> Signed-off-by: Peter Robinson 
> ---
>  env/fat.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/env/fat.c b/env/fat.c
> index 9d37d26f9e..fdccd6cd2a 100644
> --- a/env/fat.c
> +++ b/env/fat.c
> @@ -77,7 +77,7 @@ static int env_fat_save(void)
>* This printf is embedded in the messages from env_save that
>* will calling it. The missing \n is intentional.
>*/

It would be better to remove the comment above as well.

-Takahiro Akashi

> - printf("Unable to use %s %d:%d... ",
> + printf("Unable to use %s %d:%d... \n",
>  CONFIG_ENV_FAT_INTERFACE, dev, part);
>   return 1;
>   }
> @@ -93,7 +93,7 @@ static int env_fat_save(void)
>* This printf is embedded in the messages from env_save that
>* will calling it. The missing \n is intentional.
>*/
> - printf("Unable to write \"%s\" from %s%d:%d... ",
> + printf("Unable to write \"%s\" from %s%d:%d... \n",
>   file, CONFIG_ENV_FAT_INTERFACE, dev, part);
>   return 1;
>   }
> @@ -135,7 +135,7 @@ static int env_fat_load(void)
>* This printf is embedded in the messages from env_save that
>* will calling it. The missing \n is intentional.
>*/
> - printf("Unable to use %s %d:%d... ",
> + printf("Unable to use %s %d:%d... \n",
>  CONFIG_ENV_FAT_INTERFACE, dev, part);
>   goto err_env_relocate;
>   }
> @@ -153,7 +153,7 @@ static int env_fat_load(void)
>* This printf is embedded in the messages from env_save that
>* will calling it. The missing \n is intentional.
>*/
> - printf("Unable to read \"%s\" from %s%d:%d... ",
> + printf("Unable to read \"%s\" from %s%d:%d... \n",
>   CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, 
> part);
>   goto err_env_relocate;
>   }
> -- 
> 2.33.1
> 


Re: imx8mm-evk does not boot kernel 5.16

2022-01-17 Thread Frieder Schrempf
On 14.01.22 20:44, Fabio Estevam wrote:
> Hi Marcel,
> 
> On Fri, Jan 14, 2022 at 3:10 PM Marcel Ziswiler
>  wrote:
> 
>> Strange, remember, I am working on Verdin iMX8M Mini support [1] and run 
>> that stuff more or less daily.
>> However, as you can see in that patch series, I build the imx-sdma driver 
>> now as a module just like already
>> merged for imx_v6_v7_defconfig. As I also do have an imx8mm-evk laying 
>> around somewhere I can give that a try
>> as well. I keep you posted...
> 
> Just noticed that when using the TF-A from NXP: imx-atf branch:
> imx_5.4.47_2.2.0 the 5.16 kernel boots fine.
> 
> When using the mainline TF-A  (v2.5 or v2.6) the board hangs with 5.16

I remember having lockup issues with the mainline TF-A and i.MX8MM when
it came to power domain handling (with older kernels and preliminary
power domain support). I never tracked this down, but switched to the
NXP TF-A for the time being.

IIRC the mainline TF-A doesn't enable the USB power domains per default,
while the NXP TF-A does and there are probably other differences. With
the latest GPCv2 and BLK-CTRL code in the kernel it should work either
way, but there still might be some unresolved problems.


Re: [PATCH v3] pci: Work around PCIe link training failures

2022-01-17 Thread Maciej W. Rozycki
On Sat, 15 Jan 2022, Tom Rini wrote:

> > Keep the 2.5GT/s speed restriction then, conservatively, if functional 
> > once applied.
> > 
> > Signed-off-by: Maciej W. Rozycki 
> > Reviewed-by: Stefan Roese 
> 
> Applied to u-boot/master, thanks!

 Great, thank you all for input and reviews!

  Maciej


[PATCH] imx: ventana: correct splashimage load address

2022-01-17 Thread Andrey Zhizhikin
Commit 72d81360aabd ("global: Convert CONFIG_LOADADDR to
CONFIG_SYS_LOADADDR") dropped the usage of LOADADDR and replaced it with
SYS_LOADADDR.

Use the correct macro in environment by replacing CONFIG_LOADADDR with
CONFIG_SYS_LOADADDR.

Fixes: d75ebf3482c3 ("imx: ventana: fix splash logo drawing")
Signed-off-by: Andrey Zhizhikin 
Cc: Tim Harvey 
---
 include/configs/gw_ventana.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 513b2d4679..acd495f234 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -105,7 +105,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"splashpos=m,m\0" \
-   "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+   "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \

base-commit: d71dbe657c3c22f50ecb3df133e5cdd884daae7d
-- 
2.25.1



Re: [PATCH] efidebug: avoid 'dfu_alt_info not defined' message

2022-01-17 Thread Heinrich Schuchardt

On 1/17/22 01:45, AKASHI Takahiro wrote:

On Sat, Jan 15, 2022 at 02:18:21AM +0100, Heinrich Schuchardt wrote:

If variable dfu_alt_info is not defined duplicate messages are displayed.

 => efidebug boot dump
 Scanning disk mmc2.blk...
 Scanning disk mmc1.blk...
 Scanning disk mmc0.blk...
 Found 3 disks
 No EFI system partition
 "dfu_alt_info" env variable not defined!
 Probably dfu_alt_info not defined
 "dfu_alt_info" env variable not defined!
 Probably dfu_alt_info not defined

Remove the 'Probably dfu_alt_info not defined' message.
Instead write a warning if the variable contains no entities.

Signed-off-by: Heinrich Schuchardt 
---
  lib/efi_loader/efi_firmware.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index a1b88dbfc2..519a47267c 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -128,8 +128,11 @@ static efi_status_t efi_get_dfu_info(
size_t names_len, total_size;
int dfu_num, i;
u16 *name, *next;
+   int ret;
  
-	dfu_init_env_entities(NULL, NULL);

+   ret = dfu_init_env_entities(NULL, NULL);
+   if (ret)
+   return EFI_SUCCESS;


Do you want to return EFI_SUCCESS here?
It is mandatory that "dfu_alt_info" be defined so that the current
FMP drivers should work.
So if the variable is not defined, I think,
efi_firmware_[fit|raw]_get_image_info() should fail.
Even if it returns EFI_SUCCESS, descriptor_count should be set to zero.


This patch did not change the return value. It only removed superfluous 
messages that I saw everytime I used the sandbox.


For dfu_num == 0 we are returning EFI_SUCCESS. If the number is 0 due to 
the content of dfu_alt_info or due to its absence, should not make a 
difference in the return code. Writing a message if dfu_alt_info exists 
but contains no entity seems reasonable.


If you think EFI_SUCCESS is not correct in both cases, please, send a 
followup patch for review.


Best regards

Heinrich



-Takahiro Akashi


names_len = 0;
dfu_num = 0;
@@ -138,7 +141,7 @@ static efi_status_t efi_get_dfu_info(
dfu_num++;
}
if (!dfu_num) {
-   log_warning("Probably dfu_alt_info not defined\n");
+   log_warning("No entities in dfu_alt_info\n");
*image_info_size = 0;
dfu_free_entities();
  
--

2.33.1





RE: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision

2022-01-17 Thread Moti Buskila
Hi Assaf,
I've got this email a few days ago.
Is it related to what you’ve send me? 
Thanks


-Original Message-
From: Marek Behún  
Sent: Wednesday, January 12, 2022 6:07 PM
To: Stefan Roese ; Mario Six ; Dennis Gilmore 
; Kostya Porotchkin 
Cc: Pali Rohár ; u-boot@lists.denx.de; Moti Buskila 
; Marek Behún 
Subject: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX 
state decision

External Email

--
From: Marek Behún 

This is a cleaned up and fixed version of a patch
  mv_ddr: a380: fix SPLIT_OUT_MIX state decision

  in each pattern cycle the bus state can be changed
  in order to avoide it, need to back to the same bus state on each
  pattern cycle
by
  Moti Boskula 

The original patch is not in Marvell's mv-ddr-marvell repository. It was gives 
to us by Marvell to fix an issues with DDR training on some boards, but it 
cannot be applied as is to mv-ddr-marvell, because it is a very dirty draft 
patch that would certainly break other things, mainly
DDR4 training code in mv-ddr-marvell, since it changes common functions.

I have cleaned up the patch and removed stuff that seemed unnecessary (when 
removed, it still fixed things). Note that I don't understand completely what 
the code does exactly, since I haven't studied the DDR training code 
extensively (and I suspect that no one besides some few people in Marvell 
understand the code completely).

Anyway after the cleanup the patch still fixes isssues with DDR training on the 
failing boards.

There was also a problem with the original patch on some of the Allied Telesis' 
x530 boards, reported by Chris Packham. I have asked Chris to send me some 
logs, and managed to fix it:
- if you look at the change, you'll notice that it introduces
  subtraction of cur_start_win[] and cur_end_win[] members, depending on
  a bit set in the current_byte_status variable
- the original patch subtracted cur_start_win[] if either
  BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
  subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
  was set
- from Chris Packham logs I discovered that the x530 board where the
  original patch introduced DDR training failure, only the
  BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
  patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
  current_byte_status variable
- this led me to the hypothesis that both cur_start_win[] and
  cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
  set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
- this hypothesis also gains credibility when considering the commit
  title ("fix SPLIT_OUT_MIX state decision")

Hopefully this will fix things without breaking anything else.

Signed-off-by: Marek Behún 
---
 .../a38x/ddr3_training_centralization.c   | 26 +++
 1 file changed, 26 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c 
b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
index 648b37ef6f..42308b6965 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
@@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
u32 if_id, pattern_id, bit_id;
u8 bus_id;
+   u8 current_byte_status;
u8 cur_start_win[BUS_WIDTH_IN_BITS];
u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
u8 cur_end_win[BUS_WIDTH_IN_BITS];
@@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
  result[search_dir_id][7]));
}
 
+   current_byte_status =
+   
mv_ddr_tip_sub_phy_byte_status_get(if_id,
+  
bus_id);
+
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
 bit_id++) {
/* check if this code is valid for 2 
edge, probably not :( */ @@ -174,11 +179,32 @@ static int 
ddr3_tip_centralization(u32 dev_num, u32 mode)
   [HWS_LOW2HIGH]
   [bit_id],
   EDGE_1);
+   if (current_byte_status &
+   BYTE_SPLIT_OUT_MIX) {
+   if (cur_start_win[bit_id] >= 64)
+   cur_start_win[bit_id] 
-= 64;
+   else
+

Re: [PATCH] pinctrl: single: add support for pinctrl-single, pins when #pinctrl-cells = 2

2022-01-17 Thread Anthony Bagwell
Thank you for the review. Sorry I forgot to add the sign off. Here is my 
signoff line.

Signed-off-by: Anthony Bagwell 

On 14/01/2022, 18:17, "Tom Rini"  wrote:

On Fri, Dec 03, 2021 at 03:18:53PM +, AJ Bagwell wrote:

> Changes to the am33xx device (33e9021a) trees have been merged in from
> the upstream linux kernel which now means the device tree uses the new
> pins format (as of 5.10) where the confinguration can be stores as a
> separate configuration value and pin mux mode which are then OR'd
> together.
>
> This patch adds support for the new format to u-boot so that
> pinctrl-cells is now respected when reading in pinctrl-single,pins
> ---
>  drivers/pinctrl/pinctrl-single.c | 55 +---
>  1 file changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c 
b/drivers/pinctrl/pinctrl-single.c
> index 8fc07e3498..bc9c17bce8 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -28,6 +28,7 @@ struct single_pdata {
>   int offset;
>   u32 mask;
>   u32 width;
> + u32 args_count;
>   bool bits_per_mux;
>  };
>
> @@ -78,20 +79,6 @@ struct single_priv {
>   struct list_head gpiofuncs;
>  };
>
> -/**
> - * struct single_fdt_pin_cfg - pin configuration
> - *
> - * This structure is used for the pin configuration parameters in case
> - * the register controls only one pin.
> - *
> - * @reg: configuration register offset
> - * @val: configuration register value
> - */
> -struct single_fdt_pin_cfg {
> - fdt32_t reg;
> - fdt32_t val;
> -};
> -
>  /**
>   * struct single_fdt_bits_cfg - pin configuration
>   *
> @@ -314,25 +301,28 @@ static int single_pin_compare(const void *s1, const 
void *s2)
>   * @dev: Pointer to single pin configuration device which is the parent 
of
>   *   the pins node holding the pin configuration data.
>   * @pins: Pointer to the first element of an array of register/value 
pairs
> - *of type 'struct single_fdt_pin_cfg'. Each such pair describes 
the
> - *the pin to be configured and the value to be used for 
configuration.
> + *of type 'u32'. Each such pair describes the pin to be 
configured
> + *and the value to be used for configuration.
> + *The value can either be a simple value if #pinctrl-cells = 1
> + *or a configuration value and a pin mux mode value if it is 2
>   *This pointer points to a 'pinctrl-single,pins' property in the
>   *device-tree.
>   * @size: Size of the 'pins' array in bytes.
> - *The number of register/value pairs in the 'pins' array 
therefore
> - *equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
> + *The number of cells in the array therefore equals to
> + *'size / sizeof(u32)'.
>   * @fname: Function name.
>   */
>  static int single_configure_pins(struct udevice *dev,
> -  const struct single_fdt_pin_cfg *pins,
> +  const u32 *pins,
>int size, const char *fname)
>  {
>   struct single_pdata *pdata = dev_get_plat(dev);
>   struct single_priv *priv = dev_get_priv(dev);
> - int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
> + int stride = pdata->args_count + 1;
> + int n, pin, count = size / sizeof(u32);
>   struct single_func *func;
>   phys_addr_t reg;
> - u32 offset, val;
> + u32 offset, val, mux;
>
>   /* If function mask is null, needn't enable it. */
>   if (!pdata->mask)
> @@ -344,16 +334,22 @@ static int single_configure_pins(struct udevice 
*dev,
>
>   func->name = fname;
>   func->npins = 0;
> - for (n = 0; n < count; n++, pins++) {
> - offset = fdt32_to_cpu(pins->reg);
> + for (n = 0; n < count; n += stride) {
> + offset = fdt32_to_cpu(pins[n]);
>   if (offset > pdata->offset) {
>   dev_err(dev, "  invalid register offset 0x%x\n",
>   offset);
>   continue;
>   }
>
> + /* if the pinctrl-cells is 2 then the second cell contains the 
mux */
> + if (stride == 3)
> + mux = fdt32_to_cpu(pins[n + 2]);
> + else
> + mux = 0;
> +
>   reg = pdata->base + offset;
> - val = fdt32_to_cpu(pins->val) & pdata->mask;
> + val = (fdt32_to_cpu(pins[n + 1]) | mux) & pdata->mask;
>   pin = single_get_pin_by_offset(dev, offset);
>   if (pin < 0) {
>   dev_err(dev, "  failed to get pin by offset %x\n",
> @@ -453,7 +449,7 @@ static int single_configure_b

Re: [PATCH v2 11/20] board: ti: j721s2: Add board support for J721S2

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 12:12:38PM +0530, Aswath Govindraju wrote:
> Hi Tom,
> 
> On 13/01/22 7:46 pm, Tom Rini wrote:
> > On Tue, Jan 11, 2022 at 01:25:36PM +0530, Aswath Govindraju wrote:
> > 
> >> From: David Huang 
> >>
> >> Add board support for J721S2 SoC.
> >>
> >> Signed-off-by: David Huang 
> >> Signed-off-by: Aswath Govindraju 
> > [snip]
> >> diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
> >> new file mode 100644
> >> index ..1afa6e057571
> >> --- /dev/null
> >> +++ b/board/ti/j721s2/MAINTAINERS
> >> @@ -0,0 +1,7 @@
> >> +J721S2 BOARD
> >> +M:Aswath Govindraju 
> >> +S:Maintained
> >> +F:board/ti/j721s2
> >> +F:include/configs/j721s2_evm.h
> >> +F:configs/j721s2_evm_r5_defconfig
> >> +F:configs/j721s2_evm_a72_defconfig
> > 
> > Please pick up the dts files as well.
> > 
> 
> The dts files have not been added by this patch. May I know if I would
> need to add a separate patch for this after adding the dts files?

No, just add everything that'll be in MAINTAINERS when you add the file
please.

-- 
Tom


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Re: [PATCH v2 01/20] remoteproc: k3_system_controller: Support optional boot_notification channel

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 12:22:52PM +0530, Aswath Govindraju wrote:
> Hi Tom,
> 
> On 17/01/22 11:01 am, Aswath Govindraju wrote:
> > Hi Tom,
> > 
> > On 13/01/22 7:42 pm, Tom Rini wrote:
> >> On Tue, Jan 11, 2022 at 01:25:26PM +0530, Aswath Govindraju wrote:
> >>
> >>> From: Nishanth Menon 
> >>>
> >>> If there is an optional boot notification channel that an SoC uses
> >>> separate from the rx path, use the same.
> >>>
> >>> Signed-off-by: Nishanth Menon 
> >>> ---
> >>>  .../remoteproc/k3-system-controller.txt   |  3 +++
> >>>  drivers/remoteproc/k3_system_controller.c | 20 ++-
> >>>  2 files changed, 22 insertions(+), 1 deletion(-)
> >>
> >> Binding docs are rst these days, so we should sync with upstream and
> >> then this property is already there, right?
> >>
> > 
> > I will create a followup patch to convert documentation to rst. Also,
> > about the property, mbox-names property is already present but
> > "boot_notify" is a newly added channel and not are required property.
> > So, this was additionally added.
> > 
> 
> One more question regarding documentation, should it be changed to rst
> or yaml, as this is a device tree binding?

I mis-spoke, yeah.  It should be yaml and pushed upstream first, then
brought back here.

-- 
Tom


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Re: [PATCH v4 01/13] imx: Don't define __ASSEMBLY__ in C files

2022-01-17 Thread Tom Rini
On Sun, Jan 16, 2022 at 01:19:25PM -0700, Simon Glass wrote:

> This is supposed to be a build-system flag. Move it there so we can
> define it before linux/kconfig.h is included.
> 
> Signed-off-by: Simon Glass 

These aren't "C" files, they're DCD files.  I think we can move the
define as you're suggesting but the subject is wrong is all.

-- 
Tom


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[PATCH v3] drivers: spi-nor: Add JEDEC id for W25Q16JV

2022-01-17 Thread Angus Ainslie
Add a JEDEC id for the Winbond W25Q16JV 16M-BIT serial flash memory with
DUAL/QUAD SPI

Changes since v2:

Chagned the name to follow "DTR" parts

Changes since v1:

Updated the name for more suffixes 

Signed-off-by: Angus Ainslie 
---
 drivers/mtd/spi/spi-nor-ids.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index b551ebd75e..08e386fbf5 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -314,6 +314,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+   {
+   INFO("w25q16jvm", 0xef7015, 0, 64 * 1024,  32,
+   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+   },
{
INFO("w25q32jv", 0xef7016, 0, 64 * 1024,  64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-- 
2.25.1



[PATCH v2] spl: add support for custom boot method names

2022-01-17 Thread Heiko Thiery
Currently the names MMC1, MMC2 and MMC2_2 are output in the SPL. To
achieve more userbility here the name of the boot source can be returned.
E.g. for "MMC1" -> "eMMC" or "MMC2" -> "SD card".

Signed-off-by: Heiko Thiery 
Reviewed-by: Michael Walle 
Tested-by: Michael Walle 
---
v2:
 - add function documenation


 common/spl/spl.c |  5 +
 include/spl.h| 16 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4c101ec5d3..b7b53f352e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -174,6 +174,11 @@ __weak void spl_board_prepare_for_optee(void *fdt)
 {
 }
 
+__weak const char *spl_board_loader_name(u32 boot_device)
+{
+   return NULL;
+}
+
 #if CONFIG_IS_ENABLED(OPTEE_IMAGE)
 __weak void __noreturn jump_to_image_optee(struct spl_image_info *spl_image)
 {
diff --git a/include/spl.h b/include/spl.h
index 0af0ee3003..e7b2ef0693 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -459,6 +459,18 @@ void spl_board_prepare_for_boot(void);
 int spl_board_ubi_load_image(u32 boot_device);
 int spl_board_boot_device(u32 boot_device);
 
+/**
+ * spl_board_loader_name() - Return a name for the loader
+ *
+ * This is a weak function which might be overridden by the board code. With
+ * that a board specific value for the device where the U-Boot will be loaded
+ * from can be set. By default it returns NULL.
+ *
+ * @boot_device:   ID of the device which the MMC driver wants to load
+ * U-Boot from.
+ */
+const char *spl_board_loader_name(u32 boot_device);
+
 /**
  * jump_to_image_linux() - Jump to a Linux kernel from SPL
  *
@@ -541,7 +553,9 @@ struct spl_image_loader {
 static inline const char *spl_loader_name(const struct spl_image_loader 
*loader)
 {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   return loader->name;
+   const char *name;
+   name = spl_board_loader_name(loader->boot_device);
+   return name ?: loader->name;
 #else
return NULL;
 #endif
-- 
2.30.2



[PATCH] spl: spl_sdp: don't call board_usb_init twice

2022-01-17 Thread Angus Ainslie
When CONFIG_DM_USB is not defined then usb_gadget_initialize is just a call
to board_usb_init. Calling board_usb_init twice causes the USB to fail so
make sure the second invocation is not compiled in when CONFIG_DM_USB is
not defined.

Signed-off-by: Angus Ainslie 
---
 common/spl/spl_sdp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c
index ae9c09883a..2a2bc8475d 100644
--- a/common/spl/spl_sdp.c
+++ b/common/spl/spl_sdp.c
@@ -17,7 +17,8 @@ static int spl_sdp_load_image(struct spl_image_info 
*spl_image,
int ret;
const int controller_index = CONFIG_SPL_SDP_USB_DEV;
 
-   usb_gadget_initialize(controller_index);
+   if (IS_ENABLED(CONFIG_DM_USB))
+   usb_gadget_initialize(controller_index);
 
board_usb_init(0, USB_INIT_DEVICE);
 
-- 
2.25.1



[PATCH] pinctrl: nxp: don't automatically select DEVRES

2022-01-17 Thread Angus Ainslie
If we select DEVRES here then it breaks building an imx8m SPL without
DEVRES support.

Signed-off-by: Angus Ainslie 
---
 drivers/pinctrl/nxp/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 4fb0916a37..3657e9deb9 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -92,7 +92,6 @@ config PINCTRL_IMX8
 config PINCTRL_IMX8M
bool "IMX8M pinctrl driver"
depends on ARCH_IMX8M && PINCTRL_FULL
-   select DEVRES
select PINCTRL_IMX
help
  Say Y here to enable the imx8m pinctrl driver
-- 
2.25.1



Re: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision

2022-01-17 Thread Marek Behún
Hello Moti,

since you're the author of the original version of this patch, could
you please review it and if it is okay, put it into mv-ddr-marvell?

Thanks.

Marek

On Mon, 17 Jan 2022 06:52:08 +
Moti Buskila  wrote:

> Hi Assaf,
> I've got this email a few days ago.
> Is it related to what you’ve send me? 
> Thanks
> 
> 
> -Original Message-
> From: Marek Behún  
> Sent: Wednesday, January 12, 2022 6:07 PM
> To: Stefan Roese ; Mario Six ; Dennis 
> Gilmore ; Kostya Porotchkin 
> Cc: Pali Rohár ; u-boot@lists.denx.de; Moti Buskila 
> ; Marek Behún 
> Subject: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX 
> state decision
> 
> External Email
> 
> --
> From: Marek Behún 
> 
> This is a cleaned up and fixed version of a patch
>   mv_ddr: a380: fix SPLIT_OUT_MIX state decision
> 
>   in each pattern cycle the bus state can be changed
>   in order to avoide it, need to back to the same bus state on each
>   pattern cycle
> by
>   Moti Boskula 
> 
> The original patch is not in Marvell's mv-ddr-marvell repository. It was 
> gives to us by Marvell to fix an issues with DDR training on some boards, but 
> it cannot be applied as is to mv-ddr-marvell, because it is a very dirty 
> draft patch that would certainly break other things, mainly
> DDR4 training code in mv-ddr-marvell, since it changes common functions.
> 
> I have cleaned up the patch and removed stuff that seemed unnecessary (when 
> removed, it still fixed things). Note that I don't understand completely what 
> the code does exactly, since I haven't studied the DDR training code 
> extensively (and I suspect that no one besides some few people in Marvell 
> understand the code completely).
> 
> Anyway after the cleanup the patch still fixes isssues with DDR training on 
> the failing boards.
> 
> There was also a problem with the original patch on some of the Allied 
> Telesis' x530 boards, reported by Chris Packham. I have asked Chris to send 
> me some logs, and managed to fix it:
> - if you look at the change, you'll notice that it introduces
>   subtraction of cur_start_win[] and cur_end_win[] members, depending on
>   a bit set in the current_byte_status variable
> - the original patch subtracted cur_start_win[] if either
>   BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
>   subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
>   was set
> - from Chris Packham logs I discovered that the x530 board where the
>   original patch introduced DDR training failure, only the
>   BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
>   patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
>   current_byte_status variable
> - this led me to the hypothesis that both cur_start_win[] and
>   cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
>   set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
> - this hypothesis also gains credibility when considering the commit
>   title ("fix SPLIT_OUT_MIX state decision")
> 
> Hopefully this will fix things without breaking anything else.
> 
> Signed-off-by: Marek Behún 
> ---
>  .../a38x/ddr3_training_centralization.c   | 26 +++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c 
> b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> index 648b37ef6f..42308b6965 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> @@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
>   enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
>   u32 if_id, pattern_id, bit_id;
>   u8 bus_id;
> + u8 current_byte_status;
>   u8 cur_start_win[BUS_WIDTH_IN_BITS];
>   u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
>   u8 cur_end_win[BUS_WIDTH_IN_BITS];
> @@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
> result[search_dir_id][7]));
>   }
>  
> + current_byte_status =
> + 
> mv_ddr_tip_sub_phy_byte_status_get(if_id,
> +
> bus_id);
> +
>   for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
>bit_id++) {
>   /* check if this code is valid for 2 
> edge, probably not :( */ @@ -174,11 +179,32 @@ static int 
> ddr3_tip_centralization(u32 dev_num, u32 mode)
>  [HWS_LOW2HIGH]
>  [bit_id],
>  EDGE_1);
> +  

Re: [PATCH v4 03/13] mmc: fsl: Use brackets around if()

2022-01-17 Thread Minkyu Kang
Hi!

2022년 1월 17일 (월) 08:50, Jaehoon Chung 님이 작성:

> On 1/17/22 5:19 AM, Simon Glass wrote:
> > At present the IS_ENABLED() macro has extra brackets, making it possible
> > to write:
> >
> >if IS_ENABLED(CONFIG_XXX)
> >
> > but it is a bit confusing. Add the missing brackets.
> >
> > Signed-off-by: Simon Glass 
>
> Reviewed-by: Jaehoon Chung 
>
> Best Regards,
> Jaehoon Chung


Reviewed-by: Minkyu Kang 


>
> > ---
> >
> > (no changes since v1)
> >
> >  drivers/mmc/fsl_esdhc_imx.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> > index 9299635f509..08ea98fe81a 100644
> > --- a/drivers/mmc/fsl_esdhc_imx.c
> > +++ b/drivers/mmc/fsl_esdhc_imx.c
> > @@ -453,7 +453,7 @@ static int esdhc_send_cmd_common(struct
> fsl_esdhc_priv *priv, struct mmc *mmc,
> >
> >   /* Send the command */
> >   esdhc_write32(®s->cmdarg, cmd->cmdarg);
> > - if IS_ENABLED(CONFIG_FSL_USDHC) {
> > + if (IS_ENABLED(CONFIG_FSL_USDHC)) {
> >   u32 mixctrl = esdhc_read32(®s->mixctrl);
> >
> >   esdhc_write32(®s->mixctrl,
> >
>
> --
Thanks. Minkyu Kang.


Re: [RFC 0/6] Exynos5: Update devicetree files from linux kernel

2022-01-17 Thread Minkyu Kang
Hi,

On Thu, 13 Jan 2022 at 17:39, Jaehoon Chung  wrote:

> Exynos5 is using old devicetree file for only U-boot.
> It's difficult to adjust the driver-model and sync codes with linux.
> This patchset is to copy exynos5 devicetree files from linux v5.16.
>
> I don't have all exynos5 boards, so it's difficult to check whether all
> boards are working fine or not.
> If this is worthful job, I will work this continously.
> Otherwise, I will drop this RFC patches.
>
> Tested on XU3 boards.
>

Nice work!
It looks good to me.
It would be nice to check other boards as well.


>
> Jaehoon Chung (6):
>   ARM: exynos5: sync devicetree files from linux kernel
>   board: exynos5-dt-type: add hardkernel,odroid-xu3 compatible
>   mmc: exynos_dw_mmc: add exynos5420 compatible
>   mmc: exynos_dw_mmc: remove the error message and not return
>   i2c: exynos_hs_i2c: add samsung,exynos5250-hsi2c compatible
>   power: s2pms11: change the subnode name to regulators
>
>  arch/arm/dts/cros-adc-thermistors.dtsi|   41 +
>  arch/arm/dts/exynos-syscon-restart.dtsi   |   20 +
>  arch/arm/dts/exynos4-cpu-thermal.dtsi |   48 +
>  arch/arm/dts/exynos5.dtsi |  384 ++---
>  arch/arm/dts/exynos5250-arndale.dts   |  638 +++-
>  arch/arm/dts/exynos5250-pinctrl.dtsi  | 1080 +
>  arch/arm/dts/exynos5250-smdk5250.dts  |  367 +++--
>  arch/arm/dts/exynos5250-snow-common.dtsi  |  709 +
>  arch/arm/dts/exynos5250-snow-rev5.dts |   56 +
>  arch/arm/dts/exynos5250-snow.dts  |  549 +--
>  arch/arm/dts/exynos5250-spring.dts|  677 
>  arch/arm/dts/exynos5250.dtsi  | 1298 +--
>  arch/arm/dts/exynos5420-cpus.dtsi |  163 ++
>  arch/arm/dts/exynos5420-peach-pit.dts | 1228 ++
>  arch/arm/dts/exynos5420-pinctrl.dtsi  |  734 +
>  arch/arm/dts/exynos5420-smdk5420.dts  |  488 --
>  arch/arm/dts/exynos5420-trip-points.dtsi  |   31 +
>  arch/arm/dts/exynos5420.dtsi  | 1413 +
>  arch/arm/dts/exynos5422-cpus.dtsi |  170 ++
>  arch/arm/dts/exynos5422-odroid-core.dtsi  | 1071 +
>  arch/arm/dts/exynos5422-odroidxu3-audio.dtsi  |   83 +
>  arch/arm/dts/exynos5422-odroidxu3-common.dtsi |  505 ++
>  arch/arm/dts/exynos5422-odroidxu3-lite.dts|  127 ++
>  arch/arm/dts/exynos5422-odroidxu3.dts |  336 +---
>  arch/arm/dts/exynos5422-odroidxu4.dts |   92 ++
>  arch/arm/dts/exynos54xx-odroidxu-leds.dtsi|   48 +
>  arch/arm/dts/exynos54xx.dtsi  |  376 +++--
>  arch/arm/dts/exynos5800-peach-pi.dts  | 1080 +++--
>  arch/arm/dts/exynos5800.dtsi  |  162 ++
>  board/samsung/common/exynos5-dt-types.c   |1 +
>  drivers/i2c/exynos_hs_i2c.c   |1 +
>  drivers/mmc/exynos_dw_mmc.c   |   10 +-
>  drivers/power/pmic/s2mps11.c  |2 +-
>  include/dt-bindings/clock/exynos-audss-clk.h  |   27 +
>  include/dt-bindings/clock/exynos5250.h|  181 +++
>  include/dt-bindings/clock/exynos5420.h|  277 
>  include/dt-bindings/clock/maxim,max77686.h|   20 +
>  include/dt-bindings/clock/samsung,s2mps11.h   |   20 +
>  include/dt-bindings/pinctrl/samsung.h |   77 +
>  include/dt-bindings/sound/samsung-i2s.h   |   15 +
>  40 files changed, 11944 insertions(+), 2661 deletions(-)
>  create mode 100644 arch/arm/dts/cros-adc-thermistors.dtsi
>  create mode 100644 arch/arm/dts/exynos-syscon-restart.dtsi
>  create mode 100644 arch/arm/dts/exynos4-cpu-thermal.dtsi
>  create mode 100644 arch/arm/dts/exynos5250-snow-common.dtsi
>  create mode 100644 arch/arm/dts/exynos5250-snow-rev5.dts
>  create mode 100644 arch/arm/dts/exynos5420-cpus.dtsi
>  create mode 100644 arch/arm/dts/exynos5420-pinctrl.dtsi
>  create mode 100644 arch/arm/dts/exynos5420-trip-points.dtsi
>  create mode 100644 arch/arm/dts/exynos5420.dtsi
>  create mode 100644 arch/arm/dts/exynos5422-cpus.dtsi
>  create mode 100644 arch/arm/dts/exynos5422-odroid-core.dtsi
>  create mode 100644 arch/arm/dts/exynos5422-odroidxu3-audio.dtsi
>  create mode 100644 arch/arm/dts/exynos5422-odroidxu3-common.dtsi
>  create mode 100644 arch/arm/dts/exynos5422-odroidxu3-lite.dts
>  create mode 100644 arch/arm/dts/exynos5422-odroidxu4.dts
>  create mode 100644 arch/arm/dts/exynos54xx-odroidxu-leds.dtsi
>  create mode 100644 arch/arm/dts/exynos5800.dtsi
>  create mode 100644 include/dt-bindings/clock/exynos-audss-clk.h
>  create mode 100644 include/dt-bindings/clock/exynos5250.h
>  create mode 100644 include/dt-bindings/clock/exynos5420.h
>  create mode 100644 include/dt-bindings/clock/maxim,max77686.h
>  create mode 100644 include/dt-bindings/clock/samsung,s2mps11.h
>  create mode 100644 include/dt-bindings/pinctrl/samsung.h
>  create mode 100644 include/dt-bindings/sound/samsung-i2s.h
>
> --
> 2.29.0
>
>

-- 
Thanks,
Mi

Re: [PATCH 6/8] configs: am64x_evm: set eth1 as boot interface

2022-01-17 Thread Tom Rini
On Fri, Dec 24, 2021 at 12:55:34PM +0530, Vignesh Raghavendra wrote:

> ROM supports boot from CPSW second port, therefore set eth1 boot
> interface
> 
> Signed-off-by: Vignesh Raghavendra 
> ---
>  include/configs/am64x_evm.h | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
> index 99624081c3..cd4b658e5f 100644
> --- a/include/configs/am64x_evm.h
> +++ b/include/configs/am64x_evm.h
> @@ -33,7 +33,7 @@
>   * our memory footprint. The less we use for BSS the more we have available
>   * for everything else.
>   */
> -#define CONFIG_SPL_BSS_MAX_SIZE  0x1000
> +#define CONFIG_SPL_BSS_MAX_SIZE  0xa000
>  /*
>   * Link BSS to be within SPL in a dedicated region located near the top of
>   * the MCU SRAM, this way making it available also before relocation. Note
> @@ -64,6 +64,7 @@
>   "if test $fdtfile = undefined; then " \
>   "echo WARNING: Could not determine device tree to use; 
> fi; \0" \
>   "name_kern=Image\0" \
> + "ethact=eth0\0" \
>   "console=ttyS2,115200n8\0"  \
>   "args_all=setenv optargs earlycon=ns16550a,mmio32,0x0280 "  \
>   "${mtdparts}\0" \
> @@ -140,4 +141,6 @@
>  
>  #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
>  
> +#define CONFIG_SPL_ETH_DEVICE "eth1"
> +
>  #endif /* __CONFIG_AM642_EVM_H */

What's going on exactly here?  First, CONFIG_SPL_ETH_DEVICE needs to be
migrated to Kconfig now, if we're going to use it.  But, it's used to
set "ethact", which wouldd normally be eth0, but you're setting it to
eth1 here and eth0 for U-Boot itself?  Can you please explain the setup
here?  Thanks!

-- 
Tom


signature.asc
Description: PGP signature


Re: [PATCH 8/8] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot

2022-01-17 Thread Tom Rini
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:

> Enable config options needed to support Ethernet boot on AM64x SK.
> 
> Signed-off-by: Vignesh Raghavendra 

This leads to size overflow on r5.

-- 
Tom


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Description: PGP signature


[PATCH v2 1/1] env: fat: Allow overriding interface, device and partition

2022-01-17 Thread hyyxohk
For platform which can boot on different device, this allows
to override interface, device and partition from board code.

Signed-off-by: hyyxohk 
---
 env/fat.c  | 34 +++---
 include/env_internal.h | 20 
 2 files changed, 39 insertions(+), 15 deletions(-)

diff --git a/env/fat.c b/env/fat.c
index fdccd6cd2a..6251d9649b 100644
--- a/env/fat.c
+++ b/env/fat.c
@@ -32,7 +32,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static char *env_fat_device_and_part(void)
+__weak const char *env_fat_get_intf(void)
+{
+   return (const char *)CONFIG_ENV_FAT_INTERFACE;
+}
+
+__weak char *env_fat_get_dev_part(void)
 {
 #ifdef CONFIG_MMC
static char *part_str;
@@ -60,14 +65,15 @@ static int env_fat_save(void)
int dev, part;
int err;
loff_t size;
+   const char *ifname = env_fat_get_intf();
+   const char *dev_and_part = env_fat_get_dev_part();
 
err = env_export(&env_new);
if (err)
return err;
 
-   part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
-   env_fat_device_and_part(),
-   &dev_desc, &info, 1);
+   part = blk_get_device_part_str(ifname, dev_and_part,
+  &dev_desc, &info, 1);
if (part < 0)
return 1;
 
@@ -77,8 +83,7 @@ static int env_fat_save(void)
 * This printf is embedded in the messages from env_save that
 * will calling it. The missing \n is intentional.
 */
-   printf("Unable to use %s %d:%d... \n",
-  CONFIG_ENV_FAT_INTERFACE, dev, part);
+   printf("Unable to use %s %d:%d...\n", ifname, dev, part);
return 1;
}
 
@@ -93,8 +98,7 @@ static int env_fat_save(void)
 * This printf is embedded in the messages from env_save that
 * will calling it. The missing \n is intentional.
 */
-   printf("Unable to write \"%s\" from %s%d:%d... \n",
-   file, CONFIG_ENV_FAT_INTERFACE, dev, part);
+   printf("Unable to write \"%s\" from %s%d:%d...\n", file, 
ifname, dev, part);
return 1;
}
 
@@ -117,15 +121,16 @@ static int env_fat_load(void)
struct disk_partition info;
int dev, part;
int err1;
+   const char *ifname = env_fat_get_intf();
+   const char *dev_and_part = env_fat_get_dev_part();
 
 #ifdef CONFIG_MMC
-   if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc"))
+   if (!strcmp(ifname, "mmc"))
mmc_initialize(NULL);
 #endif
 
-   part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
-   env_fat_device_and_part(),
-   &dev_desc, &info, 1);
+   part = blk_get_device_part_str(ifname, dev_and_part,
+  &dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
 
@@ -135,8 +140,7 @@ static int env_fat_load(void)
 * This printf is embedded in the messages from env_save that
 * will calling it. The missing \n is intentional.
 */
-   printf("Unable to use %s %d:%d... \n",
-  CONFIG_ENV_FAT_INTERFACE, dev, part);
+   printf("Unable to use %s %d:%d...\n", ifname, dev, part);
goto err_env_relocate;
}
 
@@ -154,7 +158,7 @@ static int env_fat_load(void)
 * will calling it. The missing \n is intentional.
 */
printf("Unable to read \"%s\" from %s%d:%d... \n",
-   CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, 
part);
+   CONFIG_ENV_FAT_FILE, ifname, dev, part);
goto err_env_relocate;
}
 
diff --git a/include/env_internal.h b/include/env_internal.h
index 174c3b1a79..e42ae826ef 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -245,6 +245,26 @@ const char *env_ext4_get_dev_part(void);
  * @return  an enum env_location value on success, or -ve error code.
  */
 enum env_location env_get_location(enum env_operation op, int prio);
+
+/**
+ * env_fat_get_intf() - Provide the interface for env in FAT
+ *
+ * It is a weak function allowing board to overidde the default interface for
+ * U-Boot env in FAT: CONFIG_ENV_FAT_INTERFACE
+ *
+ * @return string of interface, empty if not supported
+ */
+const char *env_fat_get_intf(void);
+
+/**
+ * env_fat_get_dev_part() - Provide the device and partition for env in FAT
+ *
+ * It is a weak function allowing board to overidde the default device and
+ * partition used for U-Boot env in FAT: CONFIG_ENV_FAT_DEVICE_AND_PART
+ *
+ * @return string of device and partition
+ */
+char *env_fat_get_dev_part(void)
 #endif /* DO_DEPS_ONLY */
 
 #endif /* _ENV_INTERNAL_H_ */
-- 
2.17.1

[PATCH v2 01/16] spl: Tidy up the header includes

2022-01-17 Thread Simon Glass
These are out of order. Fix them.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 common/spl/spl.c | 20 +---
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index f51d1f32052..932ad53614d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -9,33 +9,31 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
 #if CONFIG_IS_ENABLED(BANNER_PRINT)
 #include 
 #endif
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 02/16] arm: qemu: Add an SPL build

2022-01-17 Thread Simon Glass
Add an SPL build for qemu so we can test the standard passage feature.

Include a binman definition so that SPL and U-Boot are in the same image.
This requires adding a proper devicetree file for qemu_arm. It is only
used for the SPL build.

For now this just boots to a prompt.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 arch/arm/dts/qemu-arm-u-boot.dtsi|  22 ++
 arch/arm/dts/qemu-arm.dts| 393 ++-
 arch/arm/mach-qemu/Kconfig   |   9 +
 board/emulation/qemu-arm/Kconfig |  23 +-
 board/emulation/qemu-arm/MAINTAINERS |   1 +
 board/emulation/qemu-arm/Makefile|   1 +
 board/emulation/qemu-arm/spl.c   |  27 ++
 configs/qemu_arm_spl_defconfig   |  72 +
 doc/board/emulation/qemu-arm.rst |  37 +++
 9 files changed, 580 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/qemu-arm-u-boot.dtsi
 create mode 100644 board/emulation/qemu-arm/spl.c
 create mode 100644 configs/qemu_arm_spl_defconfig

diff --git a/arch/arm/dts/qemu-arm-u-boot.dtsi 
b/arch/arm/dts/qemu-arm-u-boot.dtsi
new file mode 100644
index 000..2c5c7df62b4
--- /dev/null
+++ b/arch/arm/dts/qemu-arm-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Sample device tree for qemu_arm
+
+ * Copyright 2021 Google LLC
+ */
+
+/ {
+   binman {
+   u-boot-spl {
+   size = <0x1>;
+   };
+
+   u-boot {
+   };
+   };
+
+   pl011@900 {
+   u-boot,dm-spl;
+   };
+
+};
diff --git a/arch/arm/dts/qemu-arm.dts b/arch/arm/dts/qemu-arm.dts
index 230c630f04f..fed558ced98 100644
--- a/arch/arm/dts/qemu-arm.dts
+++ b/arch/arm/dts/qemu-arm.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR MIT
 /*
- * Empty device tree for qemu_arm
+ * Sample device tree for qemu_arm
 
  * Copyright 2021 Google LLC
  */
@@ -8,4 +8,395 @@
 /dts-v1/;
 
 / {
+   interrupt-parent = <0x8001>;
+   #size-cells = <0x02>;
+   #address-cells = <0x02>;
+   compatible = "linux,dummy-virt";
+
+   psci {
+   migrate = <0x8405>;
+   cpu_on = <0x8403>;
+   cpu_off = <0x8402>;
+   cpu_suspend = <0x8401>;
+   method = "hvc";
+   compatible = "arm,psci-0.2\0arm,psci";
+   };
+
+   memory@4000 {
+   reg = <0x00 0x4000 0x00 0x800>;
+   device_type = "memory";
+   };
+
+   platform@c00 {
+   interrupt-parent = <0x8001>;
+   ranges = <0x00 0x00 0xc00 0x200>;
+   #address-cells = <0x01>;
+   #size-cells = <0x01>;
+   compatible = "qemu,platform\0simple-bus";
+   };
+
+   fw-cfg@902 {
+   dma-coherent;
+   reg = <0x00 0x902 0x00 0x18>;
+   compatible = "qemu,fw-cfg-mmio";
+   };
+
+   virtio_mmio@a00 {
+   dma-coherent;
+   interrupts = <0x00 0x10 0x01>;
+   reg = <0x00 0xa00 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000200 {
+   dma-coherent;
+   interrupts = <0x00 0x11 0x01>;
+   reg = <0x00 0xa000200 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000400 {
+   dma-coherent;
+   interrupts = <0x00 0x12 0x01>;
+   reg = <0x00 0xa000400 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000600 {
+   dma-coherent;
+   interrupts = <0x00 0x13 0x01>;
+   reg = <0x00 0xa000600 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000800 {
+   dma-coherent;
+   interrupts = <0x00 0x14 0x01>;
+   reg = <0x00 0xa000800 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000a00 {
+   dma-coherent;
+   interrupts = <0x00 0x15 0x01>;
+   reg = <0x00 0xa000a00 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000c00 {
+   dma-coherent;
+   interrupts = <0x00 0x16 0x01>;
+   reg = <0x00 0xa000c00 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a000e00 {
+   dma-coherent;
+   interrupts = <0x00 0x17 0x01>;
+   reg = <0x00 0xa000e00 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a001000 {
+   dma-coherent;
+   interrupts = <0x00 0x18 0x01>;
+   reg = <0x00 0xa001000 0x00 0x200>;
+   compatible = "virtio,mmio";
+   };
+
+   virtio_mmio@a001200 {
+   dma-coherent;
+   interrupts = <0x00 0x19 0x01>;
+   

[PATCH v2 06/16] passage: arm: Accept a passage from the previous phase

2022-01-17 Thread Simon Glass
Accept a bloblist and control devicetree from a previous phase in
registers r0 and r1

Signed-off-by: Simon Glass 
---

Changes in v2:
- Use three registers instead of two for the entry

 arch/arm/cpu/armv7/start.S | 7 ++-
 arch/arm/lib/crt0.S| 5 +
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 698e15b8e18..494f4abdb1f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -36,6 +36,11 @@
 #endif
 
 reset:
+   # Keep passage information in case it is provided
+   mov r6, r1
+   mov r7, r2
+   mov r8, r3
+
/* Allow the board to save important registers */
b   save_boot_params
 save_boot_params_ret:
@@ -124,7 +129,7 @@ switch_to_hypervisor_ret:
bl  cpu_init_crit
 #endif
 #endif
-
+   # Note: r6-r8 are available to _main in case standard passage is used
bl  _main
 
 
/*--*/
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index ba312901f33..68282ebfd02 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -117,6 +117,11 @@ ENTRY(_main)
CLEAR_BSS
 #endif
 
+#if CONFIG_IS_ENABLED(PASSAGE_IN)
+   str r6, [r9, #GD_PASSAGE_MACH]
+   str r7, [r9, #GD_PASSAGE_DTB]
+   str r8, [r9, #GD_PASSAGE_BLOBLIST]
+#endif
mov r0, #0
bl  board_init_f
 
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 03/16] spl: Rename jump_to_image_no_args()

2022-01-17 Thread Simon Glass
This is about to become a misnomer since with standard passage we need to
pass arguments to U-Boot. Rename the function.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Split the jump_to_image_no_args() change into its own patch

 arch/arm/mach-imx/imx8ulp/soc.c | 2 +-
 arch/arm/mach-imx/spl.c | 2 +-
 arch/arm/mach-k3/common.c   | 2 +-
 arch/arm/mach-omap2/boot-common.c   | 2 +-
 arch/arm/mach-tegra/spl.c   | 2 +-
 arch/mips/lib/spl.c | 2 +-
 arch/riscv/lib/spl.c| 2 +-
 arch/sandbox/cpu/spl.c  | 4 ++--
 arch/x86/lib/spl.c  | 2 +-
 arch/x86/lib/tpl.c  | 2 +-
 board/freescale/common/fsl_chain_of_trust.c | 2 +-
 board/renesas/rcar-common/gen3-spl.c| 2 +-
 common/spl/spl.c| 4 ++--
 drivers/usb/gadget/f_sdp.c  | 2 +-
 include/spl.h   | 2 +-
 15 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index bba6323f96f..ad2ee880f53 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -512,7 +512,7 @@ int arch_cpu_init_dm(void)
 }
 
 #if defined(CONFIG_SPL_BUILD)
-__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+__weak void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
debug("image entry point: 0x%lx\n", spl_image->entry_point);
 
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 427b7f78599..1055b126e39 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -279,7 +279,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
  * ++ + CSF_PAD_SIZE
  */
 
-__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+__weak void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
typedef void __noreturn (*image_entry_noargs_t)(void);
uint32_t offset;
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 2666cd2d7b1..aba554e262a 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -198,7 +198,7 @@ __weak void release_resources_for_core_shutdown(void)
debug("%s not implemented...\n", __func__);
 }
 
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
diff --git a/arch/arm/mach-omap2/boot-common.c 
b/arch/arm/mach-omap2/boot-common.c
index fdb8b479ea0..ee7d1240dbf 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -216,7 +216,7 @@ void spl_board_init(void)
 #endif
 }
 
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
image_entry_noargs_t image_entry =
diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c
index ed897efc5f0..1e4efa325ee 100644
--- a/arch/arm/mach-tegra/spl.c
+++ b/arch/arm/mach-tegra/spl.c
@@ -44,7 +44,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_RAM;
 }
 
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
debug("image entry point: 0x%lX\n", spl_image->entry_point);
 
diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c
index f96fda5b2de..e07cd398d02 100644
--- a/arch/mips/lib/spl.c
+++ b/arch/mips/lib/spl.c
@@ -8,7 +8,7 @@
 #include 
 #include 
 
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index 8baee07beac..c8238ecbeb0 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -36,7 +36,7 @@ __weak void board_init_f(ulong dummy)
panic("spl_board_init_f() failed: %d\n", ret);
 }
 
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
void *fdt_blob;
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 650bdb0a701..22df543e6b7 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -58,7 +58,7 @@ static int spl_board_load_image(struct spl_image_info 
*spl_image,
}
 
/*
-* Set up spl_image to boot from jump_to_image_no_args(). Allocate this
+* Set up spl_image to boot from jump_to_image(). Allocate this
 * outs

[PATCH v2 05/16] passage: Support a control devicetree

2022-01-17 Thread Simon Glass
Add support for accepting a control devicetree from the incoming passage.
This allows SPL (or some other program) to pass a devicetree to U-Boot
proper in a standard way.

Pass the devicetree through the early parts of U-Boot needs a list care.
If it is in the bloblist, there is no need to reserve a separate space for
it to relocate into, since it will be relocated as part of the bloblist.

Also we must init the bloblist before calling fdtdec_setup(), so the
devicetree can be read from the bloblist*. This is not normally safe,
since malloc() is be called by bloblist_init() if CONFIG_BLOBLIST_ALLOC
is enabled. But in the case of a devicetree in the incoming passage, we
know we won't need to allocate the bloblist, since the previous phase has
set it up for us.

Finally, move the reloc_fdt() call after the reloc_bloblist() since, as
mentioned above, when the passage is used there is no need to relocate the
devicetree.

There is one subtlety here. If bloblist support is not enabled in U-Boot,
it can still receive a control devicetree, using the passage_dtb_off value
added to passage_bloblist. This allows the devicetree passing to work
even if the bloblist itself is ignored. In that case we do need to
relocate the devicetree. Use a global_data flag for this case.

* Actually we could init the bloblist later, since we have the offset of
the devicetree in a register, but that seems like an extreme measure,
bypassing U-Boot's own bloblist implementation to get at the data.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Incorporate devicetree source
- Rebase to master

 common/bloblist.c |  1 +
 common/board_f.c  | 16 +++
 dts/Kconfig   | 12 +++
 include/asm-generic/global_data.h |  4 
 include/bloblist.h|  1 +
 include/fdtdec.h  |  4 
 lib/fdtdec.c  | 33 +++
 7 files changed, 67 insertions(+), 4 deletions(-)

diff --git a/common/bloblist.c b/common/bloblist.c
index df45d45de90..3a2fba212c9 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -39,6 +39,7 @@ static struct tag_name {
{ BLOBLISTT_NONE, "(none)" },
 
/* BLOBLISTT_AREA_FIRMWARE_TOP */
+   { BLOBLISTT_CONTROL_DTB, "Control DTB" },
 
/* BLOBLISTT_AREA_FIRMWARE */
{ BLOBLISTT_ACPI_GNVS, "ACPI GNVS" },
diff --git a/common/board_f.c b/common/board_f.c
index 04d98366bd6..0794cc50a57 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -517,7 +517,7 @@ static int reserve_global_data(void)
 
 static int reserve_fdt(void)
 {
-   if (!IS_ENABLED(CONFIG_OF_EMBED)) {
+   if (!IS_ENABLED(CONFIG_OF_EMBED) && !(gd->flags & GD_FLG_OF_PASSAGE)) {
/*
 * If the device tree is sitting immediately above our image
 * then we must relocate it. If it is embedded in the data
@@ -622,7 +622,12 @@ static int init_post(void)
 
 static int reloc_fdt(void)
 {
-   if (!IS_ENABLED(CONFIG_OF_EMBED)) {
+   if (IS_ENABLED(CONFIG_OF_PASSAGE) && (gd->flags & GD_FLG_OF_PASSAGE)) {
+   void *blob = bloblist_find(BLOBLISTT_CONTROL_DTB, 0);
+
+   log_info("passage: Control dtb relocated to %p\n", blob);
+   gd->fdt_blob = blob;
+   } else if (!IS_ENABLED(CONFIG_OF_EMBED)) {
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
if (gd->new_fdt) {
@@ -821,6 +826,9 @@ __weak int clear_bss(void)
 
 static const init_fnc_t init_sequence_f[] = {
setup_mon_len,
+#ifdef CONFIG_OF_PASSAGE
+   bloblist_init,
+#endif
 #ifdef CONFIG_OF_CONTROL
fdtdec_setup,
 #endif
@@ -830,7 +838,7 @@ static const init_fnc_t init_sequence_f[] = {
initf_malloc,
log_init,
initf_bootstage,/* uses its own timer, so does not need DM */
-#ifdef CONFIG_BLOBLIST
+#if !defined(CONFIG_OF_PASSAGE) && defined(CONFIG_BLOBLIST)
bloblist_init,
 #endif
setup_spl_handoff,
@@ -940,9 +948,9 @@ static const init_fnc_t init_sequence_f[] = {
setup_bdinfo,
display_new_sp,
INIT_FUNC_WATCHDOG_RESET
-   reloc_fdt,
reloc_bootstage,
reloc_bloblist,
+   reloc_fdt,
setup_reloc,
 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
copy_uboot_to_ram,
diff --git a/dts/Kconfig b/dts/Kconfig
index fb7df533f92..65d129453c6 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -96,6 +96,18 @@ config OF_EMBED
 
 endchoice
 
+config OF_PASSAGE
+   bool "Devicetree provided by the standard passage protocol"
+   help
+ If this option is enabled, the device tree may be provided by the
+ standard passage, meaning that a previous phase/stage passes a
+ bloblist containing this. This is the standard way to pass a
+ devicetree between firmware components at runtime. The device tree
+ bundled with the image (if any) will be overridden / ignored.
+
+   

[PATCH v2 09/16] passage: arm: Add the arch-specific standard passage impl

2022-01-17 Thread Simon Glass
Add implementations for 32- and 64-bit ARM.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add new patch with the arm-specific standard passage implementation

 arch/arm/cpu/armv7/cpu.c | 28 
 arch/arm/cpu/armv8/cpu.c | 20 
 2 files changed, 48 insertions(+)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 68807d20997..4f16ea0058a 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -83,3 +84,30 @@ int cleanup_before_linux(void)
 {
return cleanup_before_linux_select(CBL_ALL);
 }
+
+void __noreturn arch_passage_entry(ulong entry_addr, ulong bloblist, ulong fdt)
+{
+   typedef void __noreturn (*passage_entry_t)(ulong zero1, ulong mach,
+  ulong fdt, ulong bloblist);
+   passage_entry_t entry = (passage_entry_t)entry_addr;
+
+   /*
+* Register   Contents
+* r0 0
+* r1 0xb0075701 (indicates standard passage v1)
+* r2 Address of devicetree
+* r3 Address of bloblist
+* r4 0
+* lr Return address
+*
+* The ARMv7 calling convention only passes 4 arguments in registers, so
+* set r4 to 0 manually.
+*/
+   __asm__ volatile (
+   "mov r4, #0\n"
+   :
+   :
+   : "r4"
+   );
+   entry(0, passage_mach_version(), fdt, bloblist);
+}
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index ea40c55dd2c..4d67152f033 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -84,3 +85,22 @@ void armv8_setup_psci(void)
secure_ram_addr(psci_arch_init)();
 }
 #endif
+
+void __noreturn arch_passage_entry(ulong entry_addr, ulong bloblist, ulong fdt)
+{
+   typedef void __noreturn (*passage_entry_t)(ulong fdt, ulong abi,
+  ulong zero1, ulong bloblist,
+  ulong zero2);
+   passage_entry_t entry = (passage_entry_t)entry_addr;
+
+   /*
+* Register   Contents
+* x0 Address of devicetree
+* x1 0xb00757a30001 (indicates standard passage v1)
+* x2 0
+* x3 Address of bloblist
+* x4 0
+* x30Return address
+*/
+   entry(fdt, passage_mach_version(), 0, bloblist, 0);
+}
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 08/16] passage: spl: Support passing the passage to U-Boot

2022-01-17 Thread Simon Glass
Create a new arch-specific way of creating a standard passage to the
next phase.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Make the stdpass calling standard arch-specific

 common/spl/spl.c  | 27 ++-
 include/asm-generic/global_data.h |  6 ++
 include/passage.h | 28 
 3 files changed, 56 insertions(+), 5 deletions(-)
 create mode 100644 include/passage.h

diff --git a/common/spl/spl.c b/common/spl/spl.c
index be770d0226c..0b78fdd5eae 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #if CONFIG_IS_ENABLED(BANNER_PRINT)
@@ -392,13 +393,29 @@ int spl_parse_image_header(struct spl_image_info 
*spl_image,
 
 __weak void __noreturn jump_to_image(struct spl_image_info *spl_image)
 {
-   typedef void __noreturn (*image_entry_noargs_t)(void);
-
-   image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)spl_image->entry_point;
+   typedef void __noreturn (*image_entry_t)(void);
+   ulong bloblist = 0;
+   ulong dtb_offset = 0;
 
debug("image entry point: 0x%lx\n", spl_image->entry_point);
-   image_entry();
+
+   if (CONFIG_IS_ENABLED(PASSAGE_OUT)) {
+   const void *fdt;
+
+   bloblist = bloblist_get_base();
+   fdt = bloblist_find(BLOBLISTT_CONTROL_DTB, 0);
+
+   log_debug("passage: sending bloblist at %lx, dtb offset %lx\n",
+ bloblist, dtb_offset);
+   arch_passage_entry(spl_image->entry_point,
+  map_to_sysmem(gd_bloblist()),
+  map_to_sysmem(fdt));
+   } else {
+   image_entry_t image_entry;
+
+   image_entry = (image_entry_t)spl_image->entry_point;
+   image_entry();
+   }
 }
 
 #if CONFIG_IS_ENABLED(HANDOFF)
diff --git a/include/asm-generic/global_data.h 
b/include/asm-generic/global_data.h
index 34b4139e498..71a60115cee 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -552,6 +552,12 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
 #define gd_set_multi_dtb_fit(_dtb)
 #endif
 
+#if CONFIG_IS_ENABLED(BLOBLIST)
+#define gd_bloblist()  gd->bloblist
+#else
+#define gd_bloblist()  NULL
+#endif
+
 /**
  * enum gd_flags - global data flags
  *
diff --git a/include/passage.h b/include/passage.h
new file mode 100644
index 000..51c40154711
--- /dev/null
+++ b/include/passage.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Standard passage implementation
+ *
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass 
+ */
+
+#ifndef __PASSAGE_H
+#define __PASSAGE_H
+
+enum {
+   PASSAGE_ABI_MACH= 0xb00757a3,
+   PASSAGE_ABI_VERSION = 1,
+};
+
+static inline ulong passage_mach_version(void)
+{
+#if BITS_PER_LONG == 64
+   return (ulong)PASSAGE_ABI_MACH << 32 | PASSAGE_ABI_VERSION;
+#else
+   return (PASSAGE_ABI_MACH & ~0xff) | PASSAGE_ABI_VERSION;
+#endif
+}
+
+void __noreturn arch_passage_entry(ulong entry_addr, ulong bloblist, ulong 
fdt);
+
+#endif
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 10/16] passage: Add a qemu test for ARM

2022-01-17 Thread Simon Glass
Check that the standard passage works on ARM, by setting it up in SPL
and making sure that it comes through correctly in U-Boot proper.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add a devicetree for qemu-arm so that qemu_arm_spl can work

 arch/arm/Kconfig   |  2 +-
 configs/qemu_arm_spl_defconfig |  8 +++-
 test/py/tests/test_passage.py  | 11 +++
 3 files changed, 19 insertions(+), 2 deletions(-)
 create mode 100644 test/py/tests/test_passage.py

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 78c6b2e92dc..c4d06d2f1a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -974,7 +974,7 @@ config ARCH_QEMU
imply DM_RNG
imply DM_RTC
imply RTC_PL031
-   imply OF_HAS_PRIOR_STAGE
+   imply OF_HAS_PRIOR_STAGE if !TARGET_QEMU_ARM_32BIT_SPL
 
 config ARCH_RMOBILE
bool "Renesas ARM SoCs"
diff --git a/configs/qemu_arm_spl_defconfig b/configs/qemu_arm_spl_defconfig
index a6950584542..e91fed8f5e0 100644
--- a/configs/qemu_arm_spl_defconfig
+++ b/configs/qemu_arm_spl_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_MALLOC_LEN=0x100
 CONFIG_DEFAULT_DEVICE_TREE="qemu-arm"
 CONFIG_TARGET_QEMU_ARM_32BIT_SPL=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x6000
 CONFIG_DEBUG_UART_BASE=0x900
 CONFIG_DEBUG_UART_CLOCK=0
 CONFIG_ARMV7_LPAE=y
@@ -28,6 +29,11 @@ CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_PCI_INIT_R=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_PASSAGE=y
+CONFIG_SPL_BLOBLIST_ALLOC=y
+CONFIG_BLOBLIST_SIZE=0x4000
+CONFIG_PASSAGE_IN=y
 CONFIG_SPL_FRAMEWORK_BOARD_INIT_F=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
@@ -37,7 +43,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PASSAGE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x400
 CONFIG_SPL_DM=y
diff --git a/test/py/tests/test_passage.py b/test/py/tests/test_passage.py
new file mode 100644
index 000..594dc3cc685
--- /dev/null
+++ b/test/py/tests/test_passage.py
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright 2021 Google LLC
+
+import pytest
+
+@pytest.mark.buildconfigspec('target_qemu_arm_32bit_spl')
+def test_passage(u_boot_console):
+"""Test that the standard passage on ARM from SPL to U-Boot works."""
+
+response = u_boot_console.run_command('bdinfo')
+assert 'devicetree  = passage' in response
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 13/16] passage: Add docs for spl_handoff

2022-01-17 Thread Simon Glass
This tag already exists in U-Boot. Add documentation, following the
format set out.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 board/sandbox/stdpass_check.c | 8 
 include/handoff.h | 8 +---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/board/sandbox/stdpass_check.c b/board/sandbox/stdpass_check.c
index 8391c7a4aed..9c015b6783e 100644
--- a/board/sandbox/stdpass_check.c
+++ b/board/sandbox/stdpass_check.c
@@ -28,3 +28,11 @@ void check_struct_name(void)
 {
/* __maybe_unused struct struct_name check; */
 }
+
+/* BLOBLISTT_U_BOOT_SPL_HANDOFF */
+#include 
+void check_spl_handoff(void)
+{
+   __maybe_unused struct spl_handoff check;
+};
+
diff --git a/include/handoff.h b/include/handoff.h
index 070a79c1b97..30203033ec9 100644
--- a/include/handoff.h
+++ b/include/handoff.h
@@ -9,16 +9,20 @@
 #define __HANDOFF_H
 
 #if CONFIG_IS_ENABLED(HANDOFF)
-
 #include 
+#endif
 
 /**
  * struct spl_handoff - information passed from SPL to U-Boot proper
  *
+ * bloblist_tag: BLOBLISTT_U_BOOT_SPL_HANDOFF
+ *
  * @ram_size: Value to use for gd->ram_size
  */
 struct spl_handoff {
+#if CONFIG_IS_ENABLED(HANDOFF)
struct arch_spl_handoff arch;
+#endif
u64 ram_size;
struct {
u64 start;
@@ -43,5 +47,3 @@ void handoff_load_dram_banks(struct spl_handoff *ho);
 int handoff_arch_save(struct spl_handoff *ho);
 
 #endif
-
-#endif
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 11/16] sandbox: Add a way of checking structs for standard passage

2022-01-17 Thread Simon Glass
Add a file which can be used to check that structs used in standard
passage do compile. No other validation is done at present, but could be
considered later.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 board/sandbox/Makefile|  3 ++-
 board/sandbox/stdpass_check.c | 36 +++
 include/stdpass/README|  4 
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 board/sandbox/stdpass_check.c
 create mode 100644 include/stdpass/README

diff --git a/board/sandbox/Makefile b/board/sandbox/Makefile
index 411b53c2b8d..d9b56adbbb8 100644
--- a/board/sandbox/Makefile
+++ b/board/sandbox/Makefile
@@ -2,4 +2,5 @@
 #
 # Copyright (c) 2011 The Chromium OS Authors.
 
-obj-y  := sandbox.o
+obj-y  += sandbox.o
+obj-y  += stdpass_check.o
diff --git a/board/sandbox/stdpass_check.c b/board/sandbox/stdpass_check.c
new file mode 100644
index 000..565124e1564
--- /dev/null
+++ b/board/sandbox/stdpass_check.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file compiles all the struct definitions for standard passage, to 
ensure
+ * there are no errors
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include 
+
+/* BLOBLISTT_U_BOOT_SPL_HANDOFF */
+#include 
+void check_spl_handoff(void)
+{
+   __maybe_unused struct spl_handoff check;
+};
+
+/*
+ * See also doc/develop/std_passage.rst
+ *
+ * Instructions:
+ *
+ * 1. Add your header file to U-Boot, or to include/stdpass if it is not used 
in
+ * U-Boot
+ *
+ * 2. Add a function below to include the header and use the struct
+ *
+ * Template follows, see above for example
+ */
+
+/* BLOBLISTT_tag here */
+/* #include  if not used in U-Boot*/
+void check_struct_name(void)
+{
+   /* __maybe_unused struct struct_name check; */
+}
diff --git a/include/stdpass/README b/include/stdpass/README
new file mode 100644
index 000..a972121f40c
--- /dev/null
+++ b/include/stdpass/README
@@ -0,0 +1,4 @@
+This directory contains standard passage structures
+
+See doc/develop/std_passage.rst for instructions
+
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 14/16] x86: Move Intel GNVS file into the common include directory

2022-01-17 Thread Simon Glass
Move this so we can include it from sandbox, needed since it is in a
bloblist and must have a check.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 arch/x86/cpu/apollolake/acpi.c| 2 +-
 arch/x86/cpu/intel_common/acpi.c  | 2 +-
 arch/x86/include/asm/arch-apollolake/global_nvs.h | 2 +-
 board/google/chromebook_coral/coral.c | 2 +-
 {arch/x86/include/asm => include}/intel_gnvs.h| 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename {arch/x86/include/asm => include}/intel_gnvs.h (100%)

diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
index fd21c0b4968..2822b8d06d1 100644
--- a/arch/x86/cpu/apollolake/acpi.c
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -21,7 +22,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
index 15f19da2067..4a288e85252 100644
--- a/arch/x86/cpu/intel_common/acpi.c
+++ b/arch/x86/cpu/intel_common/acpi.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -23,7 +24,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h 
b/arch/x86/include/asm/arch-apollolake/global_nvs.h
index ef8eb228dbe..639d8f2de78 100644
--- a/arch/x86/include/asm/arch-apollolake/global_nvs.h
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -10,6 +10,6 @@
 #ifndef _GLOBAL_NVS_H_
 #define _GLOBAL_NVS_H_
 
-#include 
+#include 
 
 #endif /* _GLOBAL_NVS_H_ */
diff --git a/board/google/chromebook_coral/coral.c 
b/board/google/chromebook_coral/coral.c
index 53c5171d02b..ca63cf4ef51 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -11,13 +11,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/include/asm/intel_gnvs.h b/include/intel_gnvs.h
similarity index 100%
rename from arch/x86/include/asm/intel_gnvs.h
rename to include/intel_gnvs.h
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 12/16] passage: Add documentation

2022-01-17 Thread Simon Glass
Add documentation about standard passage and update the maintainers.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add comments about how to pass standard passage to EFI
- Add comments about passing a bloblist to Linux
- Add detailed arch-specific information

 MAINTAINERS   |  10 +
 board/sandbox/stdpass_check.c |  10 +-
 doc/develop/bloblist.rst  |   4 +-
 doc/develop/index.rst |   1 +
 doc/develop/std_passage.rst   | 396 ++
 5 files changed, 411 insertions(+), 10 deletions(-)
 create mode 100644 doc/develop/std_passage.rst

diff --git a/MAINTAINERS b/MAINTAINERS
index 38c68ee87d4..63723d43b63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1177,6 +1177,16 @@ F:   common/stackprot.c
 F: cmd/stackprot_test.c
 F: test/py/tests/test_stackprotector.py
 
+STANDARD PASSAGE
+M: Simon Glass 
+F: board/sandbox/stdpass_check.c
+F: cmd/bloblist.c
+F: common/bloblist.c
+F: doc/develop/std_passage.rst
+F: include/bloblist.h
+F: include/stdpass/
+F: test/bloblist.c
+
 TARGET_BCMNS3
 M: Bharat Gooty 
 M: Rayagonda Kokatanur 
diff --git a/board/sandbox/stdpass_check.c b/board/sandbox/stdpass_check.c
index 565124e1564..8391c7a4aed 100644
--- a/board/sandbox/stdpass_check.c
+++ b/board/sandbox/stdpass_check.c
@@ -8,13 +8,6 @@
 
 #include 
 
-/* BLOBLISTT_U_BOOT_SPL_HANDOFF */
-#include 
-void check_spl_handoff(void)
-{
-   __maybe_unused struct spl_handoff check;
-};
-
 /*
  * See also doc/develop/std_passage.rst
  *
@@ -23,7 +16,8 @@ void check_spl_handoff(void)
  * 1. Add your header file to U-Boot, or to include/stdpass if it is not used 
in
  * U-Boot
  *
- * 2. Add a function below to include the header and use the struct
+ * 2. Add a function below to include the header and use the struct. Please put
+ * your function in order of tag ID (see bloblist.h)
  *
  * Template follows, see above for example
  */
diff --git a/doc/develop/bloblist.rst b/doc/develop/bloblist.rst
index 572aa65d764..e819c6dc76b 100644
--- a/doc/develop/bloblist.rst
+++ b/doc/develop/bloblist.rst
@@ -1,7 +1,7 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-Blob Lists - bloblist
-=
+Bloblist
+
 
 Introduction
 
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index 9592d193fca..d0aecc30059 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -21,6 +21,7 @@ Implementation
logging
makefiles
menus
+   std_passage
uefi/index
version
 
diff --git a/doc/develop/std_passage.rst b/doc/develop/std_passage.rst
new file mode 100644
index 000..461098e01e7
--- /dev/null
+++ b/doc/develop/std_passage.rst
@@ -0,0 +1,396 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Standard Passage
+
+
+Introduction
+
+
+It is sometimes necessary for SPL to communicate information to U-Boot proper,
+such as the RAM size. This can sometimes be handled by adding the value to a
+Kconfig which both SPL and U-Boot proper can use. But this does not work for
+values which are detected at runtime.
+
+In some cases other firmware binaries are used alongside U-Boot and these may
+need to pass information to U-Boot or receive information from it. In this case
+there is no shared build system and it is clumsy so have to specify matching
+build options across projects.
+
+U-Boot provides a standard way of passing information between different phases
+(TPL, SPL, U-Boot). This is called `standard passage` since it creates a
+standard passage through which any sort of information can flow.
+
+
+How it works
+
+
+The standard passage is very simple. It is really just a way of sending a
+bloblist between programs, either at a fixed address, or using registers to
+indicate the location.
+
+A :doc:`bloblist` is a simple, contiguous data structure containing a number of
+blobs. Each blob has a tag to indicate what it contains. It is designed for
+simple information, like a small C struct. For more complex data, a devicetree
+is preferred since it has bindings and is extensible.
+
+The bloblist is typically set up initially by one of the early phases of 
U-Boot,
+such as TPL. It starts either at a fixed address or is allocated in memory 
using
+malloc(). After that, TPL passes the location of the bloblist to SPL (using
+machine register in an architecture-specific way) and SPL passes it to U-Boot
+proper. It is possible to add new blobs to the bloblist at each phase. U-Boot
+proper relocates the bloblist so can expand it if desired.
+
+
+Use by other projects
+-
+
+The standard passage is also intended to be used by other firmware projects,
+particularly if they interface with U-Boot. It allows that project's firmware
+binaries to pass information to U-Boot (if they run before U-Boot) or receive
+information from U-Boot (if they run afterwards).
+
+These projects can copy and modify the bloblist code provided they have a
+compatible licens

[PATCH v2 16/16] WIP: RFC: Add a gitlab test

2022-01-17 Thread Simon Glass
This needs fixing up once the new hooks land as well as adding an
azure rule.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Rebase to master (dropping bloblist patches already applied)

 .gitlab-ci.yml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 4c44c01e7bf..31f3d7e55a9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -261,6 +261,12 @@ qemu_arm64 test.py:
 TEST_PY_TEST_SPEC: "not sleep"
   <<: *buildman_and_testpy_dfn
 
+#qemu_arm spl_test.py:
+#  variables:
+#TEST_PY_BD: "qemu_arm_spl"
+#TEST_PY_TEST_SPEC: "not sleep"
+#  <<: *buildman_and_testpy_dfn
+
 qemu_malta test.py:
   variables:
 TEST_PY_BD: "malta"
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH v2 15/16] passage: Add checks for pre-existing blobs

2022-01-17 Thread Simon Glass
Add checks / documentation for blobs which are already in the list. This
brings U-Boot up to the standard required by the standard-passage
documentation.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 board/sandbox/stdpass_check.c   |  71 -
 include/stdpass/tpm2_eventlog.h |  42 +
 include/stdpass/vboot_ctx.h | 267 
 3 files changed, 379 insertions(+), 1 deletion(-)
 create mode 100644 include/stdpass/tpm2_eventlog.h
 create mode 100644 include/stdpass/vboot_ctx.h

diff --git a/board/sandbox/stdpass_check.c b/board/sandbox/stdpass_check.c
index 9c015b6783e..1db9ad357ee 100644
--- a/board/sandbox/stdpass_check.c
+++ b/board/sandbox/stdpass_check.c
@@ -29,10 +29,79 @@ void check_struct_name(void)
/* __maybe_unused struct struct_name check; */
 }
 
+/* BLOBLISTT_CONTROL_DTB */
+void check_control_dtb(void)
+{
+   /*
+* Defined by devicetree specification
+* 
https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3
+*/
+};
+
+/* BLOBLISTT_ACPI_GNVS */
+#include 
+void check_acpi_gnvs(void)
+{
+   __maybe_unused struct acpi_global_nvs check;
+}
+
+/* BLOBLISTT_INTEL_VBT */
+void check_intel_vbt(void)
+{
+   /*
+* Pre-existing Intel blob, defined by source code
+*
+* 
https://github.com/freedesktop/xorg-intel-gpu-tools/blob/master/tools/intel_vbt_defs.h
+* 
https://github.com/freedesktop/xorg-intel-gpu-tools/blob/master/tools/intel_vbt_decode.c
+*/
+}
+
+/* BLOBLISTT_TPM2_TCG_LOG */
+#include 
+void check_tpm2_tcg_log(void)
+{
+   /* Struct for each record */
+   __maybe_unused struct tpm2_eventlog_context check;
+}
+
+/* BLOBLISTT_TCPA_LOG */
+#include 
+void check_tcpa_log(void)
+{
+   __maybe_unused struct acpi_tcpa check;
+};
+
+/* BLOBLISTT_ACPI_TABLES */
+void check_acpi_tables(void)
+{
+   /*
+* Defined by UEFI Advanced Configuration and Power Interface (ACPI)
+* Specification, Version 6.3, January 2019
+* 
https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
+*/
+}
+
+/* BLOBLISTT_SMBIOS_TABLES */
+void check_smbios_tables(void)
+{
+   /*
+* Defined by System Management BIOS (SMBIOS) Reference Specification
+* v3.5.0
+* https://www.dmtf.org/standards/smbios
+*/
+}
+
+/* BLOBLISTT_VBOOT_CTX */
+#include 
+void check_vboot_ctx(void)
+{
+   __maybe_unused struct vb2_shared_data check;
+
+}
+
 /* BLOBLISTT_U_BOOT_SPL_HANDOFF */
 #include 
 void check_spl_handoff(void)
 {
__maybe_unused struct spl_handoff check;
 };
-
diff --git a/include/stdpass/tpm2_eventlog.h b/include/stdpass/tpm2_eventlog.h
new file mode 100644
index 000..6b258609149
--- /dev/null
+++ b/include/stdpass/tpm2_eventlog.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/* taken from 
https://github.com/tpm2-software/tpm2-tss/blob/master/include/tss2/tss2_tpm2_types.h
 */
+#define TPM2_MAX_PCRS   32
+
+/* Hash algorithm sizes */
+#define TPM2_SHA_DIGEST_SIZE 20
+#define TPM2_SHA1_DIGEST_SIZE20
+#define TPM2_SHA256_DIGEST_SIZE  32
+#define TPM2_SHA384_DIGEST_SIZE  48
+#define TPM2_SHA512_DIGEST_SIZE  64
+#define TPM2_SM3_256_DIGEST_SIZE 32
+
+/* taken from 
https://github.com/tpm2-software/tpm2-tools/blob/master/lib/tpm2_eventlog.h#L14 
*/
+
+typedef bool (*digest2_callback)(void const *digest, size_t size, void *data);
+typedef bool (*event2_callback)(void const *event_hdr, size_t size, void 
*data);
+typedef bool (*event2data_callback)(void const *event, u32 type, void *data,
+   u32 eventlog_version);
+typedef bool (*specid_callback)(void const *event, void *data);
+typedef bool (*log_event_callback)(void const *event_hdr, size_t size,
+  void *data);
+
+struct tpm2_eventlog_context {
+   void *data;
+   specid_callback specid_cb;
+   log_event_callback log_eventhdr_cb;
+   event2_callback event2hdr_cb;
+   digest2_callback digest2_cb;
+   event2data_callback event2_cb;
+   u32 sha1_used;
+   u32 sha256_used;
+   u32 sha384_used;
+   u32 sha512_used;
+   u32 sm3_256_used;
+   u8 sha1_pcrs[TPM2_MAX_PCRS][TPM2_SHA1_DIGEST_SIZE];
+   u8 sha256_pcrs[TPM2_MAX_PCRS][TPM2_SHA256_DIGEST_SIZE];
+   u8 sha384_pcrs[TPM2_MAX_PCRS][TPM2_SHA384_DIGEST_SIZE];
+   u8 sha512_pcrs[TPM2_MAX_PCRS][TPM2_SHA512_DIGEST_SIZE];
+   u8 sm3_256_pcrs[TPM2_MAX_PCRS][TPM2_SM3_256_DIGEST_SIZE];
+   u32 eventlog_version;
+};
diff --git a/include/stdpass/vboot_ctx.h b/include/stdpass/vboot_ctx.h
new file mode 100644
index 000..ff74e8ba709
--- /dev/null
+++ b/include/stdpass/vboot_ctx.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Taken from https://chromium.googlesource.com/chromiumos/platform/vboot
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source c

[PATCH 03/13] arm: imx8m: add Purism Librem5 Kconfig

2022-01-17 Thread Angus Ainslie
Add the Librem5 target

Signed-off-by: Angus Ainslie 
---
 arch/arm/mach-imx/imx8m/Kconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d6a869068a..ba50931cd7 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -160,6 +160,14 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_LIBREM5
+   bool "Purism Librem5 Phone"
+   select BINMAN
+   select IMX8MQ
+   select SUPPORT_SPL
+   select IMX8M_LPDDR4
+
 endchoice
 
 source "board/beacon/imx8mm/Kconfig"
@@ -175,6 +183,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
+source "board/purism/librem5/Kconfig"
 source "board/ronetix/imx8mq-cm/Kconfig"
 source "board/technexion/pico-imx8mq/Kconfig"
 source "board/toradex/verdin-imx8mm/Kconfig"
-- 
2.25.1



[PATCH 04/13] configs: add the Librem5 defconfig

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 defconfig

Signed-off-by: Angus Ainslie 
---
 configs/librem5_defconfig | 120 ++
 1 file changed, 120 insertions(+)
 create mode 100644 configs/librem5_defconfig

diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
new file mode 100644
index 00..23f4260403
--- /dev/null
+++ b/configs/librem5_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x4020
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x3FE000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-librem5"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_LIBREM5=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x4048
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_WARN=y
+# CONFIG_SPL_BLK is not set
+CONFIG_SAVED_DRAM_TIMING_BASE=0x4000
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4300
+CONFIG_FASTBOOT_BUF_SIZE=0x4000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
+# CONFIG_SPL_DM_GPIO is not set
+CONFIG_GPIO_HOG=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_EARLY_INIT=y
+CONFIG_SYS_MXC_I2C1_SPEED=5
+CONFIG_SYS_MXC_I2C2_SPEED=5
+CONFIG_SYS_MXC_I2C3_SPEED=5
+CONFIG_SYS_MXC_I2C4_SPEED=5
+CONFIG_SYS_I2C_SPEED=5
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Purism"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_SDP_LOADADDR=0x4040
-- 
2.25.1



[PATCH 05/13] include: configs: add the librem5.h include file

2022-01-17 Thread Angus Ainslie
Initial commit of the librem5.h configuration

Signed-off-by: Angus Ainslie 
---
 include/configs/librem5.h | 171 ++
 1 file changed, 171 insertions(+)
 create mode 100644 include/configs/librem5.h

diff --git a/include/configs/librem5.h b/include/configs/librem5.h
new file mode 100644
index 00..e20516ffd6
--- /dev/null
+++ b/include/configs/librem5.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ * Copyright 2018 Emcraft Systems
+ * Copyright 2019 Purism
+ *
+ */
+
+#ifndef __LIBREM5_H
+#define __LIBREM5_H
+
+/* #define DEBUG */
+
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_MAX_SIZE(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_THERM_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK   0x187FF0
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR  0x0018
+#define CONFIG_SPL_BSS_MAX_SIZE0x2000  /* 8 KB */
+#define CONFIG_SPL_STACK_R_ADDR0x4230
+#define CONFIG_SPL_STACK_R
+#define CONFIG_SYS_SPL_MALLOC_START0x4220
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8 /* 512 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_MALLOC_F_ADDR   0x182000 /* malloc f used before 
GD_FLG_FULL_MALLOC_INIT */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not 
panic */
+
+#undef CONFIG_SPL_DM_PMIC
+#undef CONFIG_SPL_DM_I2C
+#undef CONFIG_SPL_DM_PMIC_BD71837
+#undef CONFIG_DM_USB
+#undef CONFIG_SPL_DM_USB
+#undef CONFIG_USB_DWC3_GENERIC
+#undef CONFIG_DEVRES
+
+#define CONFIG_SYS_I2C
+
+#define CONFIG_POWER_BD71837
+#define CONFIG_POWER_BD71837_I2C_BUS   0
+#define CONFIG_POWER_BD71837_I2C_ADDR  0x4B
+
+#define CONFIG_SPL_DMA_SUPPORT
+
+#define CONFIG_SYS_FSL_USDHC_NUM   1
+
+#else /* CONFIG_SPL_BUILD*/
+
+#define CONFIG_SYS_FSL_USDHC_NUM   2
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#endif /* CONFIG_SPL_BUILD*/
+
+#define CONSOLE_ON_UART1
+#define CONFIG_BAUDRATE115200
+
+#ifdef CONSOLE_ON_UART1
+#define CONFIG_MXC_UART_BASE   UART1_BASE_ADDR
+#define CONSOLE_UART_CLK   0
+#define CONSOLE"ttymxc0"
+#elif defined(CONSOLE_ON_UART2)
+#define CONFIG_MXC_UART_BASE   UART2_BASE_ADDR
+#define CONSOLE_UART_CLK   1
+#define CONSOLE"ttymxc1"
+#elif defined(CONSOLE_ON_UART3)
+#define CONFIG_MXC_UART_BASE   UART3_BASE_ADDR
+#define CONSOLE_UART_CLK   2
+#define CONSOLE"ttymxc2"
+#elif defined(CONSOLE_ON_UART4)
+#define CONFIG_MXC_UART_BASE   UART4_BASE_ADDR
+#define CONSOLE_UART_CLK   3
+#define CONSOLE"ttymxc3"
+#else
+#define CONFIG_MXC_UART_BASE   UART1_BASE_ADDR
+#define CONSOLE_UART_CLK   0
+#define CONSOLE"ttymxc0"
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_POSTCLK_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
+   func(USB, usb, 0) \
+   func(PXE, pxe, na) \
+   func(DHCP, dhcp, na)
+#include 
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+   "scriptaddr=0x8000\0" \
+   "pxefile_addr_r=0x8010\0" \
+   "kernel_addr_r=0x8080\0" \
+   "fdt_addr_r=0x8300\0" \
+   "ramdisk_addr_r=0x8380\0" \
+   "console=" CONSOLE ",115200\0" \
+   "bootargs=u_boot_version=" PLAIN_VERSION "\0" \
+   "stdin=nc,serial\0" \
+   "stdout=nc,serial\0" \
+   "stderr=nc,serial\0" \
+   BOOTENV
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE   0x4020
+
+#define CONFIG_SYS_INIT_RAM_ADDR0x4000
+#define CONFIG_SYS_INIT_RAM_SIZE0x8
+#define CONFIG_SYS_INIT_SP_OFFSET \
+   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+   (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MMCROOT "/dev/mmcblk0p2"  /* USDHC1 */
+
+#define CONFIG_SYS_SDRAM_BASE   0x4000
+#define PHYS_SDRAM  0x4000
+#define PHYS_SDRAM_SIZE   

[PATCH 07/13] board: librem5: add the u-boot header for the Librem5

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 u-boot header file

Signed-off-by: Angus Ainslie 
---
 board/purism/librem5/librem5.h | 176 +
 1 file changed, 176 insertions(+)
 create mode 100644 board/purism/librem5/librem5.h

diff --git a/board/purism/librem5/librem5.h b/board/purism/librem5/librem5.h
new file mode 100644
index 00..54e8f5adf2
--- /dev/null
+++ b/board/purism/librem5/librem5.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Purism
+ */
+
+#ifndef __LIBREM5_H__
+#define __LIBREM5_H__
+
+#define CAMERA_EN IMX_GPIO_NR(1, 0)
+#define SD_EN IMX_GPIO_NR(1, 3)
+#define AUDIO_EN IMX_GPIO_NR(1, 4)
+#define DSI_EN IMX_GPIO_NR(1, 5)
+#define SMC_EN IMX_GPIO_NR(1, 6)
+#define TYPEC_MUX_EN IMX_GPIO_NR(1, 11)
+#define HUB_NRESET IMX_GPIO_NR(1, 12)
+#define HUB_EN IMX_GPIO_NR(1, 14)
+#define VOL_UP IMX_GPIO_NR(1, 16)
+#define VOL_DOWN IMX_GPIO_NR(1, 17)
+#define DSI_BIAS_EN IMX_GPIO_NR(1, 20)
+#define FLASH_EN IMX_GPIO_NR(1, 23)
+#define WWAN_NRESET IMX_GPIO_NR(3, 1)
+#define CHG_EN IMX_GPIO_NR(3, 2)
+#define CHG_OTG_OUT_EN IMX_GPIO_NR(3, 4)
+#define WIFI_EN IMX_GPIO_NR(3, 10)
+#define GPS_EN IMX_GPIO_NR(3, 12)
+#define BL_EN IMX_GPIO_NR(3, 14)
+#define WWAN_EN IMX_GPIO_NR(3, 18)
+#define NFC_EN IMX_GPIO_NR(4, 28)
+#define LED_G IMX_GPIO_NR(5, 2)
+#define LED_R IMX_GPIO_NR(5, 3)
+#define LED_B IMX_GPIO_NR(1, 13)
+#define MOTO IMX_GPIO_NR(5, 5)
+#define SPI1_SCLK IMX_GPIO_NR(5, 6)
+#define SPI1_MOSI IMX_GPIO_NR(5, 7)
+#define SPI1_MISO IMX_GPIO_NR(5, 8)
+#define SPI1_SS0 IMX_GPIO_NR(5, 9)
+
+#define UART1_TX IMX_GPIO_NR(5, 23)
+#define UART1_RX IMX_GPIO_NR(5, 22)
+#define UART2_TX IMX_GPIO_NR(5, 25)
+#define UART2_RX IMX_GPIO_NR(5, 24)
+#define UART3_TX IMX_GPIO_NR(5, 27)
+#define UART3_RX IMX_GPIO_NR(5, 26)
+#define UART4_TX IMX_GPIO_NR(5, 11)
+#define UART4_RX IMX_GPIO_NR(5, 10)
+
+#define TPS_RESET IMX_GPIO_NR(3, 24)
+
+#define PURISM_VID 0x316d
+#define PURISM_PID 0x4c05
+
+#define BOARD_REV_ERROR"unknown"
+#define BOARD_REV_BIRCH"1"
+#define BOARD_REV_CHESTNUT "2"
+#define BOARD_REV_DOGWOOD  "3"
+/* Could be ASPEN, BIRCH or CHESTNUT. assume CHESTNUT */
+#define BOARD_REV_UNKNOWN  BOARD_REV_CHESTNUT
+
+#ifdef CONFIG_DM_GPIO
+static inline void init_pinmux(void)
+{
+   gpio_request(WIFI_EN, "WIFI_EN");
+#ifdef CONSOLE_ON_UART4
+   gpio_direction_output(WIFI_EN, 1);
+#else
+   gpio_direction_output(WIFI_EN, 0);
+#endif /* CONSOLE_ON_UART4 */
+}
+#else
+static const iomux_v3_cfg_t configure_pads[] = {
+   IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 | MUX_PAD_CTRL(PAD_CTL_PUE),
+   IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 | MUX_PAD_CTRL(PAD_CTL_PUE),
+   IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+   IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24,
+};
+
+static inline void init_pinmux(void)
+{
+   imx_iomux_v3_setup_multiple_pads(configure_pads, 
ARRAY_SIZE(configure_pads));
+
+   gpio_request(LED_R, "LED_R");
+   gpio_request(LED_G, "LED_G");
+   gpio_request(LED_B, "LED_B");
+   gpio_request(VOL_UP, "VOL_UP");
+   gpio_request(VOL_DOWN, "VOL_DOWN");
+
+   gpio_request(NFC_EN, "NFC_EN");
+   gpio_request(CHG_EN, "CHG_EN");
+   gpio_request(CHG_OTG_OUT_EN, "CHG_OTG_OUT_EN");
+
+   gpio_request(TYPEC_MUX_EN, "TYPEC_MUX_EN");
+
+   gpio_request(TPS_RESET, "TPS_RESET");
+
+   gpio_request(WWAN_EN, "WWAN_EN");
+   gpio_request(WWAN_NRESET, "WWAN_NRESET");
+
+   gpio_request(HUB_EN, "HUB_EN");
+   gpio_request(HUB_NRESET, "HUB_NRESET");
+   gpio_request(SD_EN, "SD_EN");
+   gpio_request(AUDIO_EN, "AUDIO_EN");
+   gpio_request(DSI_EN, "DSI_EN");
+   gpio_requ

[PATCH 08/13] board: librem5: add the SPL source for the Librem5

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 SPL source

Signed-off-by: Angus Ainslie 
Co-developed-by: Sebastian Krzyszkowiak 
Signed-off-by: Sebastian Krzyszkowiak 
---
 board/purism/librem5/spl.c | 481 +
 1 file changed, 481 insertions(+)
 create mode 100644 board/purism/librem5/spl.c

diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
new file mode 100644
index 00..976033a6e5
--- /dev/null
+++ b/board/purism/librem5/spl.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2021 Purism
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "librem5.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+   /* ddr init */
+   if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
+   ddr_init(&dram_timing);
+   else
+   ddr_init(&dram_timing_b0);
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+   log_debug("%s : starting\n", __func__);
+
+   switch (boot_dev_spl) {
+   case SD1_BOOT:
+   case MMC1_BOOT:
+   return BOOT_DEVICE_MMC1;
+   case USB_BOOT:
+   return BOOT_DEVICE_BOARD;
+   default:
+   return BOOT_DEVICE_NONE;
+   }
+}
+
+#define I2C_PAD_CTRL   (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | 
PAD_CTL_FSEL3)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+   .scl = {
+   .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+   .gp = IMX_GPIO_NR(5, 14),
+   },
+   .sda = {
+   .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+   .gp = IMX_GPIO_NR(5, 15),
+   },
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+   .scl = {
+   .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
+   .gp = IMX_GPIO_NR(5, 16),
+   },
+   .sda = {
+   .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
+   .gp = IMX_GPIO_NR(5, 17),
+   },
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+   .scl = {
+   .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
+   .gp = IMX_GPIO_NR(5, 18),
+   },
+   .sda = {
+   .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
+   .gp = IMX_GPIO_NR(5, 19),
+   },
+};
+
+struct i2c_pads_info i2c_pad_info4 = {
+   .scl = {
+   .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC,
+   .gp = IMX_GPIO_NR(5, 20),
+   },
+   .sda = {
+   .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC,
+   .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC,
+   .gp = IMX_GPIO_NR(5, 21),
+   },
+};
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+   IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+   IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+   int ret = 0;
+
+   switch (cfg->esdhc_base) {
+   case USDHC1_BASE_ADDR:
+   ret = 1;
+   break;
+   case USDHC2_BASE_ADDR:
+   ret = 1;
+   break;
+   }
+
+   return ret;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+PAD_CTL_FSEL1)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static const iomux_v3_cfg_t usdhc1_pads[] = {
+   IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USD

[PATCH 11/13] board: librem5: add Librem5 MAINTAINERS file

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 MAINTAINERS file

Signed-off-by: Angus Ainslie 
---
 board/purism/librem5/MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)
 create mode 100644 board/purism/librem5/MAINTAINERS

diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS
new file mode 100644
index 00..818e185030
--- /dev/null
+++ b/board/purism/librem5/MAINTAINERS
@@ -0,0 +1,7 @@
+PURISM LIBREM5 PHONE
+M: Angus Ainslie 
+R: ker...@puri.sm
+S: Supported
+F: board/purism/librem5/
+F: configs/librem5_defconfig
+F: include/configs/librem5.h
-- 
2.25.1



[PATCH 06/13] board: librem5: add the u-boot source for the Librem5

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 u-boot source

Signed-off-by: Angus Ainslie 
Co-developed-by: Sebastian Krzyszkowiak 
Signed-off-by: Sebastian Krzyszkowiak 
---
 board/purism/librem5/librem5.c | 708 +
 1 file changed, 708 insertions(+)
 create mode 100644 board/purism/librem5/librem5.c

diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c
new file mode 100644
index 00..b48e737e31
--- /dev/null
+++ b/board/purism/librem5/librem5.c
@@ -0,0 +1,708 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2021 Purism
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "librem5.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ENABLE_TPS_RESET
+
+#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+   IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+   struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+   log_debug("%s: starting\n", __func__);
+
+   imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+   set_wdog_reset(wdog);
+
+   return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+   /* TODO */
+   return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_USB
+int usb_gadget_handle_interrupts(void)
+{
+   dwc3_uboot_handle_interrupt(0);
+   return 0;
+}
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+   u32 RegData;
+
+   RegData = readl(dwc3->base + USB_PHY_CTRL1);
+   RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+   USB_PHY_CTRL1_COMMONONN);
+   RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+   writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+   RegData = readl(dwc3->base + USB_PHY_CTRL0);
+   RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+   writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+   RegData = readl(dwc3->base + USB_PHY_CTRL2);
+   RegData |= USB_PHY_CTRL2_TXENABLEN0;
+   writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+   RegData = readl(dwc3->base + USB_PHY_CTRL1);
+   RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+   writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+
+static struct dwc3_device dwc3_device0_data = {
+#ifdef CONFIG_SPL_BUILD
+   .maximum_speed = USB_SPEED_HIGH,
+#else
+   .maximum_speed = USB_SPEED_SUPER,
+#endif
+   .base = USB1_BASE_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 0,
+   .dis_u2_susphy_quirk = 1,
+};
+
+static struct dwc3_device dwc3_device1_data = {
+#ifdef CONFIG_SPL_BUILD
+   .maximum_speed = USB_SPEED_HIGH,
+#else
+   .maximum_speed = USB_SPEED_SUPER,
+#endif
+   .base = USB2_BASE_ADDR,
+   .dr_mode = USB_DR_MODE_HOST,
+   .index = 1,
+   .dis_u2_susphy_quirk = 1,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   int ret = 0;
+
+   imx8m_usb_power(index, true);
+
+   if (index == 0 && init == USB_INIT_DEVICE) {
+   dwc3_nxp_usb_phy_init(&dwc3_device0_data);
+   ret = dwc3_uboot_init(&dwc3_device0_data);
+   }
+   if (index == 1 && init == USB_INIT_HOST) {
+   dwc3_nxp_usb_phy_init(&dwc3_device1_data);
+   ret = dwc3_uboot_init(&dwc3_device1_data);
+   }
+
+   log_debug("%s: ending %d\n", __func__, ret);
+
+   return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   int ret = 0;
+
+   if (index == 0 && init == USB_INIT_DEVICE)
+   dwc3_uboot_exit(index);
+
+   if (index == 1 && init == USB_INIT_HOST)
+   dwc3_uboot_exit(index);
+
+   imx8m_usb_power(index, false);
+
+   return ret;
+}
+#endif
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+   return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+}
+#endif
+
+#ifdef CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION
+uint board_mmc_get_env_part(struct mmc *mmc)
+{
+   log_debug("%s: starting\n", __func__);
+   uint part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+   if (part == 7)
+   part = 0;
+   return part;
+}
+#endif
+
+#define SPI_FLASH_CS IMX_GPIO_NR(5, 9)
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+   return (bus == 0 && cs == 0) ? (SPI_FLASH_CS) : -1;
+}
+
+#define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t ecspi_pads[] = {
+   IMX8MQ_PAD_ECSPI1_SCLK__ECS

[PATCH 01/13] MAINTAINERS: add Purism to the maintainers file

2022-01-17 Thread Angus Ainslie
The Purism kernel team is in charge of maintianing the Librem5 u-boot

Signed-off-by: Angus Ainslie 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 38c68ee87d..45754b16d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1079,6 +1079,15 @@ S:   Maintained
 T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F: arch/powerpc/cpu/mpc85xx/
 
+PURISM LIBREM5 PHONE
+M: Angus Ainslie 
+R: ker...@puri.sm
+S: Supported
+F: arch/arm/dts/imx8mq-*
+F: board/purism/librem5/
+F: configs/librem5_defconfig
+F: include/configs/librem5.h
+
 RISC-V
 M: Rick Chen 
 M: Leo 
-- 
2.25.1



[PATCH 12/13] board: librem5: add Librem5 build files

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 Makefile and Kconfig

Signed-off-by: Angus Ainslie 
---
 board/purism/librem5/Kconfig  | 15 +++
 board/purism/librem5/Makefile | 13 +
 2 files changed, 28 insertions(+)
 create mode 100644 board/purism/librem5/Kconfig
 create mode 100644 board/purism/librem5/Makefile

diff --git a/board/purism/librem5/Kconfig b/board/purism/librem5/Kconfig
new file mode 100644
index 00..cf0f303683
--- /dev/null
+++ b/board/purism/librem5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LIBREM5
+
+config SYS_BOARD
+   default "librem5"
+
+config SYS_VENDOR
+   default "purism"
+
+config SYS_CONFIG_NAME
+   default "librem5"
+
+config IMX_CONFIG
+   default "board/purism/librem5/imximage-8mq-lpddr4.cfg"
+
+endif
diff --git a/board/purism/librem5/Makefile b/board/purism/librem5/Makefile
new file mode 100644
index 00..47f25f047b
--- /dev/null
+++ b/board/purism/librem5/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2017 NXP
+# Copyright 2019 Purism
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y += librem5.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
+endif
-- 
2.25.1



[PATCH 02/13] arm: dts: add the Purism devicetree files

2022-01-17 Thread Angus Ainslie
Initial commit of Librem5 devicetree files

Signed-off-by: Angus Ainslie 
---
 arch/arm/dts/Makefile   |   3 +-
 arch/arm/dts/imx8mq-librem5-u-boot.dtsi | 134 ++
 arch/arm/dts/imx8mq-librem5.dts | 593 
 3 files changed, 729 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8mq-librem5-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mq-librem5.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeaec7136f..7a829522c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -912,7 +912,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
-   imx8mq-pico-pi.dtb
+   imx8mq-pico-pi.dtb \
+   imx8mq-librem5.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-u-boot.dtsi 
b/arch/arm/dts/imx8mq-librem5-u-boot.dtsi
new file mode 100644
index 00..e3f780ca75
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-u-boot.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+&binman {
+   u-boot-spl-ddr {
+   filename = "u-boot-spl-ddr.bin";
+   pad-byte = <0xff>;
+   align-size = <4>;
+   align = <4>;
+
+   u-boot-spl {
+   align-end = <4>;
+   };
+
+   blob_1: blob-ext@1 {
+   filename = "lpddr4_pmu_train_1d_imem.bin";
+   size = <0x8000>;
+   };
+
+   blob_2: blob-ext@2 {
+   filename = "lpddr4_pmu_train_1d_dmem.bin";
+   size = <0x4000>;
+   };
+
+   blob_3: blob-ext@3 {
+   filename = "lpddr4_pmu_train_2d_imem.bin";
+   size = <0x8000>;
+   };
+
+   blob_4: blob-ext@4 {
+   filename = "lpddr4_pmu_train_2d_dmem.bin";
+   size = <0x4000>;
+   };
+   };
+
+   spl {
+   filename = "spl.bin";
+
+   mkimage {
+   args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 
0x7e1000";
+
+   blob {
+   filename = "u-boot-spl-ddr.bin";
+   };
+   };
+   };
+
+   itb {
+   filename = "u-boot.itb";
+
+   fit {
+   description = "Configuration to load ATF before U-Boot";
+   #address-cells = <1>;
+   fit,external-offset = ;
+
+   images {
+   uboot {
+   description = "U-Boot (64-bit)";
+   type = "standalone";
+   arch = "arm64";
+   compression = "none";
+   load = ;
+
+   uboot_blob: blob-ext {
+   filename = "u-boot-nodtb.bin";
+   };
+   };
+
+   atf {
+   description = "ARM Trusted Firmware";
+   type = "firmware";
+   arch = "arm64";
+   compression = "none";
+   load = <0x91>;
+   entry = <0x91>;
+
+   atf_blob: blob-ext {
+   filename = "bl31.bin";
+   };
+   };
+
+   fdt {
+   description = "NAME";
+   type = "flat_dt";
+   compression = "none";
+
+   uboot_fdt_blob: blob-ext {
+   filename = "u-boot.dtb";
+   };
+   };
+   };
+
+   configurations {
+   default = "conf";
+
+   conf {
+   description = "NAME";
+   firmware = "uboot";
+   loadables = "atf";
+   fdt = "fdt";
+   };
+   };
+   };
+   };
+
+   imx-boot {
+   filename = "flash.bin";
+   pad-byte = <0x

[PATCH 13/13] doc: librem5: add Librem5 documentation

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 documentation

Signed-off-by: Angus Ainslie 
---
 doc/board/purism/librem5/librem5.rst | 60 
 1 file changed, 60 insertions(+)
 create mode 100644 doc/board/purism/librem5/librem5.rst

diff --git a/doc/board/purism/librem5/librem5.rst 
b/doc/board/purism/librem5/librem5.rst
new file mode 100644
index 00..d380d48c71
--- /dev/null
+++ b/doc/board/purism/librem5/librem5.rst
@@ -0,0 +1,60 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Librem5
+==
+
+U-Boot for the Purism Librem5 phone
+
+Quick Start
+---
+
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi firmware
+- Build U-Boot
+
+Get and Build the ARM Trusted firmware
+--
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.puri.sm/Librem5/arm-trusted-firmware
+branch: librem5
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mq bl31
+   $ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+-
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.bin
+   $ chmod +x firmware-imx-8.10.bin
+   $ ./firmware-imx-8.10.bin
+   $ cp firmware-imx-8.10/firmware/hdmi/cadence/signed_hdmi_imx8m.bin 
$(builddir)
+   $ cp firmware-imx-8.10/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-linux-gnu
+   $ make librem5_defconfig
+   $ make flash.bin
+
+Burn the flash.bin
+--
+
+Use uuu to burn flash.bin. Power on the phone while holding vol+ to get it
+into uuu mode.
+
+.. code-block:: bash
+
+   $ git clone https://source.puri.sm/Librem5/librem5-devkit-tools.git
+   $ cd librem5-devkit-tools
+   $ cp $(builddir)/flash.bin files/
+   $ uuu uuu_scripts/u-boot_flash_librem5.lst
+
+Reboot the phone.
-- 
2.25.1



[PATCH 09/13] board: librem5: add the LPDDR4 source for the Librem5

2022-01-17 Thread Angus Ainslie
This is a copy of imx8mq LPDDR4 source files

Signed-off-by: Angus Ainslie 
---
 board/purism/librem5/lpddr4_timing.c| 1324 +++
 board/purism/librem5/lpddr4_timing_b0.c | 1191 
 2 files changed, 2515 insertions(+)
 create mode 100644 board/purism/librem5/lpddr4_timing.c
 create mode 100644 board/purism/librem5/lpddr4_timing_b0.c

diff --git a/board/purism/librem5/lpddr4_timing.c 
b/board/purism/librem5/lpddr4_timing.c
new file mode 100644
index 00..46bc7f8591
--- /dev/null
+++ b/board/purism/librem5/lpddr4_timing.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define WR_POST_EXT_3200   /* recommened to define */
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+   /* Start to config, default 3200mbps */
+   { DDRC_DBG1(0), 0x0001 },
+   { DDRC_PWRCTL(0), 0x0001 },
+   { DDRC_MSTR(0), 0xa3080020 },
+   { DDRC_MSTR2(0), 0x },
+   { DDRC_RFSHTMG(0), 0x006100E0 },
+   { DDRC_INIT0(0), 0xC003061B },
+   { DDRC_INIT1(0), 0x009D },
+   { DDRC_INIT3(0), 0x00D4002D },
+#ifdef WR_POST_EXT_3200
+   { DDRC_INIT4(0), 0x00330008 },
+#else
+   { DDRC_INIT4(0), 0x00310008 },
+#endif
+   { DDRC_INIT6(0), 0x0066004a },
+   { DDRC_INIT7(0), 0x0006004a },
+
+   { DDRC_DRAMTMG0(0), 0x1A201B22 },
+   { DDRC_DRAMTMG1(0), 0x00060633 },
+   { DDRC_DRAMTMG3(0), 0x00C0C000 },
+   { DDRC_DRAMTMG4(0), 0x0F04080F },
+   { DDRC_DRAMTMG5(0), 0x02040C0C },
+   { DDRC_DRAMTMG6(0), 0x01010007 },
+   { DDRC_DRAMTMG7(0), 0x0401 },
+   { DDRC_DRAMTMG12(0), 0x00020600 },
+   { DDRC_DRAMTMG13(0), 0x0C12 },
+   { DDRC_DRAMTMG14(0), 0x00E6 },
+   { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+   { DDRC_ZQCTL0(0), 0x03200018 },
+   { DDRC_ZQCTL1(0), 0x028061A8 },
+   { DDRC_ZQCTL2(0), 0x },
+
+   { DDRC_DFITMG0(0), 0x0497820A },
+   { DDRC_DFITMG1(0), 0x00080303 },
+   { DDRC_DFIUPD0(0), 0xE0400018 },
+   { DDRC_DFIUPD1(0), 0x00DF00E4 },
+   { DDRC_DFIUPD2(0), 0x8000 },
+   { DDRC_DFIMISC(0), 0x0011 },
+   { DDRC_DFITMG2(0), 0x170A },
+
+   { DDRC_DBICTL(0), 0x0001 },
+   { DDRC_DFIPHYMSTR(0), 0x0001 },
+   { DDRC_RANKCTL(0), 0x0c99 },
+   { DDRC_DRAMTMG2(0), 0x070E171a },
+
+   /* address mapping */
+   { DDRC_ADDRMAP0(0), 0x0015 },
+   { DDRC_ADDRMAP3(0), 0x },
+   { DDRC_ADDRMAP4(0), 0x1F1F },
+   /* bank interleave */
+   { DDRC_ADDRMAP1(0), 0x00080808 },
+   { DDRC_ADDRMAP5(0), 0x07070707 },
+   { DDRC_ADDRMAP6(0), 0x08080707 },
+
+   /* performance setting */
+   { DDRC_ODTCFG(0), 0x0b060908 },
+   { DDRC_ODTMAP(0), 0x },
+   { DDRC_SCHED(0), 0x29511505 },
+   { DDRC_SCHED1(0), 0x002c },
+   { DDRC_PERFHPR1(0), 0x5900575b },
+   /* 150T starve and 0x90 max tran len */
+   { DDRC_PERFLPR1(0), 0x9096 },
+   /* 300T starve and 0x10 max tran len */
+   { DDRC_PERFWR1(0), 0x112c },
+   { DDRC_DBG0(0), 0x0016 },
+   { DDRC_DBG1(0), 0x },
+   { DDRC_DBGCMD(0), 0x },
+   { DDRC_SWCTL(0), 0x0001 },
+   { DDRC_POISONCFG(0), 0x0011 },
+   { DDRC_PCCFG(0), 0x0111 },
+   { DDRC_PCFGR_0(0), 0x10f3 },
+   { DDRC_PCFGW_0(0), 0x72ff },
+   { DDRC_PCTRL_0(0), 0x0001 },
+   /* disable Read Qos*/
+   { DDRC_PCFGQOS0_0(0), 0x0e00 },
+   { DDRC_PCFGQOS1_0(0), 0x0062 },
+   /* disable Write Qos*/
+   { DDRC_PCFGWQOS0_0(0), 0x0e00 },
+   { DDRC_PCFGWQOS1_0(0), 0x },
+
+   /* Frequency 1: 400mbps */
+   { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+   { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+   { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+   { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+   { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+   { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+   { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+   { DDRC_FREQ1_DRAMTMG7(0), 0x090e },
+   { DDRC_FREQ1_DRAMTMG14(0), 0x0032 },
+   { DDRC_FREQ1_DRAMTMG15(0), 0x },
+   { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+   { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+   { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+   { DDRC_FREQ1_DFITMG2(0), 0x },
+   { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+   { DDRC_FREQ1_INIT3(0), 0x0084 },
+   { DDRC_FREQ1_INIT4(0), 0x00310008 },
+   { DDRC_FREQ1_INIT6(0), 0x0066004a },
+   { DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+   /* Frequency 2: 100mbps */
+   { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+   { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+   { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
+   { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+   { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+   { DDRC_FREQ2_DRAMTMG5(0), 

[PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Angus Ainslie
I sent this patchset as a single monolithic patch and did not see any 
comment on it. 

https://lists.denx.de/pipermail/u-boot/2022-January/471087.html

Here it is as a set of patches instead.

This is all of the code required to boot the Librem5 Phone.

It can boot the phone in uuu mode or directly from the eMMC

Angus Ainslie (13):
  MAINTAINERS: add Purism to the maintainers file
  arm: dts: add the Purism devicetree files
  arm: imx8m: add Purism Librem5 Kconfig
  configs: add the Librem5 defconfig
  include: configs: add the librem5.h include file
  board: librem5: add the u-boot source for the Librem5
  board: librem5: add the u-boot header for the Librem5
  board: librem5: add the SPL source for the Librem5
  board: librem5: add the LPDDR4 source for the Librem5
  board: librem5: add SPL loader configuration
  board: librem5: add Librem5 MAINTAINERS file
  board: librem5: add Librem5 build files
  doc: librem5: add Librem5 documentation

 MAINTAINERS  |9 +
 arch/arm/dts/Makefile|3 +-
 arch/arm/dts/imx8mq-librem5-u-boot.dtsi  |  134 ++
 arch/arm/dts/imx8mq-librem5.dts  |  593 
 arch/arm/mach-imx/imx8m/Kconfig  |9 +
 board/purism/librem5/Kconfig |   15 +
 board/purism/librem5/MAINTAINERS |7 +
 board/purism/librem5/Makefile|   13 +
 board/purism/librem5/imximage-8mq-lpddr4.cfg |9 +
 board/purism/librem5/librem5.c   |  708 ++
 board/purism/librem5/librem5.h   |  176 +++
 board/purism/librem5/lpddr4_timing.c | 1324 ++
 board/purism/librem5/lpddr4_timing_b0.c  | 1191 
 board/purism/librem5/spl.c   |  481 +++
 configs/librem5_defconfig|  120 ++
 doc/board/purism/librem5/librem5.rst |   60 +
 include/configs/librem5.h|  171 +++
 17 files changed, 5022 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8mq-librem5-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mq-librem5.dts
 create mode 100644 board/purism/librem5/Kconfig
 create mode 100644 board/purism/librem5/MAINTAINERS
 create mode 100644 board/purism/librem5/Makefile
 create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
 create mode 100644 board/purism/librem5/librem5.c
 create mode 100644 board/purism/librem5/librem5.h
 create mode 100644 board/purism/librem5/lpddr4_timing.c
 create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
 create mode 100644 board/purism/librem5/spl.c
 create mode 100644 configs/librem5_defconfig
 create mode 100644 doc/board/purism/librem5/librem5.rst
 create mode 100644 include/configs/librem5.h

-- 
2.25.1



[PATCH v2 04/16] passage: Support an incoming passage

2022-01-17 Thread Simon Glass
Plumb in the ability for U-Boot proper to accept an incoming standard
passage from a previous phase, such as SPL or TF-A. This allows data to
be passed from binary to binary when firmware is booting.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Rebase to master
- Rework global_data for new stdpass convention

 common/Kconfig| 31 ++
 common/bloblist.c |  7 ++-
 common/board_f.c  | 32 ---
 include/asm-generic/global_data.h | 28 +++
 lib/asm-offsets.c |  6 ++
 5 files changed, 88 insertions(+), 16 deletions(-)

diff --git a/common/Kconfig b/common/Kconfig
index 82cd864baf9..59783d66cb8 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -757,6 +757,14 @@ config BLOBLIST_ALLOC
  specify a fixed address on systems where this is unknown or can
  change at runtime.
 
+config BLOBLIST_PASSAGE
+   bool "Obtain bloblist from standard passage information"
+   help
+ Rather than allocating the bloblist, get it from the standard
+ passage provided by an earlier phase, e.g. SPL. The bloblist address
+ and size are used as is, except that the bloblist is of course
+ relocated when U-Boot relocates.
+
 endchoice
 
 config BLOBLIST_ADDR
@@ -815,6 +823,13 @@ config SPL_BLOBLIST_ALLOC
  specify a fixed address on systems where this is unknown or can
  change at runtime.
 
+config SPL_BLOBLIST_PASSAGE
+   bool "Obtain bloblist from standard passage information"
+   help
+ Rather than allocating the bloblist, get it from the standard
+ passage provided by an earlier phase, e.g. TPL. The bloblist address
+ and size are used as is within SPL, then passed on to U-Boot.
+
 endchoice
 
 endif # SPL_BLOBLIST
@@ -850,6 +865,22 @@ endif # TPL_BLOBLIST
 
 endmenu
 
+config PASSAGE_IN
+   bool "Support the standard-passage protocol (in)"
+   help
+ This enables a standard protocol for entering U-Boot, providing
+ parameters in a bloblist with a devicetree. It allows the various
+ firmware phases to communicate state and settings to following
+ phases.
+
+config SPL_PASSAGE_IN
+   bool "Support the standard-passage protocol in SPL (in)"
+   help
+ This enables a standard protocol for entering SPL, providing
+ parameters in a bloblist and a devicetree. It allows the various
+ firmware phases to communicate state and settings to following
+ phases.
+
 source "common/spl/Kconfig"
 
 config IMAGE_SIGN_INFO
diff --git a/common/bloblist.c b/common/bloblist.c
index 406073c8105..df45d45de90 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -441,7 +441,8 @@ int bloblist_init(void)
 * allocated bloblist from a previous stage, so it must be at a fixed
 * address.
 */
-   expected = fixed && !u_boot_first_phase();
+   expected = (fixed || CONFIG_IS_ENABLED(BLOBLIST_PASSAGE)) &&
+   !u_boot_first_phase();
if (spl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
expected = false;
if (fixed)
@@ -449,6 +450,10 @@ int bloblist_init(void)
  CONFIG_BLOBLIST_ADDR);
size = CONFIG_BLOBLIST_SIZE;
if (expected) {
+   if (CONFIG_IS_ENABLED(BLOBLIST_PASSAGE)) {
+   addr = gd->passage_bloblist;
+   size = 0;
+   }
ret = bloblist_check(addr, size);
if (ret) {
log_warning("Expected bloblist at %lx not found 
(err=%d)\n",
diff --git a/common/board_f.c b/common/board_f.c
index a68760092ac..04d98366bd6 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -570,11 +570,13 @@ static int reserve_stacks(void)
 static int reserve_bloblist(void)
 {
 #ifdef CONFIG_BLOBLIST
+   int new_size = CONFIG_BLOBLIST_SIZE_RELOC;
+
+   if (!new_size)
+   new_size = bloblist_get_size();
/* Align to a 4KB boundary for easier reading of addresses */
-   gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
-  CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
-   gd->new_bloblist = map_sysmem(gd->start_addr_sp,
- CONFIG_BLOBLIST_SIZE_RELOC);
+   gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - new_size, 0x1000);
+   gd->new_bloblist = map_sysmem(gd->start_addr_sp, new_size);
 #endif
 
return 0;
@@ -655,21 +657,21 @@ static int reloc_bootstage(void)
 static int reloc_bloblist(void)
 {
 #ifdef CONFIG_BLOBLIST
-   /*
-* Relocate only if we are supposed to send it
-*/
-   if ((gd->flags & GD_FLG_SKIP_RELOC) &&
-   CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
+   int size = bloblist_get_size();
+   int new_size = CONFIG_BLOBLIST_SIZE

[PATCH v2 07/16] passage: spl: Support adding the dtb to the passage bloblist

2022-01-17 Thread Simon Glass
Add an option for SPL to add a devicetree to the passage bloblist, so
SPL can provide the devicetree to U-Boot.

Signed-off-by: Simon Glass 
---

(no changes since v1)

 common/Kconfig   | 20 
 common/spl/spl.c | 44 ++--
 include/spl.h|  2 ++
 3 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/common/Kconfig b/common/Kconfig
index 59783d66cb8..bf6bff22e71 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -881,6 +881,26 @@ config SPL_PASSAGE_IN
  firmware phases to communicate state and settings to following
  phases.
 
+config SPL_PASSAGE_OUT
+   bool "Support the standard-passage protocol in SPL (out)"
+   depends on SPL_BLOBLIST
+   default y if PASSAGE_IN
+   help
+ This enables a standard protocol for entering U-Boot, providing
+ parameters in a bloblist and a devicetree. It allows the various
+ firmware stages to communicate state and settings to following
+ stages.
+
+config SPL_PASSAGE_ADD_DTB
+   bool "Add devicetree to the outgoing passage"
+   depends on SPL_PASSAGE_OUT
+   default y if SPL_PASSAGE_OUT && !SPL_PASSAGE_IN
+   help
+ Add the devicetree into the bloblist in SPL (it is assumed to not
+ already be there) so that the next phase (U-Boot) can find it.
+
+ This option should be enabled in the phase that sets up the passage.
+
 source "common/spl/Kconfig"
 
 config IMAGE_SIGN_INFO
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d54356b6a28..be770d0226c 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -56,6 +56,11 @@ binman_sym_declare(ulong, spl, image_pos);
 binman_sym_declare(ulong, spl, size);
 #endif
 
+#if CONFIG_IS_ENABLED(PASSAGE_ADD_DTB)
+binman_sym_declare(ulong, u_boot_dtb, image_pos);
+binman_sym_declare(ulong, u_boot_dtb, size);
+#endif
+
 /* Define board data structure */
 static struct bd_info bdata __attribute__ ((section(".data")));
 
@@ -406,7 +411,8 @@ static int setup_spl_handoff(void)
 {
struct spl_handoff *ho;
 
-   ho = bloblist_ensure(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(struct 
spl_handoff));
+   ho = bloblist_ensure(BLOBLISTT_U_BOOT_SPL_HANDOFF,
+sizeof(struct spl_handoff));
if (!ho)
return -ENOENT;
 
@@ -423,7 +429,8 @@ static int write_spl_handoff(void)
struct spl_handoff *ho;
int ret;
 
-   ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(struct 
spl_handoff));
+   ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
+  sizeof(struct spl_handoff));
if (!ho)
return -ENOENT;
handoff_save_dram(ho);
@@ -440,6 +447,33 @@ static inline int write_spl_handoff(void) { return 0; }
 
 #endif /* HANDOFF */
 
+/**
+ * Write the devicetree for the next phase into the passage
+ *
+ * For now we assume the next phase is U-Boot proper
+ *
+ * @return 0 on success,  -ENOSPC if it is missing and could not be added due 
to
+ * lack of space, or -ESPIPE it exists but has the wrong size
+ */
+static int passage_write_dtb(void)
+{
+#if CONFIG_IS_ENABLED(PASSAGE_ADD_DTB)
+   ulong start = binman_sym(ulong, u_boot_dtb, image_pos);
+   ulong size = binman_sym(ulong, u_boot_dtb, size);
+   void *dtb;
+   int ret;
+
+   log_debug("passage: Adding control dtb size %lx\n", size);
+   ret = bloblist_ensure_size(BLOBLISTT_CONTROL_DTB, size, 0,
+  (void **)&dtb);
+   if (ret)
+   return ret;
+   memcpy(dtb, map_sysmem(start, size), size);
+#endif
+
+   return 0;
+}
+
 /**
  * get_bootstage_id() - Get the bootstage ID to emit
  *
@@ -761,6 +795,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
printf(SPL_TPL_PROMPT
   "SPL hand-off write failed (err=%d)\n", ret);
}
+   if (CONFIG_IS_ENABLED(PASSAGE_ADD_DTB)) {
+   ret = passage_write_dtb();
+   if (ret)
+   printf(SPL_TPL_PROMPT
+  "Write DTB failed (err=%d)\n", ret);
+   }
if (CONFIG_IS_ENABLED(BLOBLIST)) {
ret = bloblist_finish();
if (ret)
diff --git a/include/spl.h b/include/spl.h
index a4d5cedad3a..472b171f5be 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -270,6 +270,8 @@ binman_sym_extern(ulong, u_boot_any, image_pos);
 binman_sym_extern(ulong, u_boot_any, size);
 binman_sym_extern(ulong, spl, image_pos);
 binman_sym_extern(ulong, spl, size);
+binman_sym_extern(ulong, u_boot_dtb, image_pos);
+binman_sym_extern(ulong, u_boot_dtb, size);
 
 /**
  * spl_get_image_pos() - get the image position of the next phase
-- 
2.34.1.703.g22d0c6ccf7-goog



[PATCH 10/13] board: librem5: add SPL loader configuration

2022-01-17 Thread Angus Ainslie
Initial commit of the Librem5 SPL loader configuration

Signed-off-by: Angus Ainslie 
---
 board/purism/librem5/imximage-8mq-lpddr4.cfg | 9 +
 1 file changed, 9 insertions(+)
 create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg

diff --git a/board/purism/librem5/imximage-8mq-lpddr4.cfg 
b/board/purism/librem5/imximage-8mq-lpddr4.cfg
new file mode 100644
index 00..90573be5fd
--- /dev/null
+++ b/board/purism/librem5/imximage-8mq-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM  sd
+LOADER u-boot-spl-ddr.bin  0x7E1000
-- 
2.25.1



[PATCH v3] spl: add support for custom boot method names

2022-01-17 Thread Heiko Thiery
Currently the names MMC1, MMC2 and MMC2_2 are output in the SPL. To
achieve more userbility here the name of the boot source can be returned.
E.g. for "MMC1" -> "eMMC" or "MMC2" -> "SD card".

Signed-off-by: Heiko Thiery 
Reviewed-by: Michael Walle 
Tested-by: Michael Walle 
---
v2:
 - add function documenation

v3:
 - fix in documentation


 common/spl/spl.c |  5 +
 include/spl.h| 15 ++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4c101ec5d3..b7b53f352e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -174,6 +174,11 @@ __weak void spl_board_prepare_for_optee(void *fdt)
 {
 }
 
+__weak const char *spl_board_loader_name(u32 boot_device)
+{
+   return NULL;
+}
+
 #if CONFIG_IS_ENABLED(OPTEE_IMAGE)
 __weak void __noreturn jump_to_image_optee(struct spl_image_info *spl_image)
 {
diff --git a/include/spl.h b/include/spl.h
index 0af0ee3003..247267bfa0 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -459,6 +459,17 @@ void spl_board_prepare_for_boot(void);
 int spl_board_ubi_load_image(u32 boot_device);
 int spl_board_boot_device(u32 boot_device);
 
+/**
+ * spl_board_loader_name() - Return a name for the loader
+ *
+ * This is a weak function which might be overridden by the board code. With
+ * that a board specific value for the device where the U-Boot will be loaded
+ * from can be set. By default it returns NULL.
+ *
+ * @boot_device:   ID of the device which SPL wants to load U-Boot from.
+ */
+const char *spl_board_loader_name(u32 boot_device);
+
 /**
  * jump_to_image_linux() - Jump to a Linux kernel from SPL
  *
@@ -541,7 +552,9 @@ struct spl_image_loader {
 static inline const char *spl_loader_name(const struct spl_image_loader 
*loader)
 {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   return loader->name;
+   const char *name;
+   name = spl_board_loader_name(loader->boot_device);
+   return name ?: loader->name;
 #else
return NULL;
 #endif
-- 
2.30.2



Re: [PATCH 0/3] sandox: test: activate tests for the command LOG

2022-01-17 Thread Patrick DELAUNAY



On 1/12/22 10:29 AM, Marcel Ziswiler wrote:

On Tue, 2022-01-11 at 17:27 +0100, Patrick Delaunay wrote:

This patches activate the command LOG and the associated tests
in sandbox with CONFIG_CMD_LOG=y and solve the associated issues
when these tests are executed.

Patrick


Patrick Delaunay (3):
   dm: fix up documentation for uclass_get_by_name_len
   dm: compare full name in uclass_get_by_name
   sandox: test: activate tests for the command LOG

Probably should read sandbox. Same for this cover-letter's subject ;-p.

oups, yes



  configs/sandbox_defconfig |  2 +-
  drivers/core/uclass.c | 11 ++-
  include/dm/uclass.h   |  4 ++--
  test/py/tests/test_log.py |  8 
  4 files changed, 17 insertions(+), 8 deletions(-)


[PATCH 0/4] pci: Extend 'pci' and 'pci regions' commands

2022-01-17 Thread Pali Rohár
Allow to call 'pci regions' with non-zero bus number and allow to call
'pci' and 'pci regions' commands with bus number '*' which process all
buses. This would be also new default action if no bus is specified.

Pali Rohár (4):
  pci: Fix setting controller's last_busno
  pci: Extend 'pci regions' command with bus number
  pci: Add checks for valid cmdline arguments
  pci: Extend 'pci' command with bus option '*'

 cmd/pci.c| 56 +++-
 drivers/pci/pci-uclass.c |  2 ++
 2 files changed, 46 insertions(+), 12 deletions(-)

-- 
2.20.1



[PATCH 1/4] pci: Fix setting controller's last_busno

2022-01-17 Thread Pali Rohár
Initially it is set to dev_seq but update to the last bus number is
missing. Fix it.

Signed-off-by: Pali Rohár 
---
 drivers/pci/pci-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 8c4d75bdb685..374b22601818 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -562,6 +562,8 @@ int pci_auto_config_devices(struct udevice *bus)
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
}
+   if (hose->last_busno < sub_bus)
+   hose->last_busno = sub_bus;
debug("%s: done\n", __func__);
 
return log_msg_ret("sub", sub_bus);
-- 
2.20.1



[PATCH 3/4] pci: Add checks for valid cmdline arguments

2022-01-17 Thread Pali Rohár
Currently pci command ignores invalid cmdline arguments and do something.
Add checks that all passed arguments were processed.

Signed-off-by: Pali Rohár 
---
 cmd/pci.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/cmd/pci.c b/cmd/pci.c
index 53edf0d90010..8d2c0c4b43dd 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -523,7 +523,12 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
}
if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] 
!= 's')) {
busnum = hextoul(argv[argc - 1], NULL);
+   argc--;
}
+   if (cmd == 'r' && argc > 2)
+   goto usage;
+   else if (cmd != 'r' && (argc > 2 || (argc == 2 && 
argv[1][0] != 's')))
+   goto usage;
}
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
if (ret) {
-- 
2.20.1



[PATCH 2/4] pci: Extend 'pci regions' command with bus number

2022-01-17 Thread Pali Rohár
'pci regions' currently prints only region information from bus 0 which
belongs to controller 0. Parser for 'pci regions' cmdline currently ignores
any additional arguments and so U-Boot always uses bus 0.

Regions are stored in controller (not on the bus) and therefore to retrieve
controller from the bus, it is needed to call pci_get_controller() which
returns root bus. Because bus 0 is root bus, current code worked fine for
controller 0.

Extend cmdline parser for 'pci regions' to allows specifying bus number,
extend pci_show_regions() code to accept also non-zero bus number and
print bus ranges for which is regions configuration assigned.

Signed-off-by: Pali Rohár 
---
 cmd/pci.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/cmd/pci.c b/cmd/pci.c
index 3b1863f139c9..53edf0d90010 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -443,7 +443,7 @@ static const struct pci_flag_info {
 
 static void pci_show_regions(struct udevice *bus)
 {
-   struct pci_controller *hose = dev_get_uclass_priv(bus);
+   struct pci_controller *hose = 
dev_get_uclass_priv(pci_get_controller(bus));
const struct pci_region *reg;
int i, j;
 
@@ -452,6 +452,7 @@ static void pci_show_regions(struct udevice *bus)
return;
}
 
+   printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
printf("#   %-18s %-18s %-18s  %s\n", "Bus start", "Phys start", "Size",
   "Flags");
for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
@@ -520,8 +521,9 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
value = 0;
argc--;
}
-   if (argc > 1)
-   busnum = hextoul(argv[1], NULL);
+   if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] 
!= 's')) {
+   busnum = hextoul(argv[argc - 1], NULL);
+   }
}
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
if (ret) {
@@ -586,7 +588,7 @@ static char pci_help_text[] =
"- show header of PCI device 'bus.device.function'\n"
"pci bar b.d.f\n"
"- show BARs base and size for device b.d.f'\n"
-   "pci regions\n"
+   "pci regions [bus]\n"
"- show PCI regions\n"
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
"- display PCI configuration space (CFG)\n"
-- 
2.20.1



[PATCH 4/4] pci: Extend 'pci' command with bus option '*'

2022-01-17 Thread Pali Rohár
Allow to call 'pci' and 'pci regions' commands with bus option '*' which
cause pci to process all buses.

PCIe is point-to-point HW and so on each bus is maximally one physical
device. Therefore for PCIe it is common to have multiple buses.

This change allows to easily print all available PCIe devices in system.

Make '*' as default option when no bus argument is specified.

Signed-off-by: Pali Rohár 
---
 cmd/pci.c | 45 +++--
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/cmd/pci.c b/cmd/pci.c
index 8d2c0c4b43dd..4415feb2225b 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -256,10 +256,8 @@ static void pci_header_show(struct udevice *dev)
 }
 }
 
-static void pciinfo_header(int busnum, bool short_listing)
+static void pciinfo_header(bool short_listing)
 {
-   printf("Scanning PCI devices on bus %d\n", busnum);
-
if (short_listing) {
printf("BusDevFun  VendorId   DeviceId   Device Class   
Sub-Class\n");

printf("_\n");
@@ -288,11 +286,15 @@ static void pci_header_show_brief(struct udevice *dev)
   pci_class_str(class), subclass);
 }
 
-static void pciinfo(struct udevice *bus, bool short_listing)
+static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
 {
struct udevice *dev;
 
-   pciinfo_header(dev_seq(bus), short_listing);
+   if (!multi)
+   printf("Scanning PCI devices on bus %d\n", dev_seq(bus));
+
+   if (!multi || dev_seq(bus) == 0)
+   pciinfo_header(short_listing);
 
for (device_find_first_child(bus, &dev);
 dev;
@@ -483,10 +485,11 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
ulong addr = 0, value = 0, cmd_size = 0;
enum pci_size_t size = PCI_SIZE_32;
struct udevice *dev, *bus;
-   int busnum = 0;
+   int busnum = -1;
pci_dev_t bdf = 0;
char cmd = 's';
int ret = 0;
+   char *endp;
 
if (argc > 1)
cmd = argv[1][0];
@@ -522,7 +525,11 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
argc--;
}
if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] 
!= 's')) {
-   busnum = hextoul(argv[argc - 1], NULL);
+   if (argv[argc - 1][0] != '*') {
+   busnum = hextoul(argv[argc - 1], &endp);
+   if (*endp)
+   goto usage;
+   }
argc--;
}
if (cmd == 'r' && argc > 2)
@@ -530,6 +537,24 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
else if (cmd != 'r' && (argc > 2 || (argc == 2 && 
argv[1][0] != 's')))
goto usage;
}
+   if (busnum == -1) {
+   if (cmd != 'r') {
+   for (busnum = 0;
+uclass_get_device_by_seq(UCLASS_PCI, 
busnum, &bus) == 0;
+busnum++)
+   pciinfo(bus, value, true);
+   } else {
+   for (busnum = 0;
+uclass_get_device_by_seq(UCLASS_PCI, 
busnum, &bus) == 0;
+busnum++) {
+   /* Regions are controller specific so 
skip non-root buses */
+   if (device_is_on_pci_bus(bus))
+   continue;
+   pci_show_regions(bus);
+   }
+   }
+   return 0;
+   }
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
if (ret) {
printf("No such bus\n");
@@ -538,7 +563,7 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
if (cmd == 'r')
pci_show_regions(bus);
else
-   pciinfo(bus, value);
+   pciinfo(bus, value, false);
return 0;
}
 
@@ -585,7 +610,7 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int 
argc, char *const argv[])
 
 #ifdef CONFIG_SYS_LONGHELP
 static char pci_help_text[] =
-   "[bus] [long]\n"
+   "[bus|*] [long]\n"
"- short or long list of PCI devices on bus 'bus'\n"
"pci enum\n"
"- Enumerate PCI buses\n"
@@ -593,7 +618,7 @@ static char pci_help_text[] =
"- show

[PATCH v2 0/3] sandbox: test: activate tests for the command LOG

2022-01-17 Thread Patrick Delaunay


This patches activate the command LOG and the associated tests
in sandbox with CONFIG_CMD_LOG=y and solve the associated issues
when these tests are executed.

Patrick

Changes in v2:
- update commit message "sandox" => "sandbox"

Patrick Delaunay (3):
  dm: fix up documentation for uclass_get_by_name_len
  dm: compare full name in uclass_get_by_name
  sandbox: test: activate tests for the command LOG

 configs/sandbox_defconfig |  2 +-
 drivers/core/uclass.c | 11 ++-
 include/dm/uclass.h   |  4 ++--
 test/py/tests/test_log.py |  8 
 4 files changed, 17 insertions(+), 8 deletions(-)

-- 
2.25.1



[PATCH v2 1/3] dm: fix up documentation for uclass_get_by_name_len

2022-01-17 Thread Patrick Delaunay
Fix up the comment for uclass_get_by_name_len() to avoid confusion.

Fixes: 4b030177b660 ("dm: core: Allow finding children / uclasses by partial 
name")
Signed-off-by: Patrick Delaunay 
---

(no changes since v1)

 include/dm/uclass.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index f1fd2ba246..a606b6a20b 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -173,10 +173,10 @@ int uclass_get(enum uclass_id key, struct uclass **ucp);
 const char *uclass_get_name(enum uclass_id id);
 
 /**
- * uclass_get_by_name() - Look up a uclass by its driver name
+ * uclass_get_by_name_len() - Look up a uclass by its partial driver name
  *
  * @name: Name to look up
- * @len: Length of name
+ * @len: Length of the partial name
  * @returns the associated uclass ID, or UCLASS_INVALID if not found
  */
 enum uclass_id uclass_get_by_name_len(const char *name, int len);
-- 
2.25.1



[PATCH v2 2/3] dm: compare full name in uclass_get_by_name

2022-01-17 Thread Patrick Delaunay
Change uclass_get_by_name to use a strict string compare function
"strcmp" with the parameter 'name'.

This patch avoids issues when strlen(name)name) as
the function uclass_get_by_name() no more use uclass_get_by_name_len(),
which limit the check with "strncmp" and length of name.

This problem is detected by the sandbox test for log filter:
in log_get_cat_by_name(), uclass_get_by_name("spi") = UCLASS_SPI_EMUL
for "spi_emul", it is not the expected result = UCLASS_SPI
for a search by name.
But it is the expected result for search with partial name
uclass_get_by_name_len("spi", 3).

Signed-off-by: Patrick Delaunay 
---

(no changes since v1)

 drivers/core/uclass.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 336ea8d243..32b6cef167 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -196,7 +196,16 @@ enum uclass_id uclass_get_by_name_len(const char *name, 
int len)
 
 enum uclass_id uclass_get_by_name(const char *name)
 {
-   return uclass_get_by_name_len(name, strlen(name));
+   int i;
+
+   for (i = 0; i < UCLASS_COUNT; i++) {
+   struct uclass_driver *uc_drv = lists_uclass_lookup(i);
+
+   if (uc_drv && !strcmp(uc_drv->name, name))
+   return i;
+   }
+
+   return UCLASS_INVALID;
 }
 
 int dev_get_uclass_index(struct udevice *dev, struct uclass **ucp)
-- 
2.25.1



[PATCH v2 3/3] sandbox: test: activate tests for the command LOG

2022-01-17 Thread Patrick Delaunay
Activate the CONFIG_CMD_LOG in sandbox to execute the LOG tests
by default and correct the test log format after 72fa1ad8d9 ("log: Allow
padding of the function name").

Signed-off-by: Patrick Delaunay 
---

Changes in v2:
- update commit message "sandox" => "sandbox"

 configs/sandbox_defconfig | 2 +-
 test/py/tests/test_log.py | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 4f413582fb..a4aeee062f 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -30,7 +30,6 @@ 
CONFIG_AUTOBOOT_STOP_STR_CRYPT="$5$rounds=64$HrpE65IkB8CM5nCL$BKT3QdF98Bo8fJ
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_F=y
 CONFIG_STACKPROTECTOR=y
@@ -108,6 +107,7 @@ CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
 CONFIG_CMD_STACKPROTECTOR_TEST=y
 CONFIG_MAC_PARTITION=y
 CONFIG_AMIGA_PARTITION=y
diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py
index 140dcb9aa2..20a3e56301 100644
--- a/test/py/tests/test_log.py
+++ b/test/py/tests/test_log.py
@@ -27,13 +27,13 @@ def test_log_format(u_boot_console):
 
 cons = u_boot_console
 with cons.log.section('format'):
-run_with_format('all', 'NOTICE.arch,file.c:123-func() msg')
+run_with_format('all', 'NOTICE.arch,file.c:123-func() 
msg')
 output = cons.run_command('log format')
 assert output == 'Log format: clFLfm'
 
-run_with_format('fm', 'func() msg')
-run_with_format('clfm', 'NOTICE.arch,func() msg')
-run_with_format('FLfm', 'file.c:123-func() msg')
+run_with_format('fm', 'func() msg')
+run_with_format('clfm', 'NOTICE.arch,func() msg')
+run_with_format('FLfm', 'file.c:123-func() msg')
 run_with_format('lm', 'NOTICE. msg')
 run_with_format('m', 'msg')
 
-- 
2.25.1



Re: [PATCH] gpio: mxc_gpio: Fix i.MX8M GPIO output status read

2022-01-17 Thread Harm Berntsen
Hi Fabio Estevam and Ye Li,

On Sat, 2022-01-15 at 10:43 -0300, Fabio Estevam wrote:
> Hi Harm and Ye Li,
> 
> On Fri, Aug 13, 2021 at 11:35 AM Harm Berntsen
>  wrote:
> > 
> > Currently the driver gets value from PSR register, but this
> > register is
> > only for input mode. For output mode, it always returns 0, not the
> > value
> > we set for output.
> > 
> > This patch changes to use DR register, which returns the DR value
> > for
> > output mode, and PSR value for input mode.
> > 
> > This patch is based on code from Ye Li 
> 
> Could this issue be fixed by setting the SION bit mode?

SION works! I did not know about it :). I see the imxrt1020-evk,
imxrt1050-evk and imx53-kp use it in their device tree. To make this
feature available, I had to ensure the IMX_PAD_SION was available in my
dts by adding a define:

#define IMX_PAD_SION   0x4000

I could then configure the pinmux in my dts file. It would be nice to
make this define available by default.

To conclude, I would now need to enable SION in order to remove the
'Warning: value of pin is still 0' text in my serial output. I'm fine
with that.


[PATCH v2 00/16] passage: Define a standard for firmware data flow

2022-01-17 Thread Simon Glass


This series adds a standard way of passing information between different
firmware phases. This already exists in U-Boot at a very basic level, in
the form of a bloblist containing an spl_handoff structure, but the intent
here is to define something useful across projects.

The need for this is growing as firmware fragments into multiple binaries
each with its own purpose. Without any run-time connection, we must rely
on build-time settings which are brittle and painful to keep in sync.

This feature is named 'standard passage' since the name is more unique
than many others that could be chosen, it is a passage in the sense that
information is flowing from one place to another and it is standard,
because that is what we want to create.

The implementation is simply a pointer to a bloblist in a register, with
an extra register to point to a devicetree, for more complex data. This
should cover all cases (small memory footprint as well as complex data
flow) and be easy enough to implement on all architectures.

The emphasis is on enabling open communcation between binaries, not
enabling passage of secret, undocumented data, although this is possible
in a private environment.

This series is available at u-boot-dm/pass-working

Changes in v2:
- Add a devicetree for qemu-arm so that qemu_arm_spl can work
- Add comments about how to pass standard passage to EFI
- Add comments about passing a bloblist to Linux
- Add detailed arch-specific information
- Add new patch with the arm-specific standard passage implementation
- Incorporate devicetree source
- Make the stdpass calling standard arch-specific
- Rebase to master
- Rebase to master (dropping bloblist patches already applied)
- Rework global_data for new stdpass convention
- Split the jump_to_image_no_args() change into its own patch
- Use three registers instead of two for the entry

Simon Glass (16):
  spl: Tidy up the header includes
  arm: qemu: Add an SPL build
  spl: Rename jump_to_image_no_args()
  passage: Support an incoming passage
  passage: Support a control devicetree
  passage: arm: Accept a passage from the previous phase
  passage: spl: Support adding the dtb to the passage bloblist
  passage: spl: Support passing the passage to U-Boot
  passage: arm: Add the arch-specific standard passage impl
  passage: Add a qemu test for ARM
  sandbox: Add a way of checking structs for standard passage
  passage: Add documentation
  passage: Add docs for spl_handoff
  x86: Move Intel GNVS file into the common include directory
  passage: Add checks for pre-existing blobs
  WIP: RFC: Add a gitlab test

 .gitlab-ci.yml|   6 +
 MAINTAINERS   |  10 +
 arch/arm/Kconfig  |   2 +-
 arch/arm/cpu/armv7/cpu.c  |  28 ++
 arch/arm/cpu/armv7/start.S|   7 +-
 arch/arm/cpu/armv8/cpu.c  |  20 +
 arch/arm/dts/qemu-arm-u-boot.dtsi |  22 +
 arch/arm/dts/qemu-arm.dts | 393 -
 arch/arm/lib/crt0.S   |   5 +
 arch/arm/mach-imx/imx8ulp/soc.c   |   2 +-
 arch/arm/mach-imx/spl.c   |   2 +-
 arch/arm/mach-k3/common.c |   2 +-
 arch/arm/mach-omap2/boot-common.c |   2 +-
 arch/arm/mach-qemu/Kconfig|   9 +
 arch/arm/mach-tegra/spl.c |   2 +-
 arch/mips/lib/spl.c   |   2 +-
 arch/riscv/lib/spl.c  |   2 +-
 arch/sandbox/cpu/spl.c|   4 +-
 arch/x86/cpu/apollolake/acpi.c|   2 +-
 arch/x86/cpu/intel_common/acpi.c  |   2 +-
 .../include/asm/arch-apollolake/global_nvs.h  |   2 +-
 arch/x86/lib/spl.c|   2 +-
 arch/x86/lib/tpl.c|   2 +-
 board/emulation/qemu-arm/Kconfig  |  23 +-
 board/emulation/qemu-arm/MAINTAINERS  |   1 +
 board/emulation/qemu-arm/Makefile |   1 +
 board/emulation/qemu-arm/spl.c|  27 ++
 board/freescale/common/fsl_chain_of_trust.c   |   2 +-
 board/google/chromebook_coral/coral.c |   2 +-
 board/renesas/rcar-common/gen3-spl.c  |   2 +-
 board/sandbox/Makefile|   3 +-
 board/sandbox/stdpass_check.c | 107 +
 common/Kconfig|  51 +++
 common/bloblist.c |   8 +-
 common/board_f.c  |  48 ++-
 common/spl/spl.c  |  95 -
 configs/qemu_arm_spl_defconfig|  78 
 doc/board/emulation/qemu-arm.rst  |  37 ++
 doc/develop/bloblist.rst  |   4 +-
 doc/develop/index.rst |   1 +
 doc/develop/std_passage.rst   | 396 ++
 drivers/usb/gadget/f_sdp.c|   2 +-
 dts/Kconfig

RE: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision

2022-01-17 Thread Moti Buskila
Hi Marek
This mail was send by accident.
Assaf H, is taking care of that.
Thanks



-Original Message-
From: Marek Behún  
Sent: Monday, January 17, 2022 4:23 PM
To: Moti Buskila 
Cc: Stefan Roese ; Mario Six ; Dennis Gilmore 
; Kostya Porotchkin ; Pali Rohár 
; u-boot@lists.denx.de; Marek Behún 
Subject: Re: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix SPLIT_OUT_MIX 
state decision

Hello Moti,

since you're the author of the original version of this patch, could you please 
review it and if it is okay, put it into mv-ddr-marvell?

Thanks.

Marek

On Mon, 17 Jan 2022 06:52:08 +
Moti Buskila  wrote:

> Hi Assaf,
> I've got this email a few days ago.
> Is it related to what you’ve send me? 
> Thanks
> 
> 
> -Original Message-
> From: Marek Behún 
> Sent: Wednesday, January 12, 2022 6:07 PM
> To: Stefan Roese ; Mario Six ; Dennis 
> Gilmore ; Kostya Porotchkin 
> Cc: Pali Rohár ; u-boot@lists.denx.de; Moti Buskila 
> ; Marek Behún 
> Subject: [EXT] [PATCH u-boot-marvell] ddr: marvell: a38x: fix 
> SPLIT_OUT_MIX state decision
> 
> External Email
> 
> --
> From: Marek Behún 
> 
> This is a cleaned up and fixed version of a patch
>   mv_ddr: a380: fix SPLIT_OUT_MIX state decision
> 
>   in each pattern cycle the bus state can be changed
>   in order to avoide it, need to back to the same bus state on each
>   pattern cycle
> by
>   Moti Boskula 
> 
> The original patch is not in Marvell's mv-ddr-marvell repository. It 
> was gives to us by Marvell to fix an issues with DDR training on some 
> boards, but it cannot be applied as is to mv-ddr-marvell, because it 
> is a very dirty draft patch that would certainly break other things, 
> mainly
> DDR4 training code in mv-ddr-marvell, since it changes common functions.
> 
> I have cleaned up the patch and removed stuff that seemed unnecessary (when 
> removed, it still fixed things). Note that I don't understand completely what 
> the code does exactly, since I haven't studied the DDR training code 
> extensively (and I suspect that no one besides some few people in Marvell 
> understand the code completely).
> 
> Anyway after the cleanup the patch still fixes isssues with DDR training on 
> the failing boards.
> 
> There was also a problem with the original patch on some of the Allied 
> Telesis' x530 boards, reported by Chris Packham. I have asked Chris to send 
> me some logs, and managed to fix it:
> - if you look at the change, you'll notice that it introduces
>   subtraction of cur_start_win[] and cur_end_win[] members, depending on
>   a bit set in the current_byte_status variable
> - the original patch subtracted cur_start_win[] if either
>   BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
>   subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
>   was set
> - from Chris Packham logs I discovered that the x530 board where the
>   original patch introduced DDR training failure, only the
>   BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
>   patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
>   current_byte_status variable
> - this led me to the hypothesis that both cur_start_win[] and
>   cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
>   set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at 
> all
> - this hypothesis also gains credibility when considering the commit
>   title ("fix SPLIT_OUT_MIX state decision")
> 
> Hopefully this will fix things without breaking anything else.
> 
> Signed-off-by: Marek Behún 
> ---
>  .../a38x/ddr3_training_centralization.c   | 26 +++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c 
> b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> index 648b37ef6f..42308b6965 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
> @@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
>   enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
>   u32 if_id, pattern_id, bit_id;
>   u8 bus_id;
> + u8 current_byte_status;
>   u8 cur_start_win[BUS_WIDTH_IN_BITS];
>   u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
>   u8 cur_end_win[BUS_WIDTH_IN_BITS];
> @@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
> result[search_dir_id][7]));
>   }
>  
> + current_byte_status =
> + 
> mv_ddr_tip_sub_phy_byte_status_get(if_id,
> +
> bus_id);
> +
>   for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
>bit_id++) {
>  

Re: [PATCH 1/9] doc: add include/dm/uclass.h to the HTML documentation

2022-01-17 Thread Patrick DELAUNAY

Hi Heinrich,

On 1/15/22 9:24 AM, Heinrich Schuchardt wrote:

On 1/12/22 10:53, Patrick Delaunay wrote:

Correct Sphinx style comments in include/dm/uclass.h
and add the driver model UCLASS API to the HTML documentation.

Signed-off-by: Patrick Delaunay 
---

  doc/api/dm.rst  |  9 ++
  doc/api/index.rst   |  1 +
  include/dm/uclass.h | 75 ++---
  3 files changed, 47 insertions(+), 38 deletions(-)
  create mode 100644 doc/api/dm.rst

diff --git a/doc/api/dm.rst b/doc/api/dm.rst
new file mode 100644
index 00..edce25da51
--- /dev/null
+++ b/doc/api/dm.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Driver Model
+
+
+Uclass and Driver
+-
+
+.. kernel-doc:: include/dm/uclass.h
diff --git a/doc/api/index.rst b/doc/api/index.rst
index 806c7385a6..3f36174167 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -7,6 +7,7 @@ U-Boot API documentation
 :maxdepth: 2

 dfu
+   dm
 efi
 getopt
 linker_lists
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index f1fd2ba246..a12a872d94 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -84,7 +84,7 @@ struct udevice;
   * its children. If non-zero this is the size of this data, to be 
allocated
   * in the child device's parent_plat pointer. This value is only 
used as

   * a fallback if this member is 0 in the driver.
- * @flags: Flags for this uclass (DM_UC_...)
+ * @flags: Flags for this uclass ``(DM_UC_...)``
   */
  struct uclass_driver {
  const char *name;
@@ -127,17 +127,16 @@ struct uclass_driver {
   * build time. Before this is used, an extern UCLASS_DRIVER() must 
have been

   * declared.
   *
- * For example:
+ * For example: ::


Nits:
"For example::" has the same effect. I will change this when merging.


ok.

https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#literal-blocks

I miss the 'Fully minimized form:' or when I test the html output

I let a space before the Literal Blocks => "Paragraph ::"

FYI: I do the same issue in several location I think.



Reviewed-by: Heinrich Schuchardt 





Patrick



Re: Please pull u-boot-net/next

2022-01-17 Thread Tom Rini
On Sat, Jan 15, 2022 at 10:01:42PM +0200, Ramon Fried wrote:

> Hi Tom,
> Please pull the latest changes from u-boot-net/next branch which include:
> * PXE label override support
> * Fastboot UDP configurable port
> * new phy driver: TI DP83869HM
> * and few minor fixes to dsa.
> 
> The following changes since commit 0dadad6d7c5769d6258baeaf1b8db843b0dfa01f:
> 
>   Merge tag 'u-boot-amlogic-20220107' of
> https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
> (2022-01-09 07:56:31 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-net.git/
> 
> for you to fetch changes up to 046bf8d4c512ad6501fe9e77508bbe1292a29fef:
> 
>   net: fastboot: make UDP port net: configurable (2022-01-15 18:54:21 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [GIT PULL] Please pull u-boot-pmic master

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 08:20:36AM +0900, Jaehoon Chung wrote:

> Dear Tom,
> 
> Please pull u-boot-pmic master into u-boot master branch.
> If there is a problem, let me know, plz
> 
> Best Regards,
> Jaehoon Chung
> 
> CI: https://source.denx.de/u-boot/custodians/u-boot-pmic/-/pipelines/10653
> 
> The following changes since commit d71dbe657c3c22f50ecb3df133e5cdd884daae7d:
> 
>   Merge tag 'efi-2022-04-rc1' of 
> https://source.denx.de/u-boot/custodians/u-boot-efi (2022-01-15 07:39:09 
> -0500)
> 
> are available in the Git repository at:
> 
>   g...@source.denx.de:u-boot/custodians/u-boot-pmic.git master
> 
> for you to fetch changes up to 97187d5e375cd56f96e6ddca44d2790986899dca:
> 
>   power: domain: Add Apple pmgr driver (2022-01-17 06:56:01 +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PULL] u-boot-at91-2022.04-b

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 12:09:06PM +, eugen.hris...@microchip.com wrote:

> Hello Tom,
> 
> Please pull tag u-boot-at91-2022.04-b , the second set of at91 features
> for the next cycle 2022.04 .
> 
> This small feature set includes few changes for sama7g5 and sama7g5ek: 
> turn blue led on at boot, changes required for the Rev4 of the board, 
> better sync with the Linux DT with regards to the new DT nodes.
> 
> Thanks,
> Eugen
> 
> The following changes since commit a02af84e03e018d7cd08bb3070cbe5517004712b:
> 
>Merge branch '2022-01-12-pci-updates' (2022-01-12 20:49:39 -0500)
> 
> are available in the Git repository at:
> 
>https://source.denx.de/u-boot/custodians/u-boot-at91.git 
> tags/u-boot-at91-2022.04-b
> 
> for you to fetch changes up to dbf500b55770e58313df9fefa217129da38ea1b6:
> 
>configs: at91: sama7g5ek: enable CONFIG_PHANDLE_CHECK_SEQ (2022-01-17 
> 11:18:39 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 1/2] lmb: Fix lmb property's defination under struct lmb

2022-01-17 Thread Patrick DELAUNAY

Hi,

On 1/14/22 1:14 PM, Michal Simek wrote:

From: Ashok Reddy Soma 

Under struct lmb {} the lmb property's should be defined only if
CONFIG_LMB_MEMORY_REGIONS is defined.

Signed-off-by: Ashok Reddy Soma 
Signed-off-by: Michal Simek 
---

  include/lmb.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/lmb.h b/include/lmb.h
index ab277ca80004..1476d78c2823 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -68,7 +68,7 @@ struct lmb_region {
  struct lmb {
struct lmb_region memory;
struct lmb_region reserved;
-#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
+#if IS_ENABLED(CONFIG_LMB_MEMORY_REGIONS)
struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
  #endif



I think this patch don't change the exiting code

because in lib/Kconfig we have also the dependancy with LMB_USE_MAX_REGIONS:

  config LMB_MEMORY_REGIONS
      int "Number of memory regions in lmb lib"
      depends on LMB && !LMB_USE_MAX_REGIONS

=> memory_regions and reserved_regions are needed in struc lmb
   only if CONFIG_LMB_USE_MAX_REGIONS is not defined
   else it is defined in "struct lmb_region" under the SAME compilation flag


struct lmb_region {
unsigned long cnt;
unsigned long max;
#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
struct lmb_property region[CONFIG_LMB_MAX_REGIONS];
#else
struct lmb_property *region;
#endif
};

with .region = pointer to 'memory_regions[]' or 'reserved_regions[]' in "struct 
lmb"

I think it is more clear to have the compilation flag in "struct 
lmb_region" and in "struct lmb_region".


but I have no objection to change it.


PS: I introduce this flag to keep the previous behavior and previous 
struct size on other platform


  when I push the commit 6d66502bc741 ("lmb: Add 2 config to define 
the max number of regions")


Regards

Patrick




Re: [PATCH v2 12/16] passage: Add documentation

2022-01-17 Thread Mark Kettenis
> From: Simon Glass 
> Date: Mon, 17 Jan 2022 08:04:24 -0700
> 
> Add documentation about standard passage and update the maintainers.
> 
> Signed-off-by: Simon Glass 
> ---
> 
> Changes in v2:
> - Add comments about how to pass standard passage to EFI
> - Add comments about passing a bloblist to Linux
> - Add detailed arch-specific information
> 
>  MAINTAINERS   |  10 +
>  board/sandbox/stdpass_check.c |  10 +-
>  doc/develop/bloblist.rst  |   4 +-
>  doc/develop/index.rst |   1 +
>  doc/develop/std_passage.rst   | 396 ++
>  5 files changed, 411 insertions(+), 10 deletions(-)
>  create mode 100644 doc/develop/std_passage.rst
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 38c68ee87d4..63723d43b63 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1177,6 +1177,16 @@ F: common/stackprot.c
>  F:   cmd/stackprot_test.c
>  F:   test/py/tests/test_stackprotector.py
>  
> +STANDARD PASSAGE
> +M:   Simon Glass 
> +F:   board/sandbox/stdpass_check.c
> +F:   cmd/bloblist.c
> +F:   common/bloblist.c
> +F:   doc/develop/std_passage.rst
> +F:   include/bloblist.h
> +F:   include/stdpass/
> +F:   test/bloblist.c
> +
>  TARGET_BCMNS3
>  M:   Bharat Gooty 
>  M:   Rayagonda Kokatanur 
> diff --git a/board/sandbox/stdpass_check.c b/board/sandbox/stdpass_check.c
> index 565124e1564..8391c7a4aed 100644
> --- a/board/sandbox/stdpass_check.c
> +++ b/board/sandbox/stdpass_check.c
> @@ -8,13 +8,6 @@
>  
>  #include 
>  
> -/* BLOBLISTT_U_BOOT_SPL_HANDOFF */
> -#include 
> -void check_spl_handoff(void)
> -{
> - __maybe_unused struct spl_handoff check;
> -};
> -
>  /*
>   * See also doc/develop/std_passage.rst
>   *
> @@ -23,7 +16,8 @@ void check_spl_handoff(void)
>   * 1. Add your header file to U-Boot, or to include/stdpass if it is not 
> used in
>   * U-Boot
>   *
> - * 2. Add a function below to include the header and use the struct
> + * 2. Add a function below to include the header and use the struct. Please 
> put
> + * your function in order of tag ID (see bloblist.h)
>   *
>   * Template follows, see above for example
>   */
> diff --git a/doc/develop/bloblist.rst b/doc/develop/bloblist.rst
> index 572aa65d764..e819c6dc76b 100644
> --- a/doc/develop/bloblist.rst
> +++ b/doc/develop/bloblist.rst
> @@ -1,7 +1,7 @@
>  .. SPDX-License-Identifier: GPL-2.0+
>  
> -Blob Lists - bloblist
> -=
> +Bloblist
> +
>  
>  Introduction
>  
> diff --git a/doc/develop/index.rst b/doc/develop/index.rst
> index 9592d193fca..d0aecc30059 100644
> --- a/doc/develop/index.rst
> +++ b/doc/develop/index.rst
> @@ -21,6 +21,7 @@ Implementation
> logging
> makefiles
> menus
> +   std_passage
> uefi/index
> version
>  
> diff --git a/doc/develop/std_passage.rst b/doc/develop/std_passage.rst
> new file mode 100644
> index 000..461098e01e7
> --- /dev/null
> +++ b/doc/develop/std_passage.rst
> @@ -0,0 +1,396 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Standard Passage
> +
> +
> +Introduction
> +
> +
> +It is sometimes necessary for SPL to communicate information to U-Boot 
> proper,
> +such as the RAM size. This can sometimes be handled by adding the value to a
> +Kconfig which both SPL and U-Boot proper can use. But this does not work for
> +values which are detected at runtime.
> +
> +In some cases other firmware binaries are used alongside U-Boot and these may
> +need to pass information to U-Boot or receive information from it. In this 
> case
> +there is no shared build system and it is clumsy so have to specify matching
> +build options across projects.
> +
> +U-Boot provides a standard way of passing information between different 
> phases
> +(TPL, SPL, U-Boot). This is called `standard passage` since it creates a
> +standard passage through which any sort of information can flow.
> +
> +
> +How it works
> +
> +
> +The standard passage is very simple. It is really just a way of sending a
> +bloblist between programs, either at a fixed address, or using registers to
> +indicate the location.
> +
> +A :doc:`bloblist` is a simple, contiguous data structure containing a number 
> of
> +blobs. Each blob has a tag to indicate what it contains. It is designed for
> +simple information, like a small C struct. For more complex data, a 
> devicetree
> +is preferred since it has bindings and is extensible.
> +
> +The bloblist is typically set up initially by one of the early phases of 
> U-Boot,
> +such as TPL. It starts either at a fixed address or is allocated in memory 
> using
> +malloc(). After that, TPL passes the location of the bloblist to SPL (using
> +machine register in an architecture-specific way) and SPL passes it to U-Boot
> +proper. It is possible to add new blobs to the bloblist at each phase. U-Boot
> +proper relocates the bloblist so can expand it if desired.
> +
> +
> +Use by other projects
> +-
> +
> +The standard passage is also 

Re: [PATCH] gpio: mxc_gpio: Fix i.MX8M GPIO output status read

2022-01-17 Thread Fabio Estevam
Hi Harm,

Adding Angus, who submitted a similar patch:
https://patchwork.ozlabs.org/project/uboot/patch/20211128145143.1433262-1-an...@akkea.ca/

On Mon, Jan 17, 2022 at 12:55 PM Harm Berntsen  wrote:

> > Could this issue be fixed by setting the SION bit mode?
>
> SION works! I did not know about it :). I see the imxrt1020-evk,

Ok, great!

> imxrt1050-evk and imx53-kp use it in their device tree. To make this
> feature available, I had to ensure the IMX_PAD_SION was available in my
> dts by adding a define:
>
> #define IMX_PAD_SION   0x4000
>
> I could then configure the pinmux in my dts file. It would be nice to
> make this define available by default.
>
> To conclude, I would now need to enable SION in order to remove the
> 'Warning: value of pin is still 0' text in my serial output. I'm fine
> with that.

Actually, there are several i.MX dts files that set bit 30 (SION bit):

For example, the I2C pins in imx8mq-evk.dts look like this:

MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x407f

Does it work if you just set bit 30 in your device tree? Which SoC are
you using?


Re: [PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 07:07:22AM -0800, Angus Ainslie wrote:

> I sent this patchset as a single monolithic patch and did not see any 
> comment on it. 
> 
> https://lists.denx.de/pipermail/u-boot/2022-January/471087.html
> 
> Here it is as a set of patches instead.
> 
> This is all of the code required to boot the Librem5 Phone.
> 
> It can boot the phone in uuu mode or directly from the eMMC

Yes, sorry, we're a little behind on imx-related patches right now.  In
general yes, splitting this up a bit helps, but it's too split now.
I'll reply with some specific questions / comments, but the way it was
before is better really.

-- 
Tom


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Re: [PATCH 01/13] MAINTAINERS: add Purism to the maintainers file

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 07:07:23AM -0800, Angus Ainslie wrote:

> The Purism kernel team is in charge of maintianing the Librem5 u-boot
> 
> Signed-off-by: Angus Ainslie 
> ---
>  MAINTAINERS | 9 +
>  1 file changed, 9 insertions(+)

In U-Boot this is done all within board/.../MAINTAINERS instead of the
top-level file, thanks!

-- 
Tom


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Re: [PATCH 02/13] arm: dts: add the Purism devicetree files

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:

> Initial commit of Librem5 devicetree files
> 
> Signed-off-by: Angus Ainslie 

Please note what kernel release the not -u-boot.dtsi files are a copy
from, as they need to be copies and not modified, thanks.

-- 
Tom


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Re: [PATCH 05/13] include: configs: add the librem5.h include file

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 07:07:27AM -0800, Angus Ainslie wrote:

> Initial commit of the librem5.h configuration
> 
> Signed-off-by: Angus Ainslie 

You'll want to use CI
(https://u-boot.readthedocs.io/en/latest/develop/ci_testing.html) to get
this tested for migrated symbols, or copy the CI logic out to a script
and do that manually as I suspect there's some symbols here that need to
be in the defconfig.  Also:

> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_THERM_SUPPORT
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_LDSCRIPT  "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK 0x187FF0
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_BSS_START_ADDR  0x0018
> +#define CONFIG_SPL_BSS_MAX_SIZE0x2000/* 8 KB */
> +#define CONFIG_SPL_STACK_R_ADDR  0x4230
> +#define CONFIG_SPL_STACK_R
> +#define CONFIG_SYS_SPL_MALLOC_START0x4220
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8   /* 512 KB */
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before 
> GD_FLG_FULL_MALLOC_INIT */
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info 
> not panic */
> +
> +#undef CONFIG_SPL_DM_PMIC
> +#undef CONFIG_SPL_DM_I2C
> +#undef CONFIG_SPL_DM_PMIC_BD71837
> +#undef CONFIG_DM_USB
> +#undef CONFIG_SPL_DM_USB
> +#undef CONFIG_USB_DWC3_GENERIC
> +#undef CONFIG_DEVRES
> +
> +#define CONFIG_SYS_I2C
> +
> +#define CONFIG_POWER_BD71837
> +#define CONFIG_POWER_BD71837_I2C_BUS 0
> +#define CONFIG_POWER_BD71837_I2C_ADDR0x4B
> +
> +#define CONFIG_SPL_DMA_SUPPORT
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +
> +#else /* CONFIG_SPL_BUILD*/
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
> +
> +#define CONFIG_USBD_HS
> +
> +#define CONFIG_USB_GADGET_VBUS_DRAW 2
> +
> +#endif /* CONFIG_SPL_BUILD*/

You can't use CONFIG_SPL_BUILD in this way.  Symbols need to always be
set (and yes, this likely came from some other bad example).

[snip]
> + "bootargs=u_boot_version=" PLAIN_VERSION "\0" \

Why do you need this?  It might be a problem for reproducible builds,
and also you should just be able to use ${version} from the environment?
Thanks.

-- 
Tom


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Re: [PATCH 13/13] doc: librem5: add Librem5 documentation

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 07:07:35AM -0800, Angus Ainslie wrote:

> Initial commit of the Librem5 documentation
> 
> Signed-off-by: Angus Ainslie 
> ---
>  doc/board/purism/librem5/librem5.rst | 60 
>  1 file changed, 60 insertions(+)
>  create mode 100644 doc/board/purism/librem5/librem5.rst

If you don't also update the index files, this won't be included, or
will give an error?  Also, I suspect there's some problems about
headings and so forth, please make sure "make htmldocs" is happy.

-- 
Tom


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Re: imx8mm-evk does not boot kernel 5.16

2022-01-17 Thread Tim Harvey
On Fri, Jan 14, 2022 at 11:44 AM Fabio Estevam  wrote:
>
> Hi Marcel,
>
> On Fri, Jan 14, 2022 at 3:10 PM Marcel Ziswiler
>  wrote:
>
> > Strange, remember, I am working on Verdin iMX8M Mini support [1] and run 
> > that stuff more or less daily.
> > However, as you can see in that patch series, I build the imx-sdma driver 
> > now as a module just like already
> > merged for imx_v6_v7_defconfig. As I also do have an imx8mm-evk laying 
> > around somewhere I can give that a try
> > as well. I keep you posted...
>
> Just noticed that when using the TF-A from NXP: imx-atf branch:
> imx_5.4.47_2.2.0 the 5.16 kernel boots fine.
>
> When using the mainline TF-A  (v2.5 or v2.6) the board hangs with 5.16
>

Interesting. Can you give us a breakdown of pros and cons of using
mainline TF-A vs NXP's? I'm not clear if NXP has been actively pushing
their changes up or not and haven't had time to follow the commits for
either project.

Best regards,

Tim


Re: [PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Angus Ainslie

Hi Toni

On 2022-01-17 08:59, Tom Rini wrote:

On Mon, Jan 17, 2022 at 07:07:22AM -0800, Angus Ainslie wrote:


I sent this patchset as a single monolithic patch and did not see any
comment on it.

https://lists.denx.de/pipermail/u-boot/2022-January/471087.html

Here it is as a set of patches instead.

This is all of the code required to boot the Librem5 Phone.

It can boot the phone in uuu mode or directly from the eMMC


Yes, sorry, we're a little behind on imx-related patches right now.  In
general yes, splitting this up a bit helps, but it's too split now.
I'll reply with some specific questions / comments, but the way it was
before is better really.


Thanks for the review and I'll start making changes for v2.

About how it should be split up. Should all of the 
"board/purism/librem5" and config files be in one patch with the 
devicetree and documentation in separate patches ?


Thanks
Angus


Re: [PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Angus Ainslie

On 2022-01-17 09:14, Angus Ainslie wrote:

Hi Toni



Sorry Tom, somehow concatenated your 2 names.


Re: imx8mm-evk does not boot kernel 5.16

2022-01-17 Thread Fabio Estevam
Hi Tim,

On Mon, Jan 17, 2022 at 2:09 PM Tim Harvey  wrote:

> Interesting. Can you give us a breakdown of pros and cons of using
> mainline TF-A vs NXP's? I'm not clear if NXP has been actively pushing
> their changes up or not and haven't had time to follow the commits for
> either project.

I am not following TF-A i.MX development in upstream, so I cannot
comment myself.

Added Jacky on Cc, who is involved with i.MX TF-A development and
could probably explain.


Re: [PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 09:14:05AM -0800, Angus Ainslie wrote:
> Hi Toni
> 
> On 2022-01-17 08:59, Tom Rini wrote:
> > On Mon, Jan 17, 2022 at 07:07:22AM -0800, Angus Ainslie wrote:
> > 
> > > I sent this patchset as a single monolithic patch and did not see any
> > > comment on it.
> > > 
> > > https://lists.denx.de/pipermail/u-boot/2022-January/471087.html
> > > 
> > > Here it is as a set of patches instead.
> > > 
> > > This is all of the code required to boot the Librem5 Phone.
> > > 
> > > It can boot the phone in uuu mode or directly from the eMMC
> > 
> > Yes, sorry, we're a little behind on imx-related patches right now.  In
> > general yes, splitting this up a bit helps, but it's too split now.
> > I'll reply with some specific questions / comments, but the way it was
> > before is better really.
> 
> Thanks for the review and I'll start making changes for v2.
> 
> About how it should be split up. Should all of the "board/purism/librem5"
> and config files be in one patch with the devicetree and documentation in
> separate patches ?

Since you've already split out driver/etc changes to other patches, one
patch with board/ and include/configs/ and configs/ and dts files is
fine.

-- 
Tom


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Re: [PATCH 00/13] Add support for the Purism Librem5 Phone

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 09:15:12AM -0800, Angus Ainslie wrote:
> On 2022-01-17 09:14, Angus Ainslie wrote:
> > Hi Toni
> > 
> 
> Sorry Tom, somehow concatenated your 2 names.

No worries.

-- 
Tom


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Re: [PATCH 02/13] arm: dts: add the Purism devicetree files

2022-01-17 Thread Angus Ainslie

Hi Tom,

On 2022-01-17 08:59, Tom Rini wrote:

On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:


Initial commit of Librem5 devicetree files

Signed-off-by: Angus Ainslie 


Please note what kernel release the not -u-boot.dtsi files are a copy
from, as they need to be copies and not modified, thanks.


There's an issue with adding the devicetree from the 5.16 kernel.

I get a compilation error due to a :missing .h in the devicetree files:

In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11,
 from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6:
arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error: 
dt-bindings/rfkill/rfkill.h: No such file or directory

   13 | #include "dt-bindings/rfkill/rfkill.h"
  |  ^

Should that get added to the u-boot source as well or should I modify 
the dts to remove this ?


For the kernel we also have 4 different dts files for the differences in 
PCB versions. For u-boot we don't need the differentiation as it deals 
with things like camera rotation and prox sensor sensitivity.


There's 2 ways to solve the this I think.

1) just use the latest librem5 dts file which is made up of 3 different 
dts(i) files.

2) have a defconfig for each of the different PCB versions.

Do you have a preference ?

Thanks
Angus


Re: [PATCH V3] sf: Querying write-protect status before operating the flash

2022-01-17 Thread Tom Rini
On Thu, Jan 13, 2022 at 08:38:04AM +0100, Jan Kiszka wrote:
> On 17.11.21 12:59, Tom Rini wrote:
> > On Wed, Nov 17, 2021 at 01:43:28PM +0530, Jagan Teki wrote:
> > > On Wed, Nov 17, 2021 at 1:33 PM Michael Walle  wrote:
> > > > 
> > > > Hi,
> > > > 
> > > > Am 2021-11-17 03:48, schrieb chaochao2021...@163.com:
> > > > > From: chao zeng 
> > > > > 
> > > > > When operating the write-protection flash,spi_flash_std_write() and
> > > > > spi_flash_std_erase() would return wrong result.The flash is 
> > > > > protected,
> > > > > but write or erase the flash would show "OK".
> > > > > 
> > > > > Check the flash write protection state before operating the flash
> > > > > and give a prompt to show it has been locked if the write-protection
> > > > > has enbale
> > > > > 
> > > > > Signed-off-by: chao zeng 
> > > > > 
> > > > > ---
> > > > > 
> > > > > Changes for V2:
> > > > >   - Return 0 not ENOPROTOOPT to refelect the flash feature
> > > > >   - Output prompt information
> > > > > Changes for V3:
> > > > >   - Modify output information
> > > > >   - Delete return statement
> > > > > ---
> > > > >   drivers/mtd/spi/sf_probe.c | 6 ++
> > > > >   1 file changed, 6 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> > > > > index f461082e03..f9e879aec5 100644
> > > > > --- a/drivers/mtd/spi/sf_probe.c
> > > > > +++ b/drivers/mtd/spi/sf_probe.c
> > > > > @@ -109,6 +109,9 @@ static int spi_flash_std_write(struct udevice
> > > > > *dev, u32 offset, size_t len,
> > > > >struct mtd_info *mtd = &flash->mtd;
> > > > >size_t retlen;
> > > > > 
> > > > > + if (flash->flash_is_locked && flash->flash_is_locked(flash, 
> > > > > offset,
> > > > > len))
> > > > > + printf("SF: Operate on the protected area.Writes will be
> > > > > ignored\n");
> > > > 
> > > > I don't think this is the correct place for this output. This could
> > > > also be called from a board file programmatically and then it might
> > > > display this error, which is annoying.
> > > > 
> > > > Also, this is issuing an additional command "read SR" for every write.
> > > > 
> > > > What is your intention here? To make the user aware that he is going
> > > > to write to a write-protected region when he is using the "sf" command?
> > > > If that is the case, this should be added to that command instead.
> > > > 
> > > > > +
> > > > >return mtd->_write(mtd, offset, len, &retlen, buf);
> > > > >   }
> > > > > 
> > > > > @@ -127,6 +130,9 @@ static int spi_flash_std_erase(struct udevice
> > > > > *dev, u32 offset, size_t len)
> > > > >instr.addr = offset;
> > > > >instr.len = len;
> > > > > 
> > > > > + if (flash->flash_is_locked && flash->flash_is_locked(flash, 
> > > > > offset,
> > > > > len))
> > > > > + printf("SF: Operate on the protected area.Erase will be 
> > > > > ignored\n");
> > > 
> > > My fundamental question, why cannot we use 'sf protect' then 'sf write'?
> > 
> > Where do we tell people to always run "sf protect" before "sf write" and
> > why is that at all user friendly?  No, we shouldn't run this test more
> > than once per time we're told to write an image.  But silently failing
> > in cases we can detect a problem is also not correct.  If it's possible
> > to spot this easily with "sf protect" why not just do that as part of
> > "sf write" and add a flag to skip the check if you know it's not needed?
> > I assume it's a fairly cheap/quick operation to do this check.
> > 
> 
> What's the status here? Who should propose/implement what now?

Good question.  Re-reading the quoted part here, the (valid!) concern I
see on the one hand is that today you can "sf write", see "OK" and have
had nothing written because the flash was protected, and that's
something we could have known at the start of "sf write".  The change as
written is within the write API, rather than the CLI API, so could we
move that check to cmd/sf.c instead?

-- 
Tom


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Re: [PATCH 02/13] arm: dts: add the Purism devicetree files

2022-01-17 Thread Tom Rini
On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote:
> Hi Tom,
> 
> On 2022-01-17 08:59, Tom Rini wrote:
> > On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:
> > 
> > > Initial commit of Librem5 devicetree files
> > > 
> > > Signed-off-by: Angus Ainslie 
> > 
> > Please note what kernel release the not -u-boot.dtsi files are a copy
> > from, as they need to be copies and not modified, thanks.
> 
> There's an issue with adding the devicetree from the 5.16 kernel.
> 
> I get a compilation error due to a :missing .h in the devicetree files:
> 
> In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11,
>  from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6:
> arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error:
> dt-bindings/rfkill/rfkill.h: No such file or directory
>13 | #include "dt-bindings/rfkill/rfkill.h"
>   |  ^
> 
> Should that get added to the u-boot source as well or should I modify the
> dts to remove this ?

Import the missing binding(s) in a separate commit first please.

> For the kernel we also have 4 different dts files for the differences in PCB
> versions. For u-boot we don't need the differentiation as it deals with
> things like camera rotation and prox sensor sensitivity.
> 
> There's 2 ways to solve the this I think.
> 
> 1) just use the latest librem5 dts file which is made up of 3 different
> dts(i) files.
> 2) have a defconfig for each of the different PCB versions.
> 
> Do you have a preference ?

Can you tell the revision at run-time?  We have examples of boards that
can and will include revA.dtb and revB.dtb and select the correct one at
run time (and start with something that works on revA and revB).

-- 
Tom


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Re: [PATCH] board: ti: am335x: Choose CPSW or PRUSS configuration based on jumper setting

2022-01-17 Thread Tom Rini
On Fri, Oct 29, 2021 at 04:08:17PM +0200, Amjad Ouled-Ameur wrote:

> The am335x-ice-v2 board's Ethernet ports can be configured
> in 'MII' or 'RMII' mode to be connected to 'PRUSS' or 'CPSW'
> Ethernet subsystems.
> 
> This patch sets the environment variable 'ice_mii' to
> 'mii' or 'rmii' accordingly. Based on that we choose the
> appropriate board devicetree i.e. 'am335x-ice-v2.dtb' or
> 'am335x-ice-v2-prueth.dtb'.
> 
> Since there are 2 Ethernet ports with 2 modes, there can be 4
> configurations but for now we consider both ports in different modes
> to be an invalid configuration and prevent boot in that case.
> 
> Signed-off-by: Roger Quadros 
> [Amjad: use overlay instead of using new am335x-ice-v2-prueth.dtb]
> Signed-off-by: Amjad Ouled-Ameur 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] nand: gpmc: Handle bitflips in erased pages when using BCH ECC engine

2022-01-17 Thread Tom Rini
On Thu, Nov 18, 2021 at 01:25:24PM -0500, David Rivshin wrote:

> From: David Rivshin 
> 
> In the case of an erased (sub)page both the data and ECC are all 0xFF
> bytes. This fails the normal ECC verification, as the computed ECC of
> all-0xFF is not also 0xFF. The GPMC NAND driver attempted to detect
> erased pages by checking that the ECC bytes are all-0xFF, but this had
> two problems:
> 1) bitflips in the data were not corrected, so the data looked not-erased
> 2) bitflips in the ECC bytes were reported as uncorrectable ECC errors
> 
> The equivalent Linux driver [1] correctly handles this by counting the
> number of 0-bits in the combination of data and ECC bytes. If the number
> of 0-bits is less than the amount of bits correctable by the selected
> ECC algorithm, then it is treated as an erased page with correctable
> bitflips.
> 
> Implement similar, though simplified, logic in omap_correct_data_bch().
> 
> [1] see omap_elm_correct_data() in omap2.c
> 
> Signed-off-by: David Rivshin 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372

2022-01-17 Thread Tom Rini
On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote:

> On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
> divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
> See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.
> 
> The QSPI_FCLK therefore needs to take this factor into account and
> becomes (19200 / 4).
> 
> Signed-off-by: Stefan Mätje 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] configs: am43xx_hs_evm: Add SPL_USB_STORAGE Support

2022-01-17 Thread Tom Rini
On Mon, Dec 06, 2021 at 06:22:00PM +0100, Amjad Ouled-Ameur wrote:

> Enable CONFIG_SPL_USB_STORAGE to support UBS MSC boot support.
> 
> Signed-off-by: Faiz Abbas 
> Signed-off-by: Amjad Ouled-Ameur 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] arm: mach-k3: am642_init: Unlock MCU PADCFG regs

2022-01-17 Thread Tom Rini
On Wed, Dec 15, 2021 at 04:14:28PM +0100, Christian Gmeiner wrote:

> From: Michael Liebert 
> 
> Currently only the PADCFG registers of the main domain are unlocked.
> Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be 
> configured by u-boot or Linux.
> 
> Signed-off-by: Michael Liebert 
> Tested-by: Christian Gmeiner 
> Acked-by: Nishanth Menon 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] omap: timer: implement timer_get_boot_us

2022-01-17 Thread Tom Rini
On Thu, Dec 16, 2021 at 10:57:29AM +0100, Christian Gmeiner wrote:

> To make the OMAP DM timer driver useful for the timing of
> bootstages, we need to implement timer_get_boot_us(..).
> 
> Signed-off-by: Christian Gmeiner 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode

2022-01-17 Thread Tom Rini
On Thu, Dec 23, 2021 at 07:26:03PM +0530, Vignesh Raghavendra wrote:

> In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed
> in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image
> directly on OSPI flash via MMIO window. So, copy the image to internal
> on-chip RAM before parsing the image.
> 
> Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform
> and thus cannot reside in OSPI/xSPI and needs to be copied over to
> internal OCRAM.
> 
> This unblocks OSPI/xSPI boot on HS platforms
> 
> Signed-off-by: Vignesh Raghavendra 
> Reviewed-by: Dave Gerlach 
> Tested-by: Keerthy 
> Acked-by: Pratyush Yadav 

Applied to u-boot/master, thanks!

-- 
Tom


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