[U-Boot] [PATCH 1/3] armv8/ls1043aqds: fix fman ucode address to an offset in QSPI flash

2016-03-09 Thread Gong Qianyu
Modify the value as the SPI interface is changed.

Signed-off-by: Gong Qianyu 
---
 include/configs/ls1043a_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 7018cb5..c78ba47 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -222,7 +222,7 @@
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR0x400d
+#define CONFIG_SYS_FMAN_FW_ADDR0xd
 #define CONFIG_ENV_SPI_BUS 0
 #define CONFIG_ENV_SPI_CS  0
 #define CONFIG_ENV_SPI_MAX_HZ  100
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] deconfig: ls1043ardb_SECURE_BOOT: fix line format

2016-03-09 Thread Gong Qianyu
Signed-off-by: Gong Qianyu 
---
 configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 4004435..34f7f29 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -7,4 +7,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
-CONFIG_DM_SPI=y
\ No newline at end of file
+CONFIG_DM_SPI=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/3] armv8/ls1043a: move CONFIG_MTD to defconfig

2016-03-09 Thread Gong Qianyu
To make it take effect to enable MTD driver model for SPI-NOR.

Signed-off-by: Gong Qianyu 
---
 configs/ls1043aqds_defconfig | 1 +
 configs/ls1043aqds_lpuart_defconfig  | 1 +
 configs/ls1043aqds_nand_defconfig| 1 +
 configs/ls1043aqds_nor_ddr3_defconfig| 1 +
 configs/ls1043aqds_qspi_defconfig| 1 +
 configs/ls1043aqds_sdcard_ifc_defconfig  | 1 +
 configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
 configs/ls1043ardb_SECURE_BOOT_defconfig | 1 +
 configs/ls1043ardb_defconfig | 1 +
 configs/ls1043ardb_nand_defconfig| 1 +
 configs/ls1043ardb_sdcard_defconfig  | 1 +
 include/configs/ls1043a_common.h | 1 -
 12 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index bd18d46..73d5258 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
index 97f0f70..3de2360 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/ls1043aqds_nand_defconfig 
b/configs/ls1043aqds_nand_defconfig
index 4153a1f..01b57a8 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig 
b/configs/ls1043aqds_nor_ddr3_defconfig
index 029b851..1c2b36b 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_qspi_defconfig 
b/configs/ls1043aqds_qspi_defconfig
index 04655e3..2a300ac 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_SYS_NS16550=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig 
b/configs/ls1043aqds_sdcard_ifc_defconfig
index f263517..f0c6173 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig 
b/configs/ls1043aqds_sdcard_qspi_defconfig
index cf77f53..ceb04c7 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_SYS_NS16550=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 34f7f29..81f992f 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index aad386f..f6076a8 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_nand_defconfig 
b/configs/ls1043ardb_nand_defconfig
index ccb50b1..c0dadd2 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_MTD=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_M25P80=y
 CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_sdcard_defconfig 
b/configs/ls1043ardb_sdcard_defconfig
index 1eba8fd..11d6605 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONF

Re: [U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support

2016-03-09 Thread Qianyu Gong
Hi Jagan,

> -Original Message-
> From: york sun
> Sent: Tuesday, March 08, 2016 12:46 AM
> To: Jagan Teki ; Huan Wang ;
> Qianyu Gong 
> Cc: u-boot@lists.denx.de; Siva Durga Prasad Paladugu ;
> Stefan Roese ; Michal Simek ; Tom Rini
> 
> Subject: Re: [U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support
> 
> On 03/03/2016 01:06 PM, york sun wrote:
> > On 02/29/2016 04:26 AM, Jagan Teki wrote:
> >> Hi York,
> >>
> >> On 27 February 2016 at 02:14, york sun  wrote:
> >>> On 02/22/2016 10:18 AM, Jagan Teki wrote:
> 
> 
> 
> 
>  Can you pls- test the dataflash changes? use u-boot-spi/spi-nor
> 
> >>> Jagan,
> >>>
> >>> I am getting there. Will test sf probe/read/write and probably boot
> >>> on selected platforms. Is there any specific platform/test in your mind?
> >>
> >> Yes, these tests OK. and if possible please verify 'sf protect' as well.
> >>
> >
> > Jagan,
> >
> > Sorry for the delay. I am having issue with both ls1021aqds and
> > ls1043aqds. Need to work with internal team to sort it out.
> >
> > My understanding the tests you need are for spi-nor, in my case,
> > fsl-qspi, right? This is not for fsl-dspi or fsl-espi driver. I only
> > have ls1021aqds and ls1043aqds with such support.
> >
> 
> Jagan,
> 
> Alison and Qianyu have tested on LS1021AQDS and LS1043AQDS. There were some
> issues. They will post their findings (and possible fix) to this thread.
> 
> York

I tested on LS1043AQDS board based on your spi-nor branch. The 'spi_flash_probe'
failed during QSPI boot. Then I found that CONFIG_DM_MTD_SPI_NOR is not defined
for the board but it could be selected if CONFIG_MTD && CONFIG_DM_SPI, correct? 

So after I moved CONFIG_MTD to the defconfig file, the probing could work now.

And there is another small effect on our Fman driver. It would like to read 
ucode blob 
from the QSPI flash. As the 'spi_flash_read' interface is changed, I've 
modified the address
value to an offset value in flash.

Here are my patches:
http://patchwork.ozlabs.org/patch/594872/
http://patchwork.ozlabs.org/patch/594873/
http://patchwork.ozlabs.org/patch/594874/


Regards,
Qianyu
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[U-Boot] [PATCH 2/3] imx: mx6: correct IPU clock

2016-03-09 Thread Peng Fan
The CONFIG_IPUV3_CLK should be 26400, to i.MX6DL, it should be
19800.

Signed-off-by: Peng Fan 
Signed-off-by: Sandor Yu 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Peter Robinson 
---
 include/configs/mx6sabre_common.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/configs/mx6sabre_common.h 
b/include/configs/mx6sabre_common.h
index 29d1f91..a6d821b 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -225,7 +225,11 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 26000
+#ifdef CONFIG_MX6DL
+#define CONFIG_IPUV3_CLK 19800
+#else
+#define CONFIG_IPUV3_CLK 26400
+#endif
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
-- 
2.6.2

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[U-Boot] [PATCH 1/3] video: ipu: avoid overflow issue

2016-03-09 Thread Peng Fan
Multiplication, as "clk->parent->rate * 16" may overflow. So use
do_div to avoid such issue.

Signed-off-by: Peng Fan 
Signed-off-by: Sandor Yu 
Cc: Anatolij Gustschin 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 drivers/video/ipu_common.c | 73 ++
 1 file changed, 54 insertions(+), 19 deletions(-)

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 9f85102..36d4b23 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "ipu.h"
 #include "ipu_regs.h"
 
@@ -275,50 +276,84 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, 
int bufNum,
 
 static void ipu_pixel_clk_recalc(struct clk *clk)
 {
-   u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
-   if (div == 0)
-   clk->rate = 0;
-   else
-   clk->rate = (clk->parent->rate * 16) / div;
+   u32 div;
+   u64 final_rate = (unsigned long long)clk->parent->rate * 16;
+
+   div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+   debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
+ div, final_rate, clk->parent->rate);
+
+   clk->rate = 0;
+   if (div != 0) {
+   do_div(final_rate, div);
+   clk->rate = final_rate;
+   }
 }
 
 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
unsigned long rate)
 {
-   u32 div, div1;
-   u32 tmp;
+   u64 div, final_rate;
+   u32 remainder;
+   u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
+
/*
 * Calculate divider
 * Fractional part is 4 bits,
 * so simply multiply by 2^4 to get fractional part.
 */
-   tmp = (clk->parent->rate * 16);
-   div = tmp / rate;
-
+   div = parent_rate;
+   remainder = do_div(div, rate);
+   /* Round the divider value */
+   if (remainder > (rate / 2))
+   div++;
if (div < 0x10)/* Min DI disp clock divider is 1 */
div = 0x10;
if (div & ~0xFEF)
div &= 0xFF8;
else {
-   div1 = div & 0xFE0;
-   if ((tmp/div1 - tmp/div) < rate / 4)
-   div = div1;
-   else
-   div &= 0xFF8;
+   /* Round up divider if it gets us closer to desired pix clk */
+   if ((div & 0xC) == 0xC) {
+   div += 0x10;
+   div &= ~0xF;
+   }
}
-   return (clk->parent->rate * 16) / div;
+   final_rate = parent_rate;
+   do_div(final_rate, div);
+
+   return final_rate;
 }
 
 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 {
-   u32 div = (clk->parent->rate * 16) / rate;
+   u64 div, parent_rate;
+   u32 remainder;
+
+   parent_rate = (unsigned long long)clk->parent->rate * 16;
+   div = parent_rate;
+   remainder = do_div(div, rate);
+   /* Round the divider value */
+   if (remainder > (rate / 2))
+   div++;
+
+   /* Round up divider if it gets us closer to desired pix clk */
+   if ((div & 0xC) == 0xC) {
+   div += 0x10;
+   div &= ~0xF;
+   }
+   if (div > 0x1000)
+   debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
 
__raw_writel(div, DI_BS_CLKGEN0(clk->id));
 
-   /* Setup pixel clock timing */
+   /*
+* Setup pixel clock timing
+* Down time is half of period
+*/
__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 
-   clk->rate = (clk->parent->rate * 16) / div;
+   clk->rate = (u64)(clk->parent->rate * 16) / div;
+
return 0;
 }
 
-- 
2.6.2

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[U-Boot] [PATCH 3/3] imx: mx6: hdmi: handle overflow condition

2016-03-09 Thread Peng Fan
If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.

Signed-off-by: Peng Fan 
Signed-off-by: Sandor Yu 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/cpu/armv7/mx6/soc.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a34675c..91a3deb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -548,7 +548,8 @@ void imx_setup_hdmi(void)
 {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-   int reg;
+   int reg, count;
+   u8 val;
 
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
@@ -565,6 +566,16 @@ void imx_setup_hdmi(void)
 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+   /* Clear the overflow condition */
+   if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
+   /* TMDS software reset */
+   writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
+   val = readb(&hdmi->fc_invidconf);
+   /* Need minimum 3 times to write to clear the register */
+   for (count = 0 ; count < 5 ; count++)
+   writeb(val, &hdmi->fc_invidconf);
+   }
 }
 #endif
 
-- 
2.6.2

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[U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Peng Fan
From: Ye Li 

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 arch/arm/cpu/armv7/mx6/soc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 91a3deb..bdd41b0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
 
/* Clear MMDC channel mask */
-   reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+   if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 
is_cpu_type(MXC_CPU_MX6SL))
+   reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+   else
+   reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | 
MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
writel(reg, &mxc_ccm->ccdr);
 }
 
-- 
2.6.2

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Re: [U-Boot] [PATCH v2] arm: imx: Add support for GE Bx50v3 boards

2016-03-09 Thread Stefano Babic
Hi Akshay,

On 08/03/2016 23:48, Akshay Bhat wrote:
> Hi Stefano,
> 
> On 01/29/2016 11:07 PM, Peng Fan wrote:
>> Hi Akshay,
>>
>> On Fri, Jan 29, 2016 at 03:16:40PM -0500, Akshay Bhat wrote:
>>> Add support for GE B450v3, B650v3 and B850v3 boards. The boards
>>> are based on Advantech BA16 module which has a i.MX6D processor.
>>> The boards support:
>>> - FEC Ethernet
>>> - USB Ports
>>> - SDHC and MMC boot
>>> - SPI NOR
>>> - LVDS and HDMI display
>>>
>>> Basic information about the module:
>>> - Module manufacturer: Advantech
>>> - CPU: Freescale ARM Cortex-A9 i.MX6D
>>> - SPECS:
>>>  Up to 2GB Onboard DDR3 Memory;
>>>  Up to 16GB Onboard eMMC NAND Flash
>>>  Supports OpenGL ES 2.0 and OpenVG 1.1
>>>  HDMI, 24-bit LVDS
>>>  1x UART, 2x I2C, 8x GPIO,
>>>  4x Host USB 2.0 port, 1x USB OTG port,
>>>  1x micro SD (SDHC),1x SDIO, 1x SATA II,
>>>  1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
>>>
>>> Signed-off-by: Akshay Bhat 
>>
>>
>> Reviewed-by: Peng Fan 
>>
>> Regards,
>> Peng.
>>
> 
> If there are no further review comments, can this patch be applied in
> the next merge window (for v2016.05)?
> 

Yes, I will do it.

> Also I have couple updates to the bx50v3.c file. Should I wait for this
> patch to be applied before sending a new patch with the changes (wasn't
> sure if you had a -next branch where the v2 patch was already applied)?
> 

Tom has proposed several times to the custodian to have a -next branch,
and making it really working. I admit I have not done enough for that,
and it is something I can improve. I will prepare a "working" -next, to
be merged into master after release.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH v2] arm: imx: Add support for GE Bx50v3 boards

2016-03-09 Thread Stefano Babic
On 09/03/2016 00:31, Fabio Estevam wrote:
> On Tue, Mar 8, 2016 at 7:48 PM, Akshay Bhat  wrote:
> 
>> If there are no further review comments, can this patch be applied in the
>> next merge window (for v2016.05)?
>>
>> Also I have couple updates to the bx50v3.c file. Should I wait for this
>> patch to be applied before sending a new patch with the changes (wasn't sure
>> if you had a -next branch where the v2 patch was already applied)?
> 
> Yes, a -next branch would be very convenient.
> 

Right, this was discussed several times in the U-Boot summit at ELCE. I
will prepare it.

Regards,
Stefano

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[U-Boot] [PATCH 3/3] imx: print ARM clock for clocks command

2016-03-09 Thread Peng Fan
Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS 792 MHz
PLL_BUS 528 MHz
PLL_OTG 480 MHz
PLL_NET  50 MHz

ARM  396000 kHz
"

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 88380a6..3b53842 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
printf("PLL_NET%8d MHz\n", freq / 100);
 
printf("\n");
+   printf("ARM%8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
printf("IPG%8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART   %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 #ifdef CONFIG_MXC_SPI
-- 
2.6.2

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[U-Boot] [PATCH 1/3] imx: mx6ul: skip setting ahb rate

2016-03-09 Thread Peng Fan
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/soc.c | 19 ---
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bdd41b0..f29901f 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -328,13 +328,18 @@ int arch_cpu_init(void)
 */
init_bandgap();
 
-   /*
-* When low freq boot is enabled, ROM will not set AHB
-* freq, so we need to ensure AHB freq is 132MHz in such
-* scenario.
-*/
-   if (mxc_get_clock(MXC_ARM_CLK) == 39600)
-   set_ahb_rate(13200);
+   if (!IS_ENABLED(CONFIG_MX6UL)) {
+   /*
+* When low freq boot is enabled, ROM will not set AHB
+* freq, so we need to ensure AHB freq is 132MHz in such
+* scenario.
+*
+* To i.MX6UL, when power up, default ARM core and
+* AHB rate is 396M and 132M.
+*/
+   if (mxc_get_clock(MXC_ARM_CLK) == 39600)
+   set_ahb_rate(13200);
+   }
 
/* Set perclk to source from OSC 24MHz */
 #if defined(CONFIG_MX6SL)
-- 
2.6.2

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[U-Boot] [PATCH 2/3] imx: mx6ul configure the PMIC_STBY_REQ pin as open drain

2016-03-09 Thread Peng Fan
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/soc.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f29901f..d4b22ad 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -341,7 +341,17 @@ int arch_cpu_init(void)
set_ahb_rate(13200);
}
 
-   /* Set perclk to source from OSC 24MHz */
+   if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+   /*
+* According to the design team's requirement on i.MX6UL,
+* the PMIC_STBY_REQ PAD should be configured as open
+* drain 100K (0xb8a0).
+* Only exists on TO1.0
+*/
+   writel(0xb8a0, IOMUXC_BASE_ADDR + 0x29c);
+   }
+
+   /* Set perclk to source from OSC 24MHz */
 #if defined(CONFIG_MX6SL)
set_preclk_from_osc();
 #endif
-- 
2.6.2

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Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-09 Thread Bakhvalov, Denis (Nokia - PL/Wroclaw)
Hi,

> However there is still no ping in U-Boot.
> After power reset I did:
>
> ># bridge disable
> ># fpga load 0  
> ># bridge enable
>
> ># md 0xff706000 1
> ff706000: 0074  <-- this means fpga is in user mode
>
> ># setenv ethaddr ...
> ># setenv ipaddr ...
> ># setenv netmask ...
> ># setenv gatewayip ...
>
> => ping 192.168.1.126
> Speed: 100, full duplex
> Using ethernet@ff702000 device
> ping failed; host 192.168.1.126 is not alive
>
> With similar commands on previous U-Boot version I had ping.

Also using wireshark I found that board sends correct ARP packets to PC.
PC in it's turn send valid ARP response to the board.
But for some reason ARP reply is not handled by the board.
And board doesn't send ICMP packets to the PC.

I already checked ip addresses, they should be fine.
Also the same IP works fine for previous U-Boot version (2013).

What could be the reason for that?

Best regards,
Denis Bakhvalov
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[U-Boot] [PATCH V2 0/3] imx6ul: convert to enable pinctrl/DM POWER

2016-03-09 Thread Peng Fan

V2: Only a small change:
Use CONFIG_SPL_BUILD to comment out I2C to SPL, but not CONFIG_SPL
for PATCH V2 3/3

This patch set is to covert to enable pinctrl driver and
DM_PMIC and DM_REGULATOR for imx6ul 14x14/9x9 evk board.

This patch set is only to add device tree for i.MX6UL and
is just initial step to convert to support device tree for
i.MX6/7, I just have an idea to discard the pinmux settings
in board file and let pinctrl driver to handle these for
different drivers.

I am not very sure whether we need a full device tree here,
since we do not support so many devices as linux kernel.

Any comments on this? There maybe some work need to be done
to support this.

To the i2c part, the pinmux settings are still needed in
board file, because there are some dependency in
arch/arm/imx-common/i2c-mxv7.c. In future, we may need
to refine this to totally let i2c driver handle this.

Peng Fan (3):
  imx: imx6ul: Introduce device tree files
  imx: mx6ul_evk: default enable device tree support
  imx: mx6ul_evk: convert to use Driver model for power and i2c

 arch/arm/dts/Makefile |4 +
 arch/arm/dts/imx6ul-14x14-evk.dts |  693 
 arch/arm/dts/imx6ul-9x9-evk.dts   |  790 ++
 arch/arm/dts/imx6ul-pinfunc.h |  938 +
 arch/arm/dts/imx6ul.dtsi  | 1158 +
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |   38 +-
 configs/mx6ul_14x14_evk_defconfig |   16 +-
 configs/mx6ul_9x9_evk_defconfig   |   23 +-
 include/configs/mx6ul_14x14_evk.h |   11 +-
 include/dt-bindings/clock/imx6ul-clock.h  |  240 +
 10 files changed, 3868 insertions(+), 43 deletions(-)
 create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dts
 create mode 100644 arch/arm/dts/imx6ul-9x9-evk.dts
 create mode 100644 arch/arm/dts/imx6ul-pinfunc.h
 create mode 100644 arch/arm/dts/imx6ul.dtsi
 create mode 100644 include/dt-bindings/clock/imx6ul-clock.h

-- 
2.6.2

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[U-Boot] [PATCH V2 2/3] imx: mx6ul_evk: default enable device tree support

2016-03-09 Thread Peng Fan
Default enable device tree for mx6ul_14x14_evk and
mx6ul_9x9_evk board. And sort the defconfig file to be in
alphabet order.

Enable pinctrl driver for the two boards.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 configs/mx6ul_14x14_evk_defconfig | 15 ++-
 configs/mx6ul_9x9_evk_defconfig   | 15 ++-
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/configs/mx6ul_14x14_evk_defconfig 
b/configs/mx6ul_14x14_evk_defconfig
index 835285f..a756de7 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -1,8 +1,13 @@
-CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6UL_14X14_EVK=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
-CONFIG_CMD_GPIO=y
+CONFIG_ARM=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_PING=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_TARGET_MX6UL_14X14_EVK=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index efbffe3..fed0254 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -1,8 +1,13 @@
-CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6UL_9X9_EVK=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
-CONFIG_CMD_GPIO=y
+CONFIG_ARM=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_PING=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_TARGET_MX6UL_9X9_EVK=y
-- 
2.6.2

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[U-Boot] [PATCH V2 3/3] imx: mx6ul_evk: convert to use Driver model for power and i2c

2016-03-09 Thread Peng Fan
Convert to use DM_PMIC/DM_REGULATOR/DM_I2C for mx6ul evk.
To mx6ul_14x14_evk, there is no pmic on board, so only enable DM_I2C.

Since we have PINCTRL driver and DM_I2C enabled, we could discard
the pinmux setting in board file, but we can not do this, because
still some dependency in arch/arm/imx-common/i2c-mxv7.c. Later
we may need to find out a way to refine this.

To avoid SPL build warning, disable mxc_i2c driver for SPL part.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 38 +--
 configs/mx6ul_14x14_evk_defconfig |  1 +
 configs/mx6ul_9x9_evk_defconfig   |  8 +
 include/configs/mx6ul_14x14_evk.h | 11 ++-
 4 files changed, 25 insertions(+), 33 deletions(-)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c 
b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 98d5675..62a3e68 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -174,45 +174,35 @@ static struct i2c_pads_info i2c_pad_info1 = {
},
 };
 
-#ifdef CONFIG_POWER
-#define I2C_PMIC   0
+#ifdef CONFIG_DM_PMIC
 int power_init_board(void)
 {
if (is_mx6ul_9x9_evk()) {
-   struct pmic *pfuze;
-   int ret;
-   unsigned int reg, rev_id;
+   struct udevice *dev;
+   int ret, dev_id, rev_id;
 
-   ret = power_pfuze3000_init(I2C_PMIC);
-   if (ret)
+   ret = pmic_get("pfuze3000", &dev);
+   if (ret == -ENODEV)
+   return 0;
+   else if (ret != 0)
return ret;
 
-   pfuze = pmic_get("PFUZE3000");
-   ret = pmic_probe(pfuze);
-   if (ret)
-   return ret;
-
-   pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
-   pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+   dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+   rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
-  reg, rev_id);
+  dev_id, rev_id);
 
/* disable Low Power Mode during standby mode */
-   pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®);
-   reg |= 0x1;
-   pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+   pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
/* SW1B step ramp up time from 2us to 4us/25mV */
-   reg = 0x40;
-   pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
+   pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
 
/* SW1B mode to APS/PFM */
-   reg = 0xc;
-   pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
+   pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
 
/* SW1B standby voltage set to 0.975V */
-   reg = 0xb;
-   pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
+   pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
}
 
return 0;
diff --git a/configs/mx6ul_14x14_evk_defconfig 
b/configs/mx6ul_14x14_evk_defconfig
index a756de7..b67e0cb 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_PING=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_DM_I2C=y
 CONFIG_OF_CONTROL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_FULL=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index fed0254..cebfbdd 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -3,7 +3,15 @@ CONFIG_ARM=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_DM_I2C=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_ERRNO_STR=y
 CONFIG_OF_CONTROL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_FULL=y
diff --git a/include/configs/mx6ul_14x14_evk.h 
b/include/configs/mx6ul_14x14_evk.h
index c7e10f9..f6f8240 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -50,19 +50,12 @@
 #endif
 
 /* I2C configs */
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_CMD_I2C
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED   10
-
-/* PMIC only for 9X9 EVK */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR  0x08
+#endif
 #endif
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
-- 
2.6.2

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Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Stefano Babic
Hi Peng, Ye,

On 09/03/2016 09:13, Peng Fan wrote:
> From: Ye Li 
> 
> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
> When clear this bit, the periph_clk_sel cannot be set and that
> CDHIPR[periph_clk_sel_busy] handshake never clears.
> 
> Signed-off-by: Ye Li 
> Signed-off-by: Peng Fan 
> ---
>  arch/arm/cpu/armv7/mx6/soc.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 91a3deb..bdd41b0 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
>   reg = readl(&mxc_ccm->ccdr);
>  
>   /* Clear MMDC channel mask */
> - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 
> is_cpu_type(MXC_CPU_MX6SL))
> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
> + else
> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | 
> MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
>   writel(reg, &mxc_ccm->ccdr);
>  }
>  

Acked-by: Stefano Babic 

This is a fix, and my question to you both: is it enough to merge it
after 2016.03 ? I have not read about big issues due to periph_clk_sel,
and maybe we can postponed it (or I merge directly into -next as several
of you have already proposed).

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH] spl: add a new stub spl_early_board_init() for early SoC-specific setup

2016-03-09 Thread Masahiro Yamada
Hi Tom,



2016-03-09 8:23 GMT+09:00 Tom Rini :
> On Tue, Mar 08, 2016 at 08:37:16PM +0900, Masahiro Yamada wrote:
>
>> We are generally supposed to implement SoC/board-specific SPL init
>> code in spl_board_init(), but it is called after spl_init() where the
>> FDT is setup and devices are bound.
>>
>> This new stub spl_early_board_init() would be useful to put something
>> really SoC-specific, for example, debug_uart_init().
>>
>> In fact, I was hit by some problems on FDT setup when I was tackling
>> on a completely new platform.  I wished I could use the debug UART
>> earlier in situations like that.
>>
>> Signed-off-by: Masahiro Yamada 
>
> This is usually done with s_init() and uniphier opts out of that.

Yes, ARM32 UniPhier needs to do some tricky initialization right after
the start-up,
so it has its own lowlevel_init.

ARM64 UniPhier is more like the standard ARM architecture,
so hopefully I will be able to reuse more common code.

>  I
> would conceed however that things could use some further clean-up and
> organization here.

As Simon pointed out, an alternative would be to override board_init_f().
I can live with that, too.




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Re: [U-Boot] [PATCH] spl: add a new stub spl_early_board_init() for early SoC-specific setup

2016-03-09 Thread Masahiro Yamada
Hi Simon,


2016-03-09 8:33 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 8 March 2016 at 04:37, Masahiro Yamada  
> wrote:
>> We are generally supposed to implement SoC/board-specific SPL init
>> code in spl_board_init(), but it is called after spl_init() where the
>> FDT is setup and devices are bound.
>>
>> This new stub spl_early_board_init() would be useful to put something
>> really SoC-specific, for example, debug_uart_init().
>>
>> In fact, I was hit by some problems on FDT setup when I was tackling
>> on a completely new platform.  I wished I could use the debug UART
>> earlier in situations like that.
>>
>> Signed-off-by: Masahiro Yamada 
>> ---
>>
>>  common/spl/spl.c | 6 ++
>>  include/spl.h| 1 +
>>  2 files changed, 7 insertions(+)
>>
>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>> index e5167bf..df85b09 100644
>> --- a/common/spl/spl.c
>> +++ b/common/spl/spl.c
>> @@ -150,6 +150,10 @@ static int spl_ram_load_image(void)
>>  }
>>  #endif
>>
>> +void __weak spl_early_board_init(void)
>> +{
>> +}
>> +
>>  int spl_init(void)
>>  {
>> int ret;
>> @@ -344,6 +348,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
>>  {
>> int i;
>>
>> +   spl_early_board_init();
>
> Why not put this in board_init_f()? That is a little earlier.

The reason is board_init_f() for SPL is not placed in the common place.

We can move it there if it is OK to deal with it per arch.


> In fact you can replace that function with your own version.

Right.  This is an alternative.

The definition of board_init_f() in arch/arm/lib/spl.c is short enough.

I can copy it into arch/arm/mach-uniphier/ and adjust it for my own use.


> (although it would be better if we had a single board_init_f() and
> called out to board-specific code from there.)
>
>> +
>> debug(">>spl:board_init_r()\n");
>>

So, what shall we do about this?


-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Peng Fan
Hi Stefano,

On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote:
>Hi Peng, Ye,
>
>On 09/03/2016 09:13, Peng Fan wrote:
>> From: Ye Li 
>> 
>> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
>> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
>> When clear this bit, the periph_clk_sel cannot be set and that
>> CDHIPR[periph_clk_sel_busy] handshake never clears.
>> 
>> Signed-off-by: Ye Li 
>> Signed-off-by: Peng Fan 
>> ---
>>  arch/arm/cpu/armv7/mx6/soc.c | 5 -
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
>> index 91a3deb..bdd41b0 100644
>> --- a/arch/arm/cpu/armv7/mx6/soc.c
>> +++ b/arch/arm/cpu/armv7/mx6/soc.c
>> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
>>  reg = readl(&mxc_ccm->ccdr);
>>  
>>  /* Clear MMDC channel mask */
>> -reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
>> +if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || 
>> is_cpu_type(MXC_CPU_MX6SL))
>> +reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
>> +else
>> +reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | 
>> MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
>>  writel(reg, &mxc_ccm->ccdr);
>>  }
>>  
>
>Acked-by: Stefano Babic 
>
>This is a fix, and my question to you both: is it enough to merge it
>after 2016.03 ? I have not read about big issues due to periph_clk_sel,
>and maybe we can postponed it (or I merge directly into -next as several
>of you have already proposed).

Yeah. It's okay to merge after 2016.03.

Regards,
Peng.

>
>Best regards,
>Stefano Babic
>
>
>
>-- 
>=
>DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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[U-Boot] [PATCH 02/10] ti_armv7_keystone2: env: Update UBIFS image paths

2016-03-09 Thread Lokesh Vutla
From: Carlos Hernandez 

UBI images created by OE does not contain boot partition by default,
instead kernel and dtb are placed in /boot directory inside rootfs
partition. So update env commands to load files from correct
location.

Signed-off-by: Carlos Hernandez 
Signed-off-by: Lokesh Vutla 
---
 include/configs/ti_armv7_keystone2.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 39e9852..85f5d64 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -240,6 +240,7 @@
DEFAULT_LINUX_BOOT_ENV  \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
"boot=ubi\0"\
+   "bootdir=/boot\0" \
"tftp_root=/\0" \
"nfs_root=/export\0"\
"mem_lpae=1\0"  \
@@ -251,14 +252,14 @@
"run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \
"init_net=run args_all args_net\0"  \
"init_ubi=run args_all args_ubi; "  \
-   "ubi part ubifs; ubifsmount ubi:boot;"  \
+   "ubi part ubifs; ubifsmount ubi:rootfs;"
\
"ubifsload ${addr_secdb_key} securedb.key.bin;\0"   \
"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"\
-   "get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0"\
+   "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" 
\
"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
-   "get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0" \
+   "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"  
\
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"   \
-   "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"   \
+   "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0"
\
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"   \
"burn_uboot_spi=sf probe; sf erase 0 0x8; " \
"sf write ${loadaddr} 0 ${filesize}\0"  \
-- 
2.1.4

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[U-Boot] [PATCH 00/10] ti: configs: Misc updates for config files

2016-03-09 Thread Lokesh Vutla
This series does miscellaneous updates to config files and environment
variables.

This depends on the TI's PMMC support on K2G SoC series posted by
Nishanth Menon[1]

[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg204671.html

Carlos Hernandez (2):
  ti_armv7_keystone2: env: Update UBIFS image paths
  ti_armv7_keystone2: env: Remove securedb.key.bin load

Lokesh Vutla (4):
  am335x: configs: Fix usb ether boot support
  ti_armv7_common: env: Consolidate support for loading script and text
env files
  k2g: env: Allow use of a script and plain text env files
  k2g: configs: Add support to save env in MMC

Mugunthan V N (2):
  ti_armv7_keystone2: configs: add usb mass storage support
  am43xx: configs: Enable USB commands for non usb boot also

Murali Karicheri (1):
  keystone2: env: add env script for booting with an initramfs with
firmware

Yan Liu (1):
  keystone2: env: Set mmc as default boot for k2g-evm

 include/configs/am335x_evm.h | 28 +---
 include/configs/am43xx_evm.h | 17 -
 include/configs/k2e_evm.h|  2 ++
 include/configs/k2g_evm.h| 10 ++
 include/configs/k2hk_evm.h   |  2 ++
 include/configs/k2l_evm.h|  2 ++
 include/configs/ti_am335x_common.h   |  4 +++-
 include/configs/ti_armv7_common.h| 25 -
 include/configs/ti_armv7_keystone2.h | 27 ++-
 include/configs/ti_omap4_common.h|  7 +--
 include/configs/ti_omap5_common.h| 13 +
 11 files changed, 72 insertions(+), 65 deletions(-)

-- 
2.1.4

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[U-Boot] [PATCH 01/10] ti_armv7_keystone2: configs: add usb mass storage support

2016-03-09 Thread Lokesh Vutla
From: Mugunthan V N 

Add USB mass storage support so that kernel can be read from
connected usb storage.

Signed-off-by: Mugunthan V N 
Signed-off-by: Lokesh Vutla 
---
 include/configs/ti_armv7_keystone2.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 70a484e..39e9852 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -195,6 +195,7 @@
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_KEYSTONE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
 #define CONFIG_EFI_PARTITION
 #define CONFIG_FS_FAT
 #define CONFIG_SYS_CACHELINE_SIZE  64
-- 
2.1.4

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[U-Boot] [PATCH 06/10] ti_armv7_common: env: Consolidate support for loading script and text env files

2016-03-09 Thread Lokesh Vutla
Support for loading bootscript and text env file is duplicated in all TI
platforms. Add this information to DEFAULT_MMC_TI_ARGS so that it can be
reused in all TI platforms.

Signed-off-by: Lokesh Vutla 
---
 include/configs/am335x_evm.h  | 28 +---
 include/configs/am43xx_evm.h  | 13 +
 include/configs/ti_armv7_common.h | 25 -
 include/configs/ti_omap4_common.h |  7 +--
 include/configs/ti_omap5_common.h | 13 +
 5 files changed, 32 insertions(+), 54 deletions(-)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 6ebe0b3..8b0a721 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -94,6 +94,7 @@
 
 #define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+   "run envboot; " \
"run distro_bootcmd"
 
 #include 
@@ -123,13 +124,6 @@
"${optargs} " \
"root=${spiroot} " \
"rootfstype=${spirootfstype}\0" \
-   "bootenv=uEnv.txt\0" \
-   "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-   "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-   "source ${loadaddr}\0" \
-   "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
-   "importbootenv=echo Importing environment from mmc ...; " \
-   "env import -t -r $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
@@ -154,21 +148,10 @@
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
-   "if run loadbootscript; then " \
-   "run bootscript;" \
-   "else " \
-   "if run loadbootenv; then " \
-   "echo Loaded environment from 
${bootenv};" \
-   "run importbootenv;" \
-   "fi;" \
-   "if test -n $uenvcmd; then " \
-   "echo Running uenvcmd ...;" \
-   "run uenvcmd;" \
-   "fi;" \
-   "if run loadimage; then " \
-   "run mmcloados;" \
-   "fi;" \
-   "fi ;" \
+   "run envboot; " \
+   "if run loadimage; then " \
+   "run mmcloados;" \
+   "fi;" \
"fi;\0" \
"spiboot=echo Booting from spi ...; " \
"run spiargs; " \
@@ -200,7 +183,6 @@
BOOTENV
 #endif
 
-
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM10x44e09000  /* Base EVM has 
UART0 */
 #define CONFIG_SYS_NS16550_COM20x48022000  /* UART1 */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 0a96bd3..b982ed6 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -259,10 +259,6 @@
"${optargs} " \
"root=${usbroot} " \
"rootfstype=${usbrootfstype}\0" \
-   "bootenv=uEnv.txt\0" \
-   "loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \
-   "importbootenv=echo Importing environment from mmc ...; " \
-   "env import -t $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
@@ -275,14 +271,6 @@
"setenv devtype mmc; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${devnum};" \
-   "if run loadbootenv; then " \
-   "echo Loaded environment from ${bootenv};" \
-   "run importbootenv;" \
-   "fi;" \
-   "if test -n $uenvcmd; then " \
-   "echo Running uenvcmd ...;" \
-   "run uenvcmd;" \
-   "fi;" \
"if run loadimage; then " \
"run loadfdt; " \
"echo Booting from mmc${mmcdev} ...; " \
@@ -329,6 +317,7 @@
 
 #define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+   "run envboot;" \
"run mmcboot;" \
"run usbboot;" \
NANDBOOT \
diff --git a/include/configs/ti_armv7_common.h 
b/include/configs/ti_armv7_common.h
index 199612b..31079f6 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -64,7 +64,30 @@
"args_mmc=run finduuid;setenv bootargs console=${console} " \
"${optargs} " \
"root=PARTUU

[U-Boot] [PATCH 03/10] ti_armv7_keystone2: env: Remove securedb.key.bin load

2016-03-09 Thread Lokesh Vutla
From: Carlos Hernandez 

securedb.key.bin is not supported so it should not be loaded by
default init_ubi command.

Signed-off-by: Carlos Hernandez 
Signed-off-by: Lokesh Vutla 
---
 include/configs/ti_armv7_keystone2.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 85f5d64..e1effc0 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -252,8 +252,7 @@
"run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \
"init_net=run args_all args_net\0"  \
"init_ubi=run args_all args_ubi; "  \
-   "ubi part ubifs; ubifsmount ubi:rootfs;"
\
-   "ubifsload ${addr_secdb_key} securedb.key.bin;\0"   \
+   "ubi part ubifs; ubifsmount ubi:rootfs;\0"  
\
"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"\
"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" 
\
"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
-- 
2.1.4

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[U-Boot] [PATCH 04/10] am335x: configs: Fix usb ether boot support

2016-03-09 Thread Lokesh Vutla
CONFIG_SPL_NET_VCI_STRING is available only with BOOTP. So if
CMD_DHCP is enabled for SPL in usb ether boot, it will not pass
the right vendor name and failing to download the right file.
Also all the net CMD_* are not required in SPL builds. So defining
these only for non-SPL builds.

Reported-by: Yan Liu 
Signed-off-by: Lokesh Vutla 
Reviewed-by: Sekhar Nori 
---
 include/configs/ti_am335x_common.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/ti_am335x_common.h 
b/include/configs/ti_am335x_common.h
index edbd820..4535b8c 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -28,6 +28,7 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK 4800
 
+#ifndef CONFIG_SPL_BUILD
 /* Network defines. */
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -38,9 +39,10 @@
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT 10
 #define CONFIG_CMD_PING
-#define CONFIG_DRIVER_TI_CPSW  /* Driver for IP block */
 #define CONFIG_MII /* Required in net/eth.c */
+#endif
 
+#define CONFIG_DRIVER_TI_CPSW  /* Driver for IP block */
 /*
  * RTC related defines. To use bootcount you must set bootlimit in the
  * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
-- 
2.1.4

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[U-Boot] [PATCH 05/10] am43xx: configs: Enable USB commands for non usb boot also

2016-03-09 Thread Lokesh Vutla
From: Mugunthan V N 

With commit aee119bd70b8 ('am43xx_evm: add usb host boot support') usb
commands is removed from U-boot second stage and enbaled only on USB
boot config. Fixing this by enable USB commands for both USB boot and
in second stage u-boot.

Signed-off-by: Mugunthan V N 
Signed-off-by: Lokesh Vutla 
---
 include/configs/am43xx_evm.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 1428aa9..0a96bd3 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -105,8 +105,10 @@
 /* SPL USB Support */
 #ifdef CONFIG_SPL_USB_HOST_SUPPORT
 #define CONFIG_SPL_USB_SUPPORT
-#define CONFIG_SYS_USB_FAT_BOOT_PARTITION  1
+#endif
 
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION  1
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
-- 
2.1.4

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[U-Boot] [PATCH 07/10] k2g: env: Allow use of a script and plain text env files

2016-03-09 Thread Lokesh Vutla
For development purposes, it is easier to use the env import command
and plain text or script files instead of script-images. So allow
u-boot to load env var from a text file or a script file.

Signed-off-by: Lokesh Vutla 
---
 include/configs/k2g_evm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index ca1e368..ba084c1 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -36,6 +36,7 @@
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
 
 #define CONFIG_BOOTCOMMAND \
+   "run envboot; " \
"run set_name_pmmc init_${boot} get_pmmc_${boot} run_pmmc " \
"get_fdt_${boot} get_mon_${boot} get_kern_${boot} " \
"run_mon run_kern"
-- 
2.1.4

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[U-Boot] [PATCH 09/10] keystone2: env: add env script for booting with an initramfs with firmware

2016-03-09 Thread Lokesh Vutla
From: Murali Karicheri 

This patch updates the env script to include a initramfs with firmware
loaded and provided to kernel through second argument of bootz command
during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the
required env variables and use it in evm specific config file.

The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes
firmwares. These requires firmware to be available early through the boot
process in some cases to satisfy firmware requests from driver. Hence use
a small initramfs to provide the same and update boot env to accommodate
this in the boot flow. This method is used when rootfs is nfs and ubifs.
This fs contains just lib/firmware folder with all required firmware.

When rootfs is on initramfs, then the filesystem has the firmware under
lib/firmware and this early initramfs is not required and is not used.

Signed-off-by: Murali Karicheri 
Signed-off-by: Lokesh Vutla 
---
 include/configs/k2e_evm.h|  1 +
 include/configs/k2g_evm.h|  2 ++
 include/configs/k2hk_evm.h   |  1 +
 include/configs/k2l_evm.h|  1 +
 include/configs/ti_armv7_keystone2.h | 15 ---
 5 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index e053a54..daf37f6 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -16,6 +16,7 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+   DEFAULT_FW_INITRAMFS_BOOT_ENV   \
"addr_mon=0x0c14\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 2c70df1..2e47763 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -21,6 +21,7 @@
"console=ttyS0,115200n8\0"  \
"bootpart=0:2\0"\
"bootdir=/boot\0"   \
+   "rd_spec=-\0"   \
"addr_mon=0x0c04\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
@@ -34,6 +35,7 @@
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "\
"${bootdir}/${name_kern}\0" \
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
+   "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
 
 #define CONFIG_BOOTCOMMAND \
"run envboot; " \
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 3cd2a85..a031ae4 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -16,6 +16,7 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+   DEFAULT_FW_INITRAMFS_BOOT_ENV   \
"addr_mon=0x0c5f\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 9bacfa4..829daa2 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -16,6 +16,7 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
+   DEFAULT_FW_INITRAMFS_BOOT_ENV   \
"addr_mon=0x0c14\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"   \
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index e1effc0..9ea6392 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -224,6 +224,15 @@
 /* EDMA3 */
 #define CONFIG_TI_EDMA3
 
+#define DEFAULT_FW_INITRAMFS_BOOT_ENV  \
+   "name_fw_rd=k2-fw-initrd.cpio.gz\0" \
+   "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"\
+   "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; "\
+   "run set_rd_spec\0" \
+   "init_fw_rd_ramfs=setenv rd_spec -\0"   \
+   "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \
+   "run set_rd_spec\0"  

[U-Boot] [PATCH 10/10] keystone2: env: Set mmc as default boot for k2g-evm

2016-03-09 Thread Lokesh Vutla
From: Yan Liu 

For k2l, k2e and k2hk, ubi is set to default boot in uboot
environment settings; while for k2g, mmc should be the
default boot. This patch is to set mmc as default for k2g-evm

Signed-off-by: Yan Liu 
Signed-off-by: Lokesh Vutla 
---
 include/configs/k2e_evm.h| 1 +
 include/configs/k2g_evm.h| 1 +
 include/configs/k2hk_evm.h   | 1 +
 include/configs/k2l_evm.h| 1 +
 include/configs/ti_armv7_keystone2.h | 1 -
 5 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index daf37f6..07f975b 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -17,6 +17,7 @@
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_FW_INITRAMFS_BOOT_ENV   \
+   "boot=ubi\0"\
"addr_mon=0x0c14\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 2e47763..7bc506f 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -18,6 +18,7 @@
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_MMC_TI_ARGS \
DEFAULT_PMMC_BOOT_ENV   \
+   "boot=mmc\0"\
"console=ttyS0,115200n8\0"  \
"bootpart=0:2\0"\
"bootdir=/boot\0"   \
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index a031ae4..a268a86 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -17,6 +17,7 @@
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_FW_INITRAMFS_BOOT_ENV   \
+   "boot=ubi\0"\
"addr_mon=0x0c5f\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 829daa2..f366e67 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -17,6 +17,7 @@
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_FW_INITRAMFS_BOOT_ENV   \
+   "boot=ubi\0"\
"addr_mon=0x0c14\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"   \
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 9ea6392..f8193c2 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -248,7 +248,6 @@
 #define CONFIG_EXTRA_ENV_SETTINGS  \
DEFAULT_LINUX_BOOT_ENV  \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
-   "boot=ubi\0"\
"bootdir=/boot\0" \
"tftp_root=/\0" \
"nfs_root=/export\0"\
-- 
2.1.4

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[U-Boot] [PATCH 08/10] k2g: configs: Add support to save env in MMC

2016-03-09 Thread Lokesh Vutla
Adding support to save env in MMC on k2g platforms, as it is the
preferred peripheral in saving env.

Signed-off-by: Lokesh Vutla 
---
 include/configs/k2g_evm.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index ba084c1..2c70df1 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -61,6 +61,12 @@
 #define CONFIG_OMAP_HSMMC
 #define CONFIG_CMD_MMC
 
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE  "mmc"
+#define FAT_ENV_DEVICE_AND_PART"0:1"
+#define FAT_ENV_FILE   "uboot.env"
+
 #define CONFIG_SF_DEFAULT_BUS  1
 #define CONFIG_SF_DEFAULT_CS   0
 
-- 
2.1.4

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[U-Boot] [PATCH] MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y

2016-03-09 Thread Daniel Schwierzeck
MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
with EB-only toolchains like the one from kernel.org. If one do
not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:

/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
 compiled for a big endian system and target is little endian
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
 endianness incompatible with that of the selected emulation
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target 
specific data of file 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
 compiled for a big endian system and target is little endian
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
 endianness incompatible with that of the selected emulation
/opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target 
specific data of file 
/opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
/work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed

One example for a failing build is Travis CI.

Signed-off-by: Daniel Schwierzeck 

---

 configs/pic32mzdask_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 169a2ac..4017983 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -29,6 +29,6 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
-- 
2.5.0

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Re: [U-Boot] [PATCH 0/6] arm: am57xx: Add Fastboot support to AM57XX EVM

2016-03-09 Thread Sam Protsenko
On Tue, Mar 8, 2016 at 10:06 PM, Tom Rini  wrote:
> I think this series shows that we really need someone to step up and
> spend time converting the environment options to Kconfig so that
> different applications of the same board can easily tweak things they
> need (ie save env on the eMMC that you're programming vs keep env as a
> FAT file on the SD card users are often using).
>

Right now I have some stuff going on I'm more concerned about. I can
look into moving options (at least ones that we are using for TI
platforms) to Kconfig, once I finished with current task. It seems
like a right thing to do. But I'd really like current patches to be
merged as is for now.
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Re: [U-Boot] [PATCH] MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y

2016-03-09 Thread Purna Chandra Mandal
On 03/09/2016 04:00 PM, Daniel Schwierzeck wrote:

> MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
> with EB-only toolchains like the one from kernel.org. If one do
> not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:
>
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
>  compiled for a big endian system and target is little endian
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o):
>  endianness incompatible with that of the selected emulation
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge 
> target specific data of file 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
>  compiled for a big endian system and target is little endian
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o):
>  endianness incompatible with that of the selected emulation
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge 
> target specific data of file 
> /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
> /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed
>
> One example for a failing build is Travis CI.
>
> Signed-off-by: Daniel Schwierzeck 

Reviewed-by: Purna Chandra Mandal 

> ---
>
>  configs/pic32mzdask_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
> index 169a2ac..4017983 100644
> --- a/configs/pic32mzdask_defconfig
> +++ b/configs/pic32mzdask_defconfig
> @@ -29,6 +29,6 @@ CONFIG_DM_ETH=y
>  CONFIG_PIC32_ETH=y
>  CONFIG_PINCTRL=y
>  # CONFIG_PINCTRL_FULL is not set
> -CONFIG_SYS_VSNPRINTF=y
> +CONFIG_USE_PRIVATE_LIBGCC=y
>  CONFIG_USE_TINY_PRINTF=y
>  CONFIG_CMD_DHRYSTONE=y

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Re: [U-Boot] [PATCH 6/6] arm: am57xx: Keep environment in eMMC

2016-03-09 Thread Sam Protsenko
On Tue, Mar 8, 2016 at 6:42 PM, Lokesh Vutla  wrote:
> Any specific reason why you want this change?
>

Yes, I'm thinking about use case when developer uses eMMC exclusively
(no SD card). In that case the environment should be stored somewhere,
and that should be eMMC. In other words, once eMMC support is fully
available in U-Boot, we can think more about eMMC use-case, because
developers usually prefer to work with eMMC. Also see how it's done in
DRA7 config, for example. And in SD card use case we can still work
with environment stored in eMMC. Seems like win-win to me.
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[U-Boot] [GIT PULL] u-boot-mips/master

2016-03-09 Thread Daniel Schwierzeck
Hi Tom,

two fixes for MIPS:
- fix a build error on Travis CI for pic32mzdask board
- fix cache op for toolchains not supporting __builtin_mips_cache()

please consider pulling, thanks


The following changes since commit deff6fb3a7790e93264292982000275e78bb12e5:

  malloc: remove !gd handling (2016-03-08 15:01:47 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

for you to fetch changes up to 40a09be2e925e6e4b56a236fec5aed2c002e9d6f:

  MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y (2016-03-09 11:54:01 +0100)


Daniel Schwierzeck (1):
  MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y

Matthias Schiffer (1):
  MIPS: fix mips_cache fallback without __builtin_mips_cache

 arch/mips/include/asm/cacheops.h | 2 +-
 configs/pic32mzdask_defconfig| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
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Re: [U-Boot] Newbie SPL question for socfpga_sockit

2016-03-09 Thread Marek Vasut
On 03/09/2016 02:42 AM, Phil Reid wrote:
> G'day George,
> 
> On 3/03/2016 10:57 PM, George Broz wrote:
>> On 2 March 2016 at 23:11, Phil Reid  wrote:
>>> On 3/03/2016 2:49 PM, George Broz wrote:

 On 1 March 2016 at 19:49, Phil Reid  wrote:
>
> On 2/03/2016 10:40 AM, George Broz wrote:
>
>> Sorry for the delayed response - got called away, but am back to this
>> now. I patched
>> socfpga_common.h and re-built the project. I picked up
>> spl/u-boot-spl-dtb.sfp and
>> u-boot-dtb.img and transferred them to the SD card with:
>>
>> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0
>> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4
>>
>> Tried this with both the original DT set (socfpga.dtsi,
>> socfpga_cyclone.dtsi,
>> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01
>> download
>> and
>> also an Altera-patched DT set that I've used to boot into Linux
>> numerous
>> times.
>>
>> When I start up the board I get:
>>
>> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM calibration failed.
>> ### ERROR ### Please RESET the board ###
>>
>> I'm not a Quartus user, so I haven't done anything with the
>> qts-filter.sh script you
>> mentioned. Do I need to? I don't have any custom FPGA logic - it's
>> just the Terasic
>> board out of the box.
>>
>> Thanks for any help!
>>
>
> Even without the custom FPGA logic the files generated from
> qts-filter.sh
> need to match your board.
> Sets up PLL and SDRAM parameters.
> I'm not familiar with the Terasic dev board ( I do have the altera
> devkit,
> but haven't used it for awhile).
> I'd hope the files in the git repo are correct for your board.
> Without the corresponding qsys project it's hard to be sure.
>
 Hi Phil,

 So as my next attempt, there was a Quartus/Qsys example that came
 with the Terasic board (specific to my Rev. of the board).

 * I took the contents of the 'handoff folder', .sof, and .sopcinfo
 file.
 * launched an "Embedded Command Shell" from EDS 15.0 and then the BSP
 editor GUI
 * pointed the BSP editor to the "handoff folder", and hit "Generate"
 to produce iocsr, pinmux, pll, etc. files
 * applied qts-filter.sh to these files, the output of which I then
 dropped into the u-boot source @ ../board/terasic/sockit/qts
 * rebuilt uboot spl & image, but got a similar result:

 U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31)
 drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
 drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
 drivers/ddr/altera/sequencer.c: Calibration complete
 SDRAM calibration failed.
 ### ERROR ### Please RESET the board ###

 Except now it repeats four times, whereas before it only printed out
 once.

 It that essentially the correct procedure? Is it now a matter of
 looking through
 the include files that where generated by qts-filter.sh to find a
 setting that is "off"?

 (BTW - my first attempt was to use EDS 13.0, but that resulted in
 several undefined macros when it
 came time to compile u-boot with the qts-filter-generated code. How
 does one know which tool version to use?)

>>>
>>> What does a diff of the new files show compared to the ones in uboot.
>>
>> Here's two of them...
>>
>> ---
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig
>>
>> +++
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h
>>
>>
>> @@ -33,10 +33,10 @@
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
>>
>> @@ -46,12 +46,12 @@
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3

Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Marek Vasut
On 03/09/2016 12:22 PM, Rajat Srivastava wrote:
> This patch adds a new 'usb regress' command, that can be used to
> regress test a USB device. It performs the following operations:
> 
> 1. starts the USB device
> 2. performs read/write operations
> 3. stops the USB device
> 4. verifies the contents of read/write operations
> 
> Sample Output:
> => usb regress 8100 8200 32m
> regressing USB..
> starting USB...
> USB0:   Register 200017f NbrPorts 2
> Starting the controller
> USB XHCI 1.00
> scanning bus 0 for devices... 2 USB Device(s) found
>scanning usb for storage devices... 1 Storage Device(s) found
> USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
> USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
> stopping USB..
> verifying data on addresses 0x8100 and 0x8200
> Total of 65536 word(s) were the same
> 
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Rajesh Bhagat 


Does it do anything which cannot be achieved on the command line itself
using "usb reset" "usb write" "usb read" "cmp" commands ?

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Re: [U-Boot] [PATCH v2] arm: imx: Add support for GE Bx50v3 boards

2016-03-09 Thread Stefano Babic
On 29/01/2016 21:16, Akshay Bhat wrote:
> Add support for GE B450v3, B650v3 and B850v3 boards. The boards
> are based on Advantech BA16 module which has a i.MX6D processor.
> The boards support:
>  - FEC Ethernet
>  - USB Ports
>  - SDHC and MMC boot
>  - SPI NOR
>  - LVDS and HDMI display
> 
> Basic information about the module:
>  - Module manufacturer: Advantech
>  - CPU: Freescale ARM Cortex-A9 i.MX6D
>  - SPECS:
>  Up to 2GB Onboard DDR3 Memory;
>  Up to 16GB Onboard eMMC NAND Flash
>  Supports OpenGL ES 2.0 and OpenVG 1.1
>  HDMI, 24-bit LVDS
>  1x UART, 2x I2C, 8x GPIO,
>  4x Host USB 2.0 port, 1x USB OTG port,
>  1x micro SD (SDHC),1x SDIO, 1x SATA II,
>  1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
> 
> Signed-off-by: Akshay Bhat 
> ---

Applied to -next, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 1/2] mx7_common: Remove unexisting options

2016-03-09 Thread Stefano Babic
On 22/02/2016 22:41, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> CONFIG_IMX_FIXED_IVT_OFFSET and CONFIG_FSL_CLK are not used
> anywhere, so just remove them.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  include/configs/mx7_common.h | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
> index fac7c3f..b2a8756 100644
> --- a/include/configs/mx7_common.h
> +++ b/include/configs/mx7_common.h
> @@ -27,7 +27,6 @@
>  
>  /* Enable iomux-lpsr support */
>  #define CONFIG_IOMUX_LPSR
> -#define CONFIG_IMX_FIXED_IVT_OFFSET
>  
>  /* Size of malloc() pool */
>  #define CONFIG_SYS_MALLOC_LEN   (32 * SZ_1M)
> @@ -38,8 +37,6 @@
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> -#define CONFIG_FSL_CLK
> -
>  #define CONFIG_LOADADDR 0x8080
>  #define CONFIG_SYS_TEXT_BASE0x8780
>  
> 

Applied to -next, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 2/2] mx7dsabresd: Define serial port locally

2016-03-09 Thread Stefano Babic
On 22/02/2016 22:41, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> CONFIG_MXC_UART_BASE should not be defined in mx7_common.h as
> the console port can vary from board to board.
> 
> Define CONFIG_MXC_UART_BASE locally instead.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  include/configs/mx7_common.h  | 1 -
>  include/configs/mx7dsabresd.h | 2 ++
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
> index b2a8756..bfad696 100644
> --- a/include/configs/mx7_common.h
> +++ b/include/configs/mx7_common.h
> @@ -77,7 +77,6 @@
>  
>  /* UART */
>  #define CONFIG_MXC_UART
> -#define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR
>  
>  /* MMC */
>  #define CONFIG_MMC
> diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
> index 2c981e0..b8b5b45 100644
> --- a/include/configs/mx7dsabresd.h
> +++ b/include/configs/mx7dsabresd.h
> @@ -14,6 +14,8 @@
>  #define CONFIG_DBG_MONITOR
>  #define PHYS_SDRAM_SIZE  SZ_1G
>  
> +#define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR
> +
>  /* Uncomment to enable secure boot support */
>  /* #define CONFIG_SECURE_BOOT */
>  #define CONFIG_CSF_SIZE  0x4000
> 
Applied to -next, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 2/3] imx: mx6ul_evk: default enable device tree support

2016-03-09 Thread Fabio Estevam
Hi Peng,

On Wed, Mar 9, 2016 at 3:01 AM, Peng Fan  wrote:
> Default enable device tree for mx6ul_14x14_evk and
> mx6ul_9x9_evk board. And sort the defconfig file to be in
> alphabet order.
>
> Enable pinctrl driver for the two boards.
>
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 

Shouldn't board/freescale/mx6ul_14x14_evk/README be updated to take
into account the new new method for flashing the image?
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Re: [U-Boot] [PATCH] mx7: Distinguish between dual and solo versions

2016-03-09 Thread Stefano Babic
On 28/02/2016 16:33, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> Read the number of cores in the fuses to distinguish between
> the dual and solo versions.
> 
> Tested on a mx7d sabresd and on a mx7solo warp7.
> 
> Signed-off-by: Fabio Estevam 
> ---

Applied to -next, thanks !

Best regards,
Stefano Babic

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[U-Boot] [PATCH] ARM: DRA7: DDR: Enable SR in Power Management Control

2016-03-09 Thread Lokesh Vutla
From: Nishanth Menon 

If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 arch/arm/include/asm/emif.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 3183130..b00dece 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -914,8 +914,8 @@ struct dmm_lisa_map_regs {
 
 /* Maximum delay before Low Power Modes */
 #define REG_CS_TIM 0x0
-#define REG_SR_TIM 0x0
-#define REG_PD_TIM 0x0
+#define REG_SR_TIM 0xF
+#define REG_PD_TIM 0xF
 
 
 /* EMIF_PWR_MGMT_CTRL register */
@@ -923,7 +923,7 @@ struct dmm_lisa_map_regs {
((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-   ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
+   ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
& EMIF_REG_LP_MODE_MASK) |\
((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
& EMIF_REG_DPD_EN_MASK))\
-- 
2.1.4

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Re: [U-Boot] [PATCH 0/6] arm: am57xx: Add Fastboot support to AM57XX EVM

2016-03-09 Thread Tom Rini
On Wed, Mar 09, 2016 at 05:35:21PM +0700, Sam Protsenko wrote:
> On Tue, Mar 8, 2016 at 10:06 PM, Tom Rini  wrote:
> > I think this series shows that we really need someone to step up and
> > spend time converting the environment options to Kconfig so that
> > different applications of the same board can easily tweak things they
> > need (ie save env on the eMMC that you're programming vs keep env as a
> > FAT file on the SD card users are often using).
> >
> 
> Right now I have some stuff going on I'm more concerned about. I can
> look into moving options (at least ones that we are using for TI
> platforms) to Kconfig, once I finished with current task. It seems
> like a right thing to do. But I'd really like current patches to be
> merged as is for now.

No, we can't merge them as-is for now as moving the environment to eMMC
by default breaks another of other use cases, so we need to move things
to Kconfig here.

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Re: [U-Boot] [PATCH 6/6] arm: am57xx: Keep environment in eMMC

2016-03-09 Thread Tom Rini
On Wed, Mar 09, 2016 at 05:46:49PM +0700, Sam Protsenko wrote:
> On Tue, Mar 8, 2016 at 6:42 PM, Lokesh Vutla  wrote:
> > Any specific reason why you want this change?
> >
> 
> Yes, I'm thinking about use case when developer uses eMMC exclusively
> (no SD card). In that case the environment should be stored somewhere,
> and that should be eMMC. In other words, once eMMC support is fully
> available in U-Boot, we can think more about eMMC use-case, because
> developers usually prefer to work with eMMC. Also see how it's done in
> DRA7 config, for example. And in SD card use case we can still work
> with environment stored in eMMC. Seems like win-win to me.

Except the DRA7 boards don't also support a community board like am57xx
does, the Beagle x15.  That's a big SD heavy use-case.

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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Hans de Goede

Hi,

On 09-03-16 12:28, Marek Vasut wrote:

On 03/09/2016 12:22 PM, Rajat Srivastava wrote:

This patch adds a new 'usb regress' command, that can be used to
regress test a USB device. It performs the following operations:

1. starts the USB device
2. performs read/write operations
3. stops the USB device
4. verifies the contents of read/write operations

Sample Output:
=> usb regress 8100 8200 32m
regressing USB..
starting USB...
USB0:   Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
stopping USB..
verifying data on addresses 0x8100 and 0x8200
Total of 65536 word(s) were the same

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 



Does it do anything which cannot be achieved on the command line itself
using "usb reset" "usb write" "usb read" "cmp" commands ?


This seems to be about a reading / writing a usb-disk / usb-storage device.
I believe this can certainly be achieved with the existing disk io commands,
and moreover this seems quite dangerous (overwriting the partition table on
the device), so I think requiring the user to do this explicitly indeed
seems better.

Regards,

Hans
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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Marek Vasut
On 03/09/2016 01:33 PM, Rajesh Bhagat wrote:
> 
> 
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Wednesday, March 09, 2016 4:59 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de
>> Cc: s...@chromium.org; Rajesh Bhagat 
>> Subject: Re: [PATCH] usb: Add new command to regress USB devices
>>
>> On 03/09/2016 12:22 PM, Rajat Srivastava wrote:
>>> This patch adds a new 'usb regress' command, that can be used to
>>> regress test a USB device. It performs the following operations:
>>>
>>> 1. starts the USB device
>>> 2. performs read/write operations
>>> 3. stops the USB device
>>> 4. verifies the contents of read/write operations
>>>
>>> Sample Output:
>>> => usb regress 8100 8200 32m
>>> regressing USB..
>>> starting USB...
>>> USB0:   Register 200017f NbrPorts 2
>>> Starting the controller
>>> USB XHCI 1.00
>>> scanning bus 0 for devices... 2 USB Device(s) found
>>>scanning usb for storage devices... 1 Storage Device(s) found
>>> USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
>>> USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
>>> stopping USB..
>>> verifying data on addresses 0x8100 and 0x8200 Total of 65536
>>> word(s) were the same
>>>
>>> Signed-off-by: Rajat Srivastava 
>>> Signed-off-by: Rajesh Bhagat 
>>
>>
>> Does it do anything which cannot be achieved on the command line itself 
>> using "usb
>> reset" "usb write" "usb read" "cmp" commands ?
>>
> 
> Let me share little background and motivation for addition of this command: 
> 
> 1. We need to test different make(from different vendors/model) USB devices 
> to test USB hardware. Where we 
> generally face below issues: 
>a. USB devices enumeration failure on Nth iteration.
>b. USB read/write failure (incomplete transfer or data corruption) for 
> particular data size e.g. 12M.
> 2. "usb regress" command takes size/iterations and performs all above 
> operations in single command to reduce 
> manual overhead.
> + "usb regress waddr raddr size [iterations] - regress a USB device\n"
> + "(starts, writes to waddr, reads from raddr, stops and verifies.\n"
> + "`size' format 1B/1K/1M/1G)\n "
> 3. We are planning to provide a patch over it to provide summary report as 
> below:
> Regress Report: 
> USB enumerate: OK/ERROR (2/20)
> USB write: OK/ERROR (2/20)
> USB read: OK/ERROR (2/20)
> USB verify: OK/ERROR (2/20)
> Above report can be useful to regress a USB devices, and detailed report need 
> to referred only when anything fails. 
> 
> Please provide your opinion on the same. 

Did you measure the overhead ? I believe the overhead of implementing
this in shell is significantly lower than the overhead of the USB and
the USB stack itself, so discussing any overhead concerns here is moot.

Yet still, I cannot find a definitive answer to my question whether this
can be implemented by pure u-boot shell commands, but I think
it can be done that way. So why should I accept this patch over
something like:

while true ; do \
 usb reset & usb write .. && usb read ... && cmp ... && echo OK ; \
done

?
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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Marek Vasut
On 03/09/2016 01:21 PM, Hans de Goede wrote:
> Hi,
> 
> On 09-03-16 12:28, Marek Vasut wrote:
>> On 03/09/2016 12:22 PM, Rajat Srivastava wrote:
>>> This patch adds a new 'usb regress' command, that can be used to
>>> regress test a USB device. It performs the following operations:
>>>
>>> 1. starts the USB device
>>> 2. performs read/write operations
>>> 3. stops the USB device
>>> 4. verifies the contents of read/write operations
>>>
>>> Sample Output:
>>> => usb regress 8100 8200 32m
>>> regressing USB..
>>> starting USB...
>>> USB0:   Register 200017f NbrPorts 2
>>> Starting the controller
>>> USB XHCI 1.00
>>> scanning bus 0 for devices... 2 USB Device(s) found
>>> scanning usb for storage devices... 1 Storage Device(s) found
>>> USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
>>> USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
>>> stopping USB..
>>> verifying data on addresses 0x8100 and 0x8200
>>> Total of 65536 word(s) were the same
>>>
>>> Signed-off-by: Rajat Srivastava 
>>> Signed-off-by: Rajesh Bhagat 
>>
>>
>> Does it do anything which cannot be achieved on the command line itself
>> using "usb reset" "usb write" "usb read" "cmp" commands ?
> 
> This seems to be about a reading / writing a usb-disk / usb-storage device.

That's what usb read / usb write commands are for, reading raw data from
USB disk :-)

> I believe this can certainly be achieved with the existing disk io
> commands,
> and moreover this seems quite dangerous (overwriting the partition table on
> the device), so I think requiring the user to do this explicitly indeed
> seems better.

Yeah

> Regards,
> 
> Hans


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[U-Boot] hab_status & CONFIG_SECURE_BOOT - query

2016-03-09 Thread C Supriya
Hello Team , 

Am using u-boot 2015.07 version downloaded from git
I have two queries

1. Which is the file to enable secure boot config in this version for imx6q 
SabreSD board ? (CONFIG_SECURE_BOOT)
2. When I give the u-boot command 'hab_status' in u-boot prompt, am getting 
"Unknown command 'hab_status' - try 'help'"

Please let me know the solution for both.
-Supriya
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[U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Rajat Srivastava
This patch adds a new 'usb regress' command, that can be used to
regress test a USB device. It performs the following operations:

1. starts the USB device
2. performs read/write operations
3. stops the USB device
4. verifies the contents of read/write operations

Sample Output:
=> usb regress 8100 8200 32m
regressing USB..
starting USB...
USB0:   Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
   scanning usb for storage devices... 1 Storage Device(s) found
USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
stopping USB..
verifying data on addresses 0x8100 and 0x8200
Total of 65536 word(s) were the same

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 common/cmd_usb.c | 174 ++-
 1 file changed, 173 insertions(+), 1 deletion(-)

diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index a540b42..25fdeab 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_USB_STORAGE
 static int usb_stor_curr_dev = -1; /* current device */
@@ -616,6 +617,167 @@ static int usb_device_info(void)
 }
 #endif
 
+static unsigned long calc_blockcount(char * const size)
+{
+   unsigned long value, multiplier;
+   int size_len = strlen(size);
+   char unit;
+
+   /* extract the unit of size passed */
+   unit = size[size_len - 1];
+   /* updating the source string to remove unit */
+   size[size_len - 1] = '\0';
+
+   value = simple_strtoul(size, NULL, 10);
+   if (value <= 0) {
+   printf("invalid size\n");
+   return 0;
+   }
+
+   if (unit == 'G' || unit == 'g') {
+   multiplier = 2 * 1024 * 1024;
+   } else if (unit == 'M' || unit == 'm') {
+   multiplier = 2 * 1024;
+   } else if (unit == 'K' || unit == 'k') {
+   multiplier = 2;
+   } else if (unit == 'B' || unit == 'b') {
+   if (value % 512 != 0) {
+   printf("size can only be multiples of 512 bytes\n");
+   return 0;
+   }
+   multiplier = 1;
+   value /= 512;
+   } else {
+   printf("syntax mismatch\n");
+   return 0;
+   }
+
+   return value * multiplier;
+}
+
+static int usb_read_write_verify(unsigned long w_addr, unsigned long r_addr,
+   unsigned long cnt)
+{
+   cmd_tbl_t *c;
+   char str[3][16];
+   char *ptr[4] = { "cmp", str[0], str[1], str[2] };
+
+   c = find_cmd("cmp");
+   if (!c) {
+   printf("compare command not found\n");
+   return -1;
+   }
+   printf("verifying data on addresses 0x%lx and 0x%lx\n", w_addr, r_addr);
+   sprintf(str[0], "%lx", w_addr);
+   sprintf(str[1], "%lx", r_addr);
+   sprintf(str[2], "%lx", cnt);
+   (c->cmd)(c, 0, 4, ptr);
+   return 0;
+}
+
+
+static int do_usb_regress(int argc, char * const argv[])
+{
+   unsigned long loopcount, iteration;
+   unsigned long w_addr, r_addr, cnt, n;
+   unsigned long blk = 0;
+   extern char usb_started;
+
+#ifdef CONFIG_USB_STORAGE
+   block_dev_desc_t *stor_dev;
+#endif
+
+   if (argc < 5 || argc > 6) {
+   printf("syntax mismatch\n");
+   return -1;
+   }
+
+   if (argc == 5)
+   loopcount = 1;
+   else
+   loopcount = simple_strtoul(argv[5], NULL, 10);
+
+   if (loopcount <= 0) {
+   printf("syntax mismatch\n");
+   return -1;
+   }
+
+   cnt = calc_blockcount(argv[4]);
+   if (cnt == 0)
+   return -1;
+
+   iteration = loopcount;
+   while (loopcount--) {
+   if (argc > 5)
+   printf("\niteration #%lu\n\n", iteration - loopcount);
+
+   /* start USB */
+   if (usb_started) {
+   printf("USB already started\n");
+   } else {
+   printf("starting USB...\n");
+   do_usb_start();
+   }
+   if (!usb_started) {
+   printf("USB did not start\n");
+   return -1;
+   }
+   if (usb_stor_curr_dev < 0) {
+   printf("no current device selected\nstopping USB...\n");
+   usb_stop();
+   return -1;
+   }
+
+#ifdef CONFIG_USB_STORAGE
+   /* write on USB from address (w_addr) of RAM */
+   w_addr = simple_strtoul(argv[2], NULL, 16);
+   printf("USB write: device %d block # %ld, count %ld ... ",
+  usb_stor_curr_dev, blk, cnt);
+   stor_dev = usb

Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-09 Thread Marek Vasut
On 03/09/2016 10:22 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
> 
>> However there is still no ping in U-Boot.
>> After power reset I did:
>>
>>> # bridge disable
>>> # fpga load 0  
>>> # bridge enable
>>
>>> # md 0xff706000 1
>> ff706000: 0074  <-- this means fpga is in user mode
>>
>>> # setenv ethaddr ...
>>> # setenv ipaddr ...
>>> # setenv netmask ...
>>> # setenv gatewayip ...
>>
>> => ping 192.168.1.126
>> Speed: 100, full duplex
>> Using ethernet@ff702000 device
>> ping failed; host 192.168.1.126 is not alive
>>
>> With similar commands on previous U-Boot version I had ping.
> 
> Also using wireshark I found that board sends correct ARP packets to PC.
> PC in it's turn send valid ARP response to the board.
> But for some reason ARP reply is not handled by the board.
> And board doesn't send ICMP packets to the PC.
> 
> I already checked ip addresses, they should be fine.
> Also the same IP works fine for previous U-Boot version (2013).
> 
> What could be the reason for that?

Perform usual test, disable cache (dcache off) .

And please CC the usual lineup, Chin and Dinh ;-)

-- 
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Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-09 Thread Bakhvalov, Denis (Nokia - PL/Wroclaw)
Hi Marek,

> Perform usual test, disable cache (dcache off) .

I tried and result is still the same.

UPD: I did a little trick:
1. I started ping from the board side. That made the board listen to incoming 
packets (calling in infinite loop eth_rx() ).
2. Started ping from PC side.
3. In this case board receive ICMP packets from PC:

packet received
Receive from protocol 0x800
Got IP
len=60, v=45
Got ICMP ECHO REQUEST, return 74 bytes 

So, ICMP packets are handled by the board, but ARP packets not.

In my understanding it tells me that at least interface on the board side is 
alive.

I'm now doing some low-level debugging, however I think this is not the best 
idea. :)
Now dw_eth_recv (designware.c) always returns 0 length of the packet.

Best regards,
Denis Bakhvalov
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[U-Boot] Eeprom Configuration

2016-03-09 Thread Guy Thouret
Hello u-boot,

I'm defining a new board config and have some observations about eeprom 
configuration I hope someone could clarify for me.

There appear to be two conflicting config options:
CONFIG_I2C_ENV_EEPROM_BUS and CONFIG_SYS_I2C_EEPROM_BUS

What are the purpose of these two options?  Could we do without 
CONFIG_I2C_ENV_EEPROM_BUS and just use CONFIG_SYS_I2C_EEPROM_BUS?

An include for the TI SoC I am using defines CONFIG_SPI, when this is defined 
the following code sets CONFIG_SYS_DEF_EEPROM_ADDR to 0.  
CONFIG_SYS_DEF_EEPROM_ADDR is used in common/env_eeprom.c as the i2c address to 
read the environment from so with CONFIG_SPI set one can not use an eeprom for 
the u-boot environment.

include/common.h:475
#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
# define CONFIG_SYS_DEF_EEPROM_ADDR 0
#else
#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
#endif
#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */

If I accidentally define CONFIG_ENV_EEPROM_IS_ON_I2C likewise, 
CONFIG_SYS_DEF_EEPROM_ADDR remains unset and the environment is not read.

It would seem logical to define that as my environment eeprom is indeed on an 
eeprom so I'm not sure why that config option exists.

Thanks,
Guy Thouret
Guy Thouret

Senior Software Engineer

t: 0161 4751777 Ext.244 |  m:  |  dd: |  f: 0161 4751778  |  w: 
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Linkedin  |  Follow WEMS on 
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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Rajesh Bhagat


> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, March 09, 2016 4:59 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de
> Cc: s...@chromium.org; Rajesh Bhagat 
> Subject: Re: [PATCH] usb: Add new command to regress USB devices
> 
> On 03/09/2016 12:22 PM, Rajat Srivastava wrote:
> > This patch adds a new 'usb regress' command, that can be used to
> > regress test a USB device. It performs the following operations:
> >
> > 1. starts the USB device
> > 2. performs read/write operations
> > 3. stops the USB device
> > 4. verifies the contents of read/write operations
> >
> > Sample Output:
> > => usb regress 8100 8200 32m
> > regressing USB..
> > starting USB...
> > USB0:   Register 200017f NbrPorts 2
> > Starting the controller
> > USB XHCI 1.00
> > scanning bus 0 for devices... 2 USB Device(s) found
> >scanning usb for storage devices... 1 Storage Device(s) found
> > USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
> > USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
> > stopping USB..
> > verifying data on addresses 0x8100 and 0x8200 Total of 65536
> > word(s) were the same
> >
> > Signed-off-by: Rajat Srivastava 
> > Signed-off-by: Rajesh Bhagat 
> 
> 
> Does it do anything which cannot be achieved on the command line itself using 
> "usb
> reset" "usb write" "usb read" "cmp" commands ?
> 

Let me share little background and motivation for addition of this command: 

1. We need to test different make(from different vendors/model) USB devices to 
test USB hardware. Where we 
generally face below issues: 
   a. USB devices enumeration failure on Nth iteration.
   b. USB read/write failure (incomplete transfer or data corruption) for 
particular data size e.g. 12M.
2. "usb regress" command takes size/iterations and performs all above 
operations in single command to reduce 
manual overhead.
+   "usb regress waddr raddr size [iterations] - regress a USB device\n"
+   "(starts, writes to waddr, reads from raddr, stops and verifies.\n"
+   "`size' format 1B/1K/1M/1G)\n "
3. We are planning to provide a patch over it to provide summary report as 
below:
Regress Report: 
USB enumerate: OK/ERROR (2/20)
USB write: OK/ERROR (2/20)
USB read: OK/ERROR (2/20)
USB verify: OK/ERROR (2/20)
Above report can be useful to regress a USB devices, and detailed report need 
to referred only when anything fails. 

Please provide your opinion on the same. 

> --
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v2] arm: imx: Add support for GE Bx50v3 boards

2016-03-09 Thread Akshay Bhat



On 03/09/2016 06:47 AM, Stefano Babic wrote:

On 29/01/2016 21:16, Akshay Bhat wrote:

Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
  - FEC Ethernet
  - USB Ports
  - SDHC and MMC boot
  - SPI NOR
  - LVDS and HDMI display

Basic information about the module:
  - Module manufacturer: Advantech
  - CPU: Freescale ARM Cortex-A9 i.MX6D
  - SPECS:
  Up to 2GB Onboard DDR3 Memory;
  Up to 16GB Onboard eMMC NAND Flash
  Supports OpenGL ES 2.0 and OpenVG 1.1
  HDMI, 24-bit LVDS
  1x UART, 2x I2C, 8x GPIO,
  4x Host USB 2.0 port, 1x USB OTG port,
  1x micro SD (SDHC),1x SDIO, 1x SATA II,
  1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat 
---


Applied to -next, thanks !



Thank you very much for making -next happen. Appreciate it.
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Re: [U-Boot] Newbie SPL question for socfpga_sockit

2016-03-09 Thread George Broz
On 9 March 2016 at 02:55, Marek Vasut  wrote:
> On 03/09/2016 02:42 AM, Phil Reid wrote:
>> G'day George,
>>
>> On 3/03/2016 10:57 PM, George Broz wrote:
>>> On 2 March 2016 at 23:11, Phil Reid  wrote:
 On 3/03/2016 2:49 PM, George Broz wrote:
>
> On 1 March 2016 at 19:49, Phil Reid  wrote:
>>
>> On 2/03/2016 10:40 AM, George Broz wrote:
>>
>>> Sorry for the delayed response - got called away, but am back to this
>>> now. I patched
>>> socfpga_common.h and re-built the project. I picked up
>>> spl/u-boot-spl-dtb.sfp and
>>> u-boot-dtb.img and transferred them to the SD card with:
>>>
>>> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0
>>> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4
>>>
>>> Tried this with both the original DT set (socfpga.dtsi,
>>> socfpga_cyclone.dtsi,
>>> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01
>>> download
>>> and
>>> also an Altera-patched DT set that I've used to boot into Linux
>>> numerous
>>> times.
>>>
>>> When I start up the board I get:
>>>
>>> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> SDRAM calibration failed.
>>> ### ERROR ### Please RESET the board ###
>>>
>>> I'm not a Quartus user, so I haven't done anything with the
>>> qts-filter.sh script you
>>> mentioned. Do I need to? I don't have any custom FPGA logic - it's
>>> just the Terasic
>>> board out of the box.
>>>
>>> Thanks for any help!
>>>
>>
>> Even without the custom FPGA logic the files generated from
>> qts-filter.sh
>> need to match your board.
>> Sets up PLL and SDRAM parameters.
>> I'm not familiar with the Terasic dev board ( I do have the altera
>> devkit,
>> but haven't used it for awhile).
>> I'd hope the files in the git repo are correct for your board.
>> Without the corresponding qsys project it's hard to be sure.
>>
> Hi Phil,
>
> So as my next attempt, there was a Quartus/Qsys example that came
> with the Terasic board (specific to my Rev. of the board).
>
> * I took the contents of the 'handoff folder', .sof, and .sopcinfo
> file.
> * launched an "Embedded Command Shell" from EDS 15.0 and then the BSP
> editor GUI
> * pointed the BSP editor to the "handoff folder", and hit "Generate"
> to produce iocsr, pinmux, pll, etc. files
> * applied qts-filter.sh to these files, the output of which I then
> dropped into the u-boot source @ ../board/terasic/sockit/qts
> * rebuilt uboot spl & image, but got a similar result:
>
> U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
> drivers/ddr/altera/sequencer.c: Calibration complete
> SDRAM calibration failed.
> ### ERROR ### Please RESET the board ###
>
> Except now it repeats four times, whereas before it only printed out
> once.
>
> It that essentially the correct procedure? Is it now a matter of
> looking through
> the include files that where generated by qts-filter.sh to find a
> setting that is "off"?
>
> (BTW - my first attempt was to use EDS 13.0, but that resulted in
> several undefined macros when it
> came time to compile u-boot with the qts-filter-generated code. How
> does one know which tool version to use?)
>

 What does a diff of the new files show compared to the ones in uboot.
>>>
>>> Here's two of them...
>>>
>>> ---
>>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig
>>>
>>> +++
>>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h
>>>
>>>
>>> @@ -33,10 +33,10 @@
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
>>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
>>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
>>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
>>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
>>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
>>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
>>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
>>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
>>>
>>> @@ -46,12 +46,12 @@
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
>>>   #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_T

Re: [U-Boot] [PATCH v4] x86: baytrail: Configure FSP UPD from device tree

2016-03-09 Thread Stefan Roese
Hi Simon,

On 09.03.2016 00:33, Simon Glass wrote:



 I'm currently struggling with the USB EHCI ports on my custom Bay
 Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
 only some of the USB EHCI ports are enabled / available. Here
 the "usb tree" output with 3 USB keys installed:

 => usb tree
 USB device tree:
 1  Hub (480 Mb/s, 0mA)
 |  u-boot EHCI Host Controller
 |
 +-2  Hub (480 Mb/s, 0mA)
   |
   +-3  Hub (480 Mb/s, 100mA)
   | |
   | +-4  Hub (12 Mb/s, 100mA)
   |
   +-5  Mass Storage (480 Mb/s, 200mA)
JetFlash Mass Storage Device 3281440601

 When I first start the original (AMI) BIOS on this custom board,
 and then reboot into U-Boot (without a power-cycle), I see this
 configuration:

 => usb tree
 USB device tree:
 1  Hub (480 Mb/s, 0mA)
 |  u-boot EHCI Host Controller
 |
 +-2  Hub (480 Mb/s, 0mA)
   |
   +-3  Hub (480 Mb/s, 100mA)
   | |
   | +-4  Hub (12 Mb/s, 100mA)
   |
   +-5  Hub (480 Mb/s, 0mA)
   | |
   | +-6  Mass Storage (480 Mb/s, 200mA)
   | |Kingston DataTraveler 2.0 50E549C688C4BE7189942766
   | |
   | +-7  Mass Storage (480 Mb/s, 98mA)
   |  USBest Technology USB Mass Storage Device 09092207fbf0c4
   |
   +-8  Mass Storage (480 Mb/s, 200mA)
JetFlash Mass Storage Device 3281440601

 So now all 3 USB sticks are detected.

 It doesn't seem to be a problem with missing USB power switch
 enabling via some GPIOs. I've checked the schematics and all ports
 should have power enabled.

 Do you have any quick ideas, what might be missing to enable all
 4 EHCI ports on Bay Trail? There seems to be a per-port disable
 feature which might be involved. I'm still pretty new to x86, and
 I'm struggling with finding the correct datasheet for this. So any
 hints are really appreciated.
>>>
>>> It might be worth checking the pci bus device list in both cases.
>>> Perhaps one of the USB ports is disabled?
>>
>> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
>> In both cases its this output:
>>
>> => pci
>> Scanning PCI devices on bus 0
>> BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
>> _
>> 00.1f.00   0x8086 0x0f1c Bridge device   0x01
>> 00.00.00   0x8086 0x0f00 Bridge device   0x00
>> 00.02.00   0x8086 0x0f31 Display controller  0x00
>> 00.11.00   0x8086 0x0f15 Base system peripheral  0x05
>> 00.12.00   0x8086 0x0f16 Base system peripheral  0x05
>> 00.13.00   0x8086 0x0f23 Mass storage controller 0x06
>> 00.15.00   0x8086 0x0f28 Multimedia device   0x01
>> 00.18.00   0x8086 0x0f40 Base system peripheral  0x01
>> 00.18.01   0x8086 0x0f41 Serial bus controller   0x80
>> 00.18.02   0x8086 0x0f42 Serial bus controller   0x80
>> 00.18.03   0x8086 0x0f43 Serial bus controller   0x80
>> 00.18.04   0x8086 0x0f44 Serial bus controller   0x80
>> 00.18.05   0x8086 0x0f45 Serial bus controller   0x80
>> 00.18.06   0x8086 0x0f46 Serial bus controller   0x80
>> 00.18.07   0x8086 0x0f47 Serial bus controller   0x80
>> 00.1a.00   0x8086 0x0f18 Cryptographic device0x80
>> 00.1c.00   0x8086 0x0f48 Bridge device   0x04
>> 00.1c.03   0x8086 0x0f4e Bridge device   0x04
>> 00.1d.00   0x8086 0x0f34 Serial bus controller   0x03
>> 00.1e.00   0x8086 0x0f06 Base system peripheral  0x01
>> 00.1e.01   0x8086 0x0f08 Serial bus controller   0x80
>> 00.1e.02   0x8086 0x0f09 Serial bus controller   0x80
>> 00.1e.04   0x8086 0x0f0c Simple comm. controller 0x80
>> 00.1e.05   0x8086 0x0f0e Serial bus controller   0x80
>> 00.1f.03   0x8086 0x0f12 Serial bus controller   0x05
>>
>> Here 00.1d.00 is the EHCI controller. The "pci long" output
>> is also identical. So its not that simple I'm afraid.
>>
>> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
>> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
>> page 150:
>>
>> • Per port USB disable
>>
>> Perhaps this feature is biting me here. I'm wondering how this can
>> be configured.
> 
> That sounds likely.
> 
> Also: xHCI and EHCI Port Mapping
> 
> suggests that you need to make sure the ports are being driven by EHCI
> instead of XHCI.
> 
> It mentions USB2HCSEL but I cannot find that in the datasheet.

Same here.
 
> It does appear here though:
> 
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c
> 
> See  IOSF_PORT_0x5a here:
> 
> https://chromium.googlesource

[U-Boot] [RESEND PATCH 6/7 v5] pci/layerscape: fdt: function to set msi-map entries

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

msi-map properties are used to tell an OS how PCI requester
IDs are mapped to ARM SMMU stream IDs.  This patch defines a
function to append a single msi-map entry to a given PCI controller
device tree node.

Signed-off-by: Stuart Yoder 
---
-v5: no change

 drivers/pci/pcie_layerscape.c |   42 +
 1 file changed, 42 insertions(+)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index f3bf689..73af423 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -520,6 +520,48 @@ static u32 ls_pcie_next_streamid(void)
 
return next_stream_id++;
 }
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node.  It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ *  msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
+  u32 devid, u32 streamid)
+{
+   char pcie_path[19];
+   u32 *prop;
+   u32 phandle;
+   int nodeoffset;
+
+   /* find pci controller node */
+   snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
+(u64)pcie->dbi);
+   nodeoffset = fdt_path_offset(blob, pcie_path);
+   if (nodeoffset < 0) {
+   printf("\n%s: ERROR: unable to update PCIe node: %s\n",
+  __func__, pcie_path);
+   return;
+   }
+
+   /* get phandle to MSI controller */
+   prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
+   if (prop == NULL) {
+   printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
+  pcie_path);
+   return;
+   }
+   phandle = be32_to_cpu(*prop);
+
+   /* set one msi-map row */
+   fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
+   fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
+   fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
+   fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
+}
 #endif
 
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
*info)
-- 
1.7.9.5

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[U-Boot] [RESEND PATCH 5/7 v5] pci/layerscape: add stream ID allocator

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

add a function to return the next available stream ID
for PCI

Signed-off-by: Stuart Yoder 
---
-v5: no change

 drivers/pci/pcie_layerscape.c |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 5cc6855..f3bf689 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -509,6 +509,17 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, 
int index, u32 devid,
writel((devid << 16), lut + PCIE_LUT_UDR(index));
writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
 }
+
+/* returns the next available streamid */
+static u32 ls_pcie_next_streamid(void)
+{
+   static int next_stream_id = FSL_PEX_STREAM_ID_START;
+
+   if (next_stream_id > FSL_PEX_STREAM_ID_END)
+   return 0x;
+
+   return next_stream_id++;
+}
 #endif
 
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
*info)
-- 
1.7.9.5

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[U-Boot] [RESEND PATCH 1/7 v5] armv8: ls2080a: remove obsolete stream ID partitioning support

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder 
---
-v5: no change

 arch/arm/cpu/armv8/fsl-layerscape/fdt.c |  113 ---
 drivers/pci/pcie_layerscape.c   |   70 ---
 2 files changed, 183 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4e4861d..7a64f41 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -70,115 +70,6 @@ void ft_fixup_cpu(void *blob)
 }
 #endif
 
-/*
- * the burden is on the the caller to not request a count
- * exceeding the bounds of the stream_ids[] array
- */
-void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt)
-{
-   int i;
-
-   if (count > max_cnt) {
-   printf("\n%s: ERROR: max per-device stream ID count exceed\n",
-  __func__);
-   return;
-   }
-
-   for (i = 0; i < count; i++)
-   stream_ids[i] = start_id++;
-}
-
-/*
- * This function updates the mmu-masters property on the SMMU
- * node as per the SMMU binding-- phandle and list of stream IDs
- * for each MMU master.
- */
-void append_mmu_masters(void *blob, const char *smmu_path,
-   const char *master_name, u32 *stream_ids, int count)
-{
-   u32 phandle;
-   int smmu_nodeoffset;
-   int master_nodeoffset;
-   int i;
-
-   /* get phandle of mmu master device */
-   master_nodeoffset = fdt_path_offset(blob, master_name);
-   if (master_nodeoffset < 0) {
-   printf("\n%s: ERROR: master not found\n", __func__);
-   return;
-   }
-   phandle = fdt_get_phandle(blob, master_nodeoffset);
-   if (!phandle) { /* if master has no phandle, create one */
-   phandle = fdt_create_phandle(blob, master_nodeoffset);
-   if (!phandle) {
-   printf("\n%s: ERROR: unable to create phandle\n",
-  __func__);
-   return;
-   }
-   }
-
-   /* append it to mmu-masters */
-   smmu_nodeoffset = fdt_path_offset(blob, smmu_path);
-   if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
-  phandle) < 0) {
-   printf("\n%s: ERROR: unable to update SMMU node\n", __func__);
-   return;
-   }
-
-   /* for each stream ID, append to mmu-masters */
-   for (i = 0; i < count; i++) {
-   fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters",
-  stream_ids[i]);
-   }
-
-   /* fix up #stream-id-cells with stream ID count */
-   if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells",
-   count) < 0)
-   printf("\n%s: ERROR: unable to update #stream-id-cells\n",
-  __func__);
-}
-
-
-/*
- * The info below summarizes how streamID partitioning works
- * for ls2080a and how it is conveyed to the OS via the device tree.
- *
- *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
- * -all legacy devices get a unique ICID assigned and programmed in
- *  their AMQR registers by u-boot
- * -u-boot updates the hardware device tree with streamID properties
- *  for each platform/legacy device (smmu-masters property)
- *
- *  -PCIe
- * -for each PCI controller that is active (as per RCW settings),
- *  u-boot will allocate a range of ICID and convey that to Linux via
- *  the device tree (smmu-masters property)
- *
- *  -DPAA2
- * -u-boot will allocate a range of ICIDs to be used by the Management
- *  Complex for containers and will set these values in the MC DPC image.
- * -the MC is responsible for allocating and setting up ICIDs
- *  for all DPAA2 devices.
- *
- */
-#ifdef CONFIG_FSL_LSCH3
-static void fdt_fixup_smmu(void *blob)
-{
-   int nodeoffset;
-
-   nodeoffset = fdt_path_offset(blob, "/iommu@500");
-   if (nodeoffset < 0) {
-   printf("\n%s: WARNING: no SMMU node found\n", __func__);
-   return;
-   }
-
-   /* fixup for all PCI controllers */
-#ifdef CONFIG_PCI
-   fdt_fixup_smmu_pcie(blob);
-#endif
-}
-#endif
-
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_MP
@@ -200,8 +91,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_ESDHC
fdt_fixup_esdhc(blob, bd);
 #endif
-
-#ifdef CONFIG_FSL_LSCH3
-   fdt_fixup_smmu(blob);
-#endif
 }
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 99f9c83..bb29222 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -664,73 +664,3 @@ void ft_pci_setup(void *blob, bd_t *bd)
 {
 }
 #endif
-
-#

[U-Boot] [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.

This patch implements infrastructure to enable LUT initialization:
  -define registers offsets
  -add an index to 'struct ls_pcie' to track next available slot in LUT
  -add function to allocate the next available entry index
  -add function to program a LUT entry

Signed-off-by: Stuart Yoder 
---
-v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines

 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
 drivers/pci/pcie_layerscape.c  |   30 
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..d04e336 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -86,6 +86,10 @@
 #define PCIE_LUT_BASE  0x8
 #define PCIE_LUT_LCTRL00x7F8
 #define PCIE_LUT_DBG   0x7FC
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT32
 
 /* Device Configuration */
 #define DCFG_BASE  0x01e0
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index bb29222..5cc6855 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -93,6 +93,7 @@ struct ls_pcie {
void __iomem *dbi;
void __iomem *va_cfg0;
void __iomem *va_cfg1;
+   int next_lut_index;
struct pci_controller hose;
 };
 
@@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct 
ls_pcie_info *info)
}
 }
 
+#ifdef CONFIG_FSL_LSCH3
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
+{
+   if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+   return pcie->next_lut_index++;
+   else
+   return -1;  /* LUT is full */
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
+u32 streamid)
+{
+   void __iomem *lut;
+
+   lut = pcie->dbi + PCIE_LUT_BASE;
+
+   /* leave mask as all zeroes, want to match all bits */
+   writel((devid << 16), lut + PCIE_LUT_UDR(index));
+   writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+}
+#endif
+
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
*info)
 {
struct ls_pcie *pcie;
@@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, 
struct ls_pcie_info *info)
pcie->va_cfg1 = map_physmem(info->cfg1_phys,
info->cfg1_size,
MAP_NOCACHE);
+   pcie->next_lut_index = 0;
 
/* outbound memory */
pci_set_region(&hose->regions[0],
-- 
1.7.9.5

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[U-Boot] [RESEND PATCH 2/7 v5] armv8: ls2080a: update stream ID partitioning info

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

-update comments around how stream IDs are partitioned

-stream IDs allocated to PCI are no longer divided up by
 controller, but are instead a contiguous range

Signed-off-by: Stuart Yoder 
---
-v5: no change

 .../asm/arch-fsl-layerscape/ls2080a_stream_id.h|   55 
 1 file changed, 34 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
index 954104b..ee28323 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
@@ -7,28 +7,48 @@
 #ifndef __FSL_STREAM_ID_H
 #define __FSL_STREAM_ID_H
 
-/* Stream IDs on ls2080a devices are not hardwired and are
+/*
+ * Stream IDs on ls2080a devices are not hardwired and are
  * programmed by sw.  There are a limited number of stream IDs
  * available, and the partitioning of them is scenario dependent.
  * This header defines the partitioning between legacy, PCI,
  * and DPAA2 devices.
  *
- * This partitiong can be customized in this file depending
- * on the specific hardware config-- e.g. perhaps not all
- * PEX controllers are in use.
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
+ * -all legacy devices get a unique stream ID assigned and programmed in
+ *  their AMQR registers by u-boot
+ *
+ *  -PCIe
+ * -there is a range of stream IDs set aside for PCI in this
+ *  file.  U-boot will scan the PCI bus and for each device discovered:
+ * -allocate a streamID
+ * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ * -set a msi-map entry in the PEXn controller node in the
+ *  device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *  for more info on the msi-map definition)
  *
- * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
+ *  -DPAA2
+ * -u-boot will allocate a range of stream IDs to be used by the Management
+ *  Complex for containers and will set these values in the MC DPC image.
+ * -the MC is responsible for allocating and setting up 'isolation context
+ *  IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
+ *
+ * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
  *  AMQ bitstreamID bit
  *  ---
- *   PL[18] 9
- *  BMT[17] 8
- *   VA[16] 7
- * [15] -
- * ICID[14:7]   -
- * ICID[6:0]6-0
+ *   PL[18] 9// privilege bit
+ *  BMT[17] 8// bypass translation
+ *   VA[16] 7// reserved
+ * [15] -// unused
+ * ICID[14:7]   -// unused
+ * ICID[6:0]6-0  // isolation context id
  * 
+ *
  */
 
 #define AMQ_PL_MASK(0x1 << 18)   /* priviledge bit */
@@ -46,16 +66,9 @@
 #define FSL_SATA2_STREAM_ID5
 #define FSL_DMA_STREAM_ID  6
 
-/* PCI - programmed in PEXn_LUT by OS */
-/*   4 IDs per controller */
-#define FSL_PEX1_STREAM_ID_START   7
-#define FSL_PEX1_STREAM_ID_END 10
-#define FSL_PEX2_STREAM_ID_START   11
-#define FSL_PEX2_STREAM_ID_END 14
-#define FSL_PEX3_STREAM_ID_START   15
-#define FSL_PEX3_STREAM_ID_END 18
-#define FSL_PEX4_STREAM_ID_START   19
-#define FSL_PEX4_STREAM_ID_END 22
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START7
+#define FSL_PEX_STREAM_ID_END  22
 
 /* DPAA2 - set in MC DPC and alloced by MC */
 #define FSL_DPAA2_STREAM_ID_START  23
-- 
1.7.9.5

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[U-Boot] [RESEND PATCH 7/7 v5] pci/layerscape: set LUT and msi-map for discovered PCI devices

2016-03-09 Thread Stuart Yoder
From: Stuart Yoder 

for all PCI devices discovered in a system:
  -allocate a LUT (look-up-table) entry in that PCI controller
  -allocate a stream ID for the device
  -program and enable a LUT entry (maps PCI requester id to stream ID)
  -set the msi-map property on the controller reflecting the
   LUT mapping

basic bus scanning loop/logic was taken from drivers/pci/pci.c
pci_hose_scan_bus().

Signed-off-by: Stuart Yoder 
---
-v5: no change

 drivers/pci/pcie_layerscape.c |   64 +
 1 file changed, 64 insertions(+)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 73af423..0450483 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -562,6 +562,66 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct 
ls_pcie *pcie,
fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
 }
+
+static void fdt_fixup_pcie(void *blob)
+{
+   unsigned int found_multi = 0;
+   unsigned char header_type;
+   int index;
+   u32 streamid;
+   pci_dev_t dev;
+   int bus;
+   unsigned short id;
+   struct pci_controller *hose;
+   struct ls_pcie *pcie;
+   int i;
+
+   for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
+   pcie = hose->priv_data;
+   for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
+
+   for (dev =  PCI_BDF(bus, 0, 0);
+dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+   PCI_MAX_PCI_FUNCTIONS - 1);
+dev += PCI_BDF(0, 0, 1)) {
+
+   if (PCI_FUNC(dev) && !found_multi)
+   continue;
+
+   pci_read_config_word(dev, PCI_VENDOR_ID, &id);
+
+   pci_read_config_byte(dev, PCI_HEADER_TYPE,
+&header_type);
+
+   if ((id == 0x) || (id == 0x))
+   continue;
+
+   if (!PCI_FUNC(dev))
+   found_multi = header_type & 0x80;
+
+   streamid = ls_pcie_next_streamid();
+   if (streamid == 0x) {
+   printf("ERROR: no stream ids free\n");
+   continue;
+   }
+
+   index = ls_pcie_next_lut_index(pcie);
+   if (index < 0) {
+   printf("ERROR: no LUT indexes free\n");
+   continue;
+   }
+
+   /* map PCI b.d.f to streamID in LUT */
+   ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+   streamid);
+
+   /* update msi-map in device tree */
+   fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+  streamid);
+   }
+   }
+   }
+}
 #endif
 
 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
*info)
@@ -740,6 +800,10 @@ void ft_pci_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCIE4
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
#endif
+
+   #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   fdt_fixup_pcie(blob);
+   #endif
 }
 
 #else
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 1/3] armv8/ls1043aqds: fix fman ucode address to an offset in QSPI flash

2016-03-09 Thread york sun
On 03/09/2016 12:00 AM, Gong Qianyu wrote:
> Modify the value as the SPI interface is changed.
> 
> Signed-off-by: Gong Qianyu 
> ---
>  include/configs/ls1043a_common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/configs/ls1043a_common.h 
> b/include/configs/ls1043a_common.h
> index 7018cb5..c78ba47 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -222,7 +222,7 @@
>  
>  #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
>  #define CONFIG_SYS_QE_FW_IN_SPIFLASH
> -#define CONFIG_SYS_FMAN_FW_ADDR  0x400d
> +#define CONFIG_SYS_FMAN_FW_ADDR  0xd
>  #define CONFIG_ENV_SPI_BUS   0
>  #define CONFIG_ENV_SPI_CS0
>  #define CONFIG_ENV_SPI_MAX_HZ100
> 

Put a note to remind myself. These changes are based on spi-nor changes Jagan is
working on.

York

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Re: [U-Boot] [PATCH 1/2] defconfig: ls1021aqds_sdcard_qspi: Enable SPI-NOR

2016-03-09 Thread york sun
On 03/08/2016 07:04 PM, Alison Wang wrote:
> As QSPI driver is supported in ls1021aqds_sdcard_qspi_defconfig, SPI-NOR
> with MTD uclass, CONFIG_MTD_DATAFLASH and new flash vendor config
> CONFIG_SPI_NOR_SPANSION need be enabled.
> 
> Signed-off-by: Alison Wang 
> ---
>  configs/ls1021aqds_sdcard_qspi_defconfig | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig 
> b/configs/ls1021aqds_sdcard_qspi_defconfig
> index cd75af6..25ab3ee 100644
> --- a/configs/ls1021aqds_sdcard_qspi_defconfig
> +++ b/configs/ls1021aqds_sdcard_qspi_defconfig
> @@ -7,8 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_OF_CONTROL=y
>  CONFIG_DM=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_MTD=y
> +CONFIG_MTD_SPI_NOR=y
> +CONFIG_MTD_M25P80=y
> +CONFIG_MTD_DATAFLASH=y
> +CONFIG_SPI_NOR_SPANSION=y
>  CONFIG_NETDEVICES=y
>  CONFIG_E1000=y
>  CONFIG_SYS_NS16550=y
> 

Put a note for myself, this patch is on top of spi-nor patchset Jagan is 
working on.

York
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Re: [U-Boot] armv8: fsl-layerscape: Updating entries in Serdes Table

2016-03-09 Thread york sun
On 03/08/2016 01:16 AM, Pratiyush Mohan Srivastava wrote:
> From: Pratiyush Srivastava 
> 
> The serdes protocol entries in  Serdes table 1 for protocol
> 0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
> and 0x47 are updated to reflect the entries in
> current Reference Manual.
> 
> Signed-off-by: Pratiyush Mohan Srivastava 
> Reported-by: Jose Rivera 
> ---

Please resend with updated version number. Somehow patchwork didn't catch this
patch.

York


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Re: [U-Boot] [PATCH v4] x86: baytrail: Configure FSP UPD from device tree

2016-03-09 Thread Simon Glass
Hi Stefan,

On 9 March 2016 at 09:15, Stefan Roese  wrote:
>
> Hi Simon,
>
> On 09.03.2016 00:33, Simon Glass wrote:
>
> 
>
>  I'm currently struggling with the USB EHCI ports on my custom Bay
>  Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>  only some of the USB EHCI ports are enabled / available. Here
>  the "usb tree" output with 3 USB keys installed:
> 
>  => usb tree
>  USB device tree:
>  1  Hub (480 Mb/s, 0mA)
>  |  u-boot EHCI Host Controller
>  |
>  +-2  Hub (480 Mb/s, 0mA)
>    |
>    +-3  Hub (480 Mb/s, 100mA)
>    | |
>    | +-4  Hub (12 Mb/s, 100mA)
>    |
>    +-5  Mass Storage (480 Mb/s, 200mA)
> JetFlash Mass Storage Device 3281440601
> 
>  When I first start the original (AMI) BIOS on this custom board,
>  and then reboot into U-Boot (without a power-cycle), I see this
>  configuration:
> 
>  => usb tree
>  USB device tree:
>  1  Hub (480 Mb/s, 0mA)
>  |  u-boot EHCI Host Controller
>  |
>  +-2  Hub (480 Mb/s, 0mA)
>    |
>    +-3  Hub (480 Mb/s, 100mA)
>    | |
>    | +-4  Hub (12 Mb/s, 100mA)
>    |
>    +-5  Hub (480 Mb/s, 0mA)
>    | |
>    | +-6  Mass Storage (480 Mb/s, 200mA)
>    | |Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>    | |
>    | +-7  Mass Storage (480 Mb/s, 98mA)
>    |  USBest Technology USB Mass Storage Device 09092207fbf0c4
>    |
>    +-8  Mass Storage (480 Mb/s, 200mA)
> JetFlash Mass Storage Device 3281440601
> 
>  So now all 3 USB sticks are detected.
> 
>  It doesn't seem to be a problem with missing USB power switch
>  enabling via some GPIOs. I've checked the schematics and all ports
>  should have power enabled.
> 
>  Do you have any quick ideas, what might be missing to enable all
>  4 EHCI ports on Bay Trail? There seems to be a per-port disable
>  feature which might be involved. I'm still pretty new to x86, and
>  I'm struggling with finding the correct datasheet for this. So any
>  hints are really appreciated.
> >>>
> >>> It might be worth checking the pci bus device list in both cases.
> >>> Perhaps one of the USB ports is disabled?
> >>
> >> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
> >> In both cases its this output:
> >>
> >> => pci
> >> Scanning PCI devices on bus 0
> >> BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
> >> _
> >> 00.1f.00   0x8086 0x0f1c Bridge device   0x01
> >> 00.00.00   0x8086 0x0f00 Bridge device   0x00
> >> 00.02.00   0x8086 0x0f31 Display controller  0x00
> >> 00.11.00   0x8086 0x0f15 Base system peripheral  0x05
> >> 00.12.00   0x8086 0x0f16 Base system peripheral  0x05
> >> 00.13.00   0x8086 0x0f23 Mass storage controller 0x06
> >> 00.15.00   0x8086 0x0f28 Multimedia device   0x01
> >> 00.18.00   0x8086 0x0f40 Base system peripheral  0x01
> >> 00.18.01   0x8086 0x0f41 Serial bus controller   0x80
> >> 00.18.02   0x8086 0x0f42 Serial bus controller   0x80
> >> 00.18.03   0x8086 0x0f43 Serial bus controller   0x80
> >> 00.18.04   0x8086 0x0f44 Serial bus controller   0x80
> >> 00.18.05   0x8086 0x0f45 Serial bus controller   0x80
> >> 00.18.06   0x8086 0x0f46 Serial bus controller   0x80
> >> 00.18.07   0x8086 0x0f47 Serial bus controller   0x80
> >> 00.1a.00   0x8086 0x0f18 Cryptographic device0x80
> >> 00.1c.00   0x8086 0x0f48 Bridge device   0x04
> >> 00.1c.03   0x8086 0x0f4e Bridge device   0x04
> >> 00.1d.00   0x8086 0x0f34 Serial bus controller   0x03
> >> 00.1e.00   0x8086 0x0f06 Base system peripheral  0x01
> >> 00.1e.01   0x8086 0x0f08 Serial bus controller   0x80
> >> 00.1e.02   0x8086 0x0f09 Serial bus controller   0x80
> >> 00.1e.04   0x8086 0x0f0c Simple comm. controller 0x80
> >> 00.1e.05   0x8086 0x0f0e Serial bus controller   0x80
> >> 00.1f.03   0x8086 0x0f12 Serial bus controller   0x05
> >>
> >> Here 00.1d.00 is the EHCI controller. The "pci long" output
> >> is also identical. So its not that simple I'm afraid.
> >>
> >> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
> >> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
> >> page 150:
> >>
> >> • Per port USB disable
> >>
> >> Perhaps this feature is biting me here. I'm wondering how this can
> >> be configured.
> >
> > That sounds likely.
> >
> > Also: xHCI and EHCI Port Mapping
> >
> > suggests that you need to make sure the ports are being driven by EHCI
> > instead of XHCI.
> >
> > It men

Re: [U-Boot] [PATCH v4 04/14] SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb

2016-03-09 Thread york sun
On 02/08/2016 09:27 PM, Saksham Jain wrote:
> Following changes have been made to enable secure boot:
> 1) Sec_init has been called in starting to initialize SEC Block (CAAM)
> which will be used for Secure Boot validation later for both ls2080a qds
> and rdb
> 2) 64Bit address in ESBC Header has been enabled as this SoC is based on
> armv8
> 3) Secure Boot defconfigs created for boards (NOR Boot).
> 
> Signed-off-by: Aneesh Bansal 
> Signed-off-by: Saksham Jain 
> ---
> Changes for v2:
>   - No changes
> Changes for v3:
>   - No changes
> Changes for v4:
>   - Cleaned up commit message
> 
>  arch/arm/include/asm/fsl_secure_boot.h   |  9 +++--
>  board/freescale/ls2080aqds/ls2080aqds.c  |  5 -
>  board/freescale/ls2080ardb/ls2080ardb.c  |  5 -
>  configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++
>  configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++
>  configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++
>  configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++
>  include/configs/ls2080aqds.h |  2 ++
>  include/configs/ls2080ardb.h |  2 ++
>  9 files changed, 79 insertions(+), 4 deletions(-)
>  create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig
>  create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig
>  create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig
>  create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig
> 

Please update MAINTAINERS file.

York

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Re: [U-Boot] buildman for sandbox

2016-03-09 Thread Simon Glass
Hi Tom,

On 8 March 2016 at 16:42, Tom Rini  wrote:
> On Sun, Mar 06, 2016 at 07:39:30PM -0700, Simon Glass wrote:
>> Hi Joe,
>>
>> On 7 May 2015 at 03:17, Joe Hershberger  wrote:
>> > Hi Simon,
>> >
>> > Is there a way to make buildman compile sandbox with a non-system tool
>> > chain? I've tried creating an alias from sandbox to i386 and removing
>> > the "root" entry. It then simply claims not to have a sandbox tool
>> > chain.
>> >
>> > Thanks,
>> > -Joe
>>
>> FYI I've prepared a series that permits:
>>
>> [toolchain-prefix]
>> sandbox = /path/to/sandbox-gcc
>
> And in this case it just takes what it finds, if it exists right?  ie I
> can also do:
> sandbox = /usr/bin/clang
> ?

What should it set CROSS_COMPILE to in that case?

Regards,
Simon
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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Simon Glass
Hi,

On 9 March 2016 at 05:55, Marek Vasut  wrote:
>
> On 03/09/2016 01:21 PM, Hans de Goede wrote:
> > Hi,
> >
> > On 09-03-16 12:28, Marek Vasut wrote:
> >> On 03/09/2016 12:22 PM, Rajat Srivastava wrote:
> >>> This patch adds a new 'usb regress' command, that can be used to
> >>> regress test a USB device. It performs the following operations:
> >>>
> >>> 1. starts the USB device
> >>> 2. performs read/write operations
> >>> 3. stops the USB device
> >>> 4. verifies the contents of read/write operations
> >>>
> >>> Sample Output:
> >>> => usb regress 8100 8200 32m
> >>> regressing USB..
> >>> starting USB...
> >>> USB0:   Register 200017f NbrPorts 2
> >>> Starting the controller
> >>> USB XHCI 1.00
> >>> scanning bus 0 for devices... 2 USB Device(s) found
> >>> scanning usb for storage devices... 1 Storage Device(s) found
> >>> USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
> >>> USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
> >>> stopping USB..
> >>> verifying data on addresses 0x8100 and 0x8200
> >>> Total of 65536 word(s) were the same
> >>>
> >>> Signed-off-by: Rajat Srivastava 
> >>> Signed-off-by: Rajesh Bhagat 
> >>
> >>
> >> Does it do anything which cannot be achieved on the command line itself
> >> using "usb reset" "usb write" "usb read" "cmp" commands ?
> >
> > This seems to be about a reading / writing a usb-disk / usb-storage device.
>
> That's what usb read / usb write commands are for, reading raw data from
> USB disk :-)
>
> > I believe this can certainly be achieved with the existing disk io
> > commands,
> > and moreover this seems quite dangerous (overwriting the partition table on
> > the device), so I think requiring the user to do this explicitly indeed
> > seems better.
>
> Yeah
>
> > Regards,
> >
> > Hans

We do have an 'sf test' command. I think it is useful, particularly if
it measures speed as well.

Regards,
Simon
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Re: [U-Boot] [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT

2016-03-09 Thread york sun
On 03/09/2016 08:24 AM, Stuart Yoder wrote:
> From: Stuart Yoder 
> 
> The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
> that maps PCI requester IDs (bus/dev/fun) to a stream ID.
> 
> This patch implements infrastructure to enable LUT initialization:
>   -define registers offsets
>   -add an index to 'struct ls_pcie' to track next available slot in LUT
>   -add function to allocate the next available entry index
>   -add function to program a LUT entry
> 
> Signed-off-by: Stuart Yoder 
> ---
> -v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines
> 
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
>  drivers/pci/pcie_layerscape.c  |   30 
> 
>  2 files changed, 34 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 91f3ce8..d04e336 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -86,6 +86,10 @@
>  #define PCIE_LUT_BASE0x8
>  #define PCIE_LUT_LCTRL0  0x7F8
>  #define PCIE_LUT_DBG 0x7FC
> +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> +#define PCIE_LUT_ENABLE (1 << 31)
> +#define PCIE_LUT_ENTRY_COUNT32
>  
>  /* Device Configuration */
>  #define DCFG_BASE0x01e0
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index bb29222..5cc6855 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -93,6 +93,7 @@ struct ls_pcie {
>   void __iomem *dbi;
>   void __iomem *va_cfg0;
>   void __iomem *va_cfg1;
> + int next_lut_index;
>   struct pci_controller hose;
>  };
>  
> @@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, 
> struct ls_pcie_info *info)
>   }
>  }
>  
> +#ifdef CONFIG_FSL_LSCH3
> +/*
> + * Return next available LUT index.
> + */
> +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> +{
> + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> + return pcie->next_lut_index++;
> + else
> + return -1;  /* LUT is full */
> +}
> +
> +/*
> + * Program a single LUT entry
> + */
> +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 
> devid,
> +  u32 streamid)
> +{
> + void __iomem *lut;
> +
> + lut = pcie->dbi + PCIE_LUT_BASE;
> +
> + /* leave mask as all zeroes, want to match all bits */
> + writel((devid << 16), lut + PCIE_LUT_UDR(index));
> + writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
> +}
> +#endif
> +
>  int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
> *info)
>  {
>   struct ls_pcie *pcie;
> @@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, 
> struct ls_pcie_info *info)
>   pcie->va_cfg1 = map_physmem(info->cfg1_phys,
>   info->cfg1_size,
>   MAP_NOCACHE);
> + pcie->next_lut_index = 0;
>  
>   /* outbound memory */
>   pci_set_region(&hose->regions[0],
> 

Stuart,

This patch breaks git bisect. Please rearrange your changes.
 warning: ‘ls_pcie_next_lut_index’ defined but not used [-Wunused-function]
 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
^
 warning: ‘ls_pcie_lut_set_mapping’ defined but not used [-Wunused-function]
 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
 ^

York

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Re: [U-Boot] buildman for sandbox

2016-03-09 Thread Tom Rini
On Wed, Mar 09, 2016 at 10:43:58AM -0700, Simon Glass wrote:
> Hi Tom,
> 
> On 8 March 2016 at 16:42, Tom Rini  wrote:
> > On Sun, Mar 06, 2016 at 07:39:30PM -0700, Simon Glass wrote:
> >> Hi Joe,
> >>
> >> On 7 May 2015 at 03:17, Joe Hershberger  wrote:
> >> > Hi Simon,
> >> >
> >> > Is there a way to make buildman compile sandbox with a non-system tool
> >> > chain? I've tried creating an alias from sandbox to i386 and removing
> >> > the "root" entry. It then simply claims not to have a sandbox tool
> >> > chain.
> >> >
> >> > Thanks,
> >> > -Joe
> >>
> >> FYI I've prepared a series that permits:
> >>
> >> [toolchain-prefix]
> >> sandbox = /path/to/sandbox-gcc
> >
> > And in this case it just takes what it finds, if it exists right?  ie I
> > can also do:
> > sandbox = /usr/bin/clang
> > ?
> 
> What should it set CROSS_COMPILE to in that case?

Ah, so that's where life is going to get "fun" for buildman and llvm.
For sandbox, nothing.  For other arches, well, I need to toy with
cc-option I think to see if we can make life a lot easier than
doc/README.llvm says to do, today.  Not supporting llvm in buildman
today is OK since we don't well support it anyhow, but I want to fix
that going forward.

-- 
Tom


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Re: [U-Boot] [PATCH v2 2/2] fastboot: sparse: remove unnecessary logging

2016-03-09 Thread Maxime Ripard
On Tue, Feb 09, 2016 at 11:19:11AM -0800, Steve Rae wrote:
> remove logging of the 'skipped' blocks
> 
> Signed-off-by: Steve Rae 

Acked-by: Maxime Ripard 

Thanks!
Maxime

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Embedded Linux, Kernel and Android engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH v2 1/2] fastboot: sparse: fix block addressing for don't care chunk type

2016-03-09 Thread Maxime Ripard
On Tue, Feb 09, 2016 at 11:19:10AM -0800, Steve Rae wrote:
> When 7bfc3b1 (sparse: Refactor chunk parsing function) was implemented,
> it dropped 9981945 (aboot: fix block addressing for don't care chunk type).
> 
> This re-implements the required fix for the "don't care chunk type"...
> 
> Signed-off-by: Steve Rae 

Acked-by: Maxime Ripard 

Thanks!
Maxime

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Re: [U-Boot] [PATCH] usb: Add new command to regress USB devices

2016-03-09 Thread Simon Glass
Hi Rajat,

On 9 March 2016 at 04:22, Rajat Srivastava  wrote:
> This patch adds a new 'usb regress' command, that can be used to
> regress test a USB device. It performs the following operations:
>
> 1. starts the USB device
> 2. performs read/write operations
> 3. stops the USB device
> 4. verifies the contents of read/write operations
>
> Sample Output:
> => usb regress 8100 8200 32m
> regressing USB..
> starting USB...
> USB0:   Register 200017f NbrPorts 2
> Starting the controller
> USB XHCI 1.00
> scanning bus 0 for devices... 2 USB Device(s) found
>scanning usb for storage devices... 1 Storage Device(s) found
> USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK
> USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK
> stopping USB..
> verifying data on addresses 0x8100 and 0x8200
> Total of 65536 word(s) were the same
>
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Rajesh Bhagat 
> ---
>  common/cmd_usb.c | 174 
> ++-
>  1 file changed, 173 insertions(+), 1 deletion(-)

Can you rebase to mainline? This file has been renamed.

>
> diff --git a/common/cmd_usb.c b/common/cmd_usb.c
> index a540b42..25fdeab 100644
> --- a/common/cmd_usb.c
> +++ b/common/cmd_usb.c
> @@ -20,6 +20,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #ifdef CONFIG_USB_STORAGE
>  static int usb_stor_curr_dev = -1; /* current device */
> @@ -616,6 +617,167 @@ static int usb_device_info(void)
>  }
>  #endif
>
> +static unsigned long calc_blockcount(char * const size)

Can you put this function in lib/display_options.c? I suggest
something that decodes a string and returns a value (i.e. it would
return 1024 for K, not 2, since that assumes a block size).

The multiple check can go in cmd/usb.c

> +{
> +   unsigned long value, multiplier;
> +   int size_len = strlen(size);
> +   char unit;
> +
> +   /* extract the unit of size passed */
> +   unit = size[size_len - 1];
> +   /* updating the source string to remove unit */
> +   size[size_len - 1] = '\0';
> +
> +   value = simple_strtoul(size, NULL, 10);
> +   if (value <= 0) {
> +   printf("invalid size\n");
> +   return 0;
> +   }
> +
> +   if (unit == 'G' || unit == 'g') {
> +   multiplier = 2 * 1024 * 1024;
> +   } else if (unit == 'M' || unit == 'm') {
> +   multiplier = 2 * 1024;
> +   } else if (unit == 'K' || unit == 'k') {
> +   multiplier = 2;
> +   } else if (unit == 'B' || unit == 'b') {
> +   if (value % 512 != 0) {
> +   printf("size can only be multiples of 512 bytes\n");
> +   return 0;
> +   }
> +   multiplier = 1;
> +   value /= 512;
> +   } else {
> +   printf("syntax mismatch\n");
> +   return 0;
> +   }
> +
> +   return value * multiplier;
> +}
> +
> +static int usb_read_write_verify(unsigned long w_addr, unsigned long r_addr,
> +   unsigned long cnt)
> +{
> +   cmd_tbl_t *c;
> +   char str[3][16];
> +   char *ptr[4] = { "cmp", str[0], str[1], str[2] };
> +
> +   c = find_cmd("cmp");
> +   if (!c) {
> +   printf("compare command not found\n");
> +   return -1;
> +   }
> +   printf("verifying data on addresses 0x%lx and 0x%lx\n", w_addr, 
> r_addr);
> +   sprintf(str[0], "%lx", w_addr);
> +   sprintf(str[1], "%lx", r_addr);
> +   sprintf(str[2], "%lx", cnt);
> +   (c->cmd)(c, 0, 4, ptr);

We shouldn't call U-Boot functions via the command line parsing.

Please can you refactor do_mem_cmp() to separate the command parsing
from the memory comparison logic? Then you can call the latter
directory.

> +   return 0;
> +}
> +
> +
> +static int do_usb_regress(int argc, char * const argv[])

Would 'usb datatest' be a better name?

> +{
> +   unsigned long loopcount, iteration;
> +   unsigned long w_addr, r_addr, cnt, n;
> +   unsigned long blk = 0;
> +   extern char usb_started;
> +
> +#ifdef CONFIG_USB_STORAGE
> +   block_dev_desc_t *stor_dev;
> +#endif
> +
> +   if (argc < 5 || argc > 6) {
> +   printf("syntax mismatch\n");
> +   return -1;
> +   }
> +
> +   if (argc == 5)
> +   loopcount = 1;
> +   else
> +   loopcount = simple_strtoul(argv[5], NULL, 10);
> +
> +   if (loopcount <= 0) {
> +   printf("syntax mismatch\n");
> +   return -1;
> +   }
> +
> +   cnt = calc_blockcount(argv[4]);
> +   if (cnt == 0)
> +   return -1;
> +
> +   iteration = loopcount;
> +   while (loopcount--) {
> +   if (argc > 5)
> +   printf("\niteration #%lu\n\n", iteration - loopcount);
> +
> +   /* start USB */
> +  

Re: [U-Boot] Olimex-A20-EVB ethernet stops working with latest U-boot, works with tag v2016.01

2016-03-09 Thread Simon Glass
Hi,

On 9 March 2016 at 14:04, Karsten Merker  wrote:
> [Olimex A20-SOM-EVB: ethernet non-functional with current u-boot
>  git head, but no problems with v2016.01]
>
> On Tue, Mar 08, 2016 at 11:54:03AM +0100, Hans de Goede wrote:
>> On 25-02-16 08:31, Ing. Damiano Bolla wrote:
>> >Can I assist further ?
>>
>> Can you please git bisect this, and find out which commit breaks things ?
>
> Hello Hans, hello Simon,
>
> I am not the original poster, but I have bisected the issue down
> to the following commit:
>
> commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d
> Author: Simon Glass 
> Date:   Sun Jan 17 14:51:56 2016 -0700
>
> net: Don't call board/cpu_eth_init() with driver model
>
> We should avoid weak functions with driver model. Existing boards that use
> driver model don't need them, so let's kill them off.
>
> Signed-off-by: Simon Glass 
> Reviewed-by: Bin Meng 
> Acked-by: Joe Hershberger 

Is this board-specific init, or sunxi-specific?

Can you just call the init on start-up, instead of from the Ethernet driver?

Regards,
Simon
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Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-09 Thread Dinh Nguyen
On 03/09/2016 08:00 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi Marek,
> 
>> Perform usual test, disable cache (dcache off) .
> 
> I tried and result is still the same.
> 
> UPD: I did a little trick:
> 1. I started ping from the board side. That made the board listen to incoming 
> packets (calling in infinite loop eth_rx() ).
> 2. Started ping from PC side.
> 3. In this case board receive ICMP packets from PC:
> 
> packet received
> Receive from protocol 0x800
> Got IP
> len=60, v=45
> Got ICMP ECHO REQUEST, return 74 bytes 
> 
> So, ICMP packets are handled by the board, but ARP packets not.
> 
> In my understanding it tells me that at least interface on the board side is 
> alive.
> 
> I'm now doing some low-level debugging, however I think this is not the best 
> idea. :)
> Now dw_eth_recv (designware.c) always returns 0 length of the packet.
> 

I was able to tftp an kernel image using mainline U-Boot on my Arria5
board today. However, I wasn't able to dhcp, but I'm not sure if that's
the board or my network.


U-Boot 2016.03-rc3-8-g08b2472 (Mar 09 2016 - 13:37:27 -0600)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Arria V, D5, version 0x0
BOOT:  SD/MMC External Transceiver (1.8V)
   Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
In:serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Arria V SoC Development Kit
Net:   eth0: ethernet@ff702000
Hit any key to stop autoboot:  0
=> tftp ${loadaddr} zImage
Speed: 1000, full duplex
Using ethernet@ff702000 device
TFTP from server 137.57.160.210; our IP address is 137.57.160.216
Filename 'zImage'.
Load address: 0x8000
Loading:
 #
 552.7 KiB/s
done
Bytes transferred = 3491984 (354890 hex)
=>
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[U-Boot] [PATCH 2/2] sunxi: Add defconfig and dts for colorfly e708 q1 tablet

2016-03-09 Thread Hans de Goede
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly
e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC,
1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41,
stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip.

The added dts is identical to the dts submitted to the upstream kernel,
note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the
upstream kernel as the added dts depends on these.

Signed-off-by: Hans de Goede 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/axp22x.dtsi | 143 ++
 arch/arm/dts/sun6i-a31.dtsi  |  65 -
 arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 208 +++
 board/sunxi/MAINTAINERS  |   1 +
 configs/colorfly_e708_q1_defconfig   |  25 
 6 files changed, 440 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/axp22x.dtsi
 create mode 100644 arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts
 create mode 100644 configs/colorfly_e708_q1_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 578038b..a8bc7b0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -152,6 +152,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+   sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-primo81.dtb \
sun6i-a31s-sinovoip-bpi-m2.dtb
diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi
new file mode 100644
index 000..76302f5
--- /dev/null
+++ b/arch/arm/dts/axp22x.dtsi
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP221/221s/223 Integrated Power Management Chip
+ * http://www.x-powers.com/product/AXP22X.php
+ * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf
+ */
+
+&axp22x {
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   regulators {
+   /* Default work frequency for buck regulators */
+   x-powers,dcdc-freq = <3000>;
+
+   reg_dcdc1: dcdc1 {
+   regulator-name = "dcdc1";
+   };
+
+   reg_dcdc2: dcdc2 {
+   regulator-name = "dcdc2";
+   };
+
+   reg_dcdc3: dcdc3 {
+   regulator-name = "dcdc3";
+   };
+
+   reg_dcdc4: dcdc4 {
+   regulator-name = "dcdc4";
+   };
+
+   reg_dcdc5: dcdc5 {
+   regulator-name = "dcdc5";
+   };
+
+   reg_dc1sw: dc1sw {
+   regulator-name = "dc1sw";
+   };
+
+   reg_dc5ldo: dc5ldo {
+   regulator-name = "dc5ldo";
+   };
+
+   reg_aldo1: aldo1 {
+   regulator-name = "aldo1";
+   };
+
+ 

[U-Boot] [PATCH 1/2] sunxi: A23: Fix some revisions needing a different magic sram poke

2016-03-09 Thread Hans de Goede
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.

Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/board.c | 22 +++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index eb5f4b6..cb94855 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -113,11 +113,27 @@ int spl_board_load_image(void)
 
 void s_init(void)
 {
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
-   /* Magic (undocmented) value taken from boot0, without this DRAM
-* access gets messed up (seems cache related) */
+   /*
+* Undocmented magic taken from boot0, without this DRAM
+* access gets messed up (seems cache related).
+* The boot0 sources describe this as: "config ema for cache sram"
+*/
+#if defined CONFIG_MACH_SUN6I
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#elif defined CONFIG_MACH_SUN8I_A23
+   uint version;
+
+   /* Unlock sram version info reg, read it, relock */
+   setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+   version = readl(SUNXI_SRAMC_BASE + 0x24);
+   clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+   if ((version & 0x) == 0x1650)
+   setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+   else /* 0x1661 ? */
+   setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 #endif
+
 #if defined CONFIG_MACH_SUN6I || \
 defined CONFIG_MACH_SUN7I || \
 defined CONFIG_MACH_SUN8I
-- 
2.7.2

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Re: [U-Boot] [PATCH v5 24/30] efi_loader: Add distro boot script for removable media

2016-03-09 Thread Alexander Graf


On 04.03.16 01:10, Alexander Graf wrote:
> UEFI defines a simple boot protocol for removable media. There we should look
> at the EFI (first GPT FAT) partition and search for /efi/boot/bootXXX.efi with
> XXX being different between different platforms (x86, x64, arm, aa64, ...).
> 
> This patch implements a simple version of that protocol for the default distro
> boot script. With this we can automatically boot from valid UEFI enabled
> removable media.
> 
> Because from all I could see U-Boot by default doesn't deliver device tree
> blobs with its firmware, we also need to load the dtb from somewhere. Traverse
> the same EFI partition for an fdt file that fits our current board so that
> an OS receives a valid device tree when booted automatically.
> 
> Signed-off-by: Alexander Graf 
> Reviewed-by: Simon Glass 
> ---
>  include/config_distro_bootcmd.h | 47 
> -
>  1 file changed, 46 insertions(+), 1 deletion(-)
> 
> diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
> index 37c6b43..c19f1b0 100644
> --- a/include/config_distro_bootcmd.h
> +++ b/include/config_distro_bootcmd.h
> @@ -90,6 +90,48 @@
>   BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
>  #endif
>  
> +#ifdef CONFIG_EFI_LOADER
> +#if defined(CONFIG_ARM64)
> +#define BOOTEFI_NAME "bootaa64.efi"
> +#elif defined(CONFIG_ARM)
> +#define BOOTEFI_NAME "bootarm.efi"
> +#endif
> +#endif
> +
> +#ifdef BOOTEFI_NAME
> +#define BOOTENV_SHARED_EFI\
> + "boot_efi_binary="\
> + "load ${devtype} ${devnum}:${distro_bootpart} "   \
> + "${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "  \
> + "bootefi ${kernel_addr_r}\0"  \
> + \
> + "load_efi_dtb="   \
> + "load ${devtype} ${devnum}:${distro_bootpart} "   \
> + "${fdt_addr_r} ${prefix}${fdt_name}; "   \
> + "fdt addr ${fdt_addr_r}\0"\
> + \
> + "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"\
> + "scan_dev_for_efi="   \
> + "for prefix in ${efi_dtb_prefixes}; do "  \
> + "if test -e ${devtype} "  \
> + "${devnum}:${distro_bootpart} "   \
> + "${prefix}${fdt_name}; then " \
> + "run load_efi_dtb; "  \
> + "fi;" \
> + "done;"   \
> + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \
> + "efi/boot/"BOOTEFI_NAME"; then "  \
> + "echo Found EFI removable media binary "  \
> + "efi/boot/"BOOTEFI_NAME"; "   \
> + "run boot_efi_binary; "   \
> + "echo EFI LOAD FAILED: continuing...; "   \
> + "fi; "

Whoever applies this, please also apply the patch below on top and
squash it in (or tell me to resend). Without the fix, we end up slurping
the boot_prefix variable into the scan_dev_for_efi variable.


Alex

diff --git a/include/config_distro_bootcmd.h
b/include/config_distro_bootcmd.h
index e7d7002..ad9045e 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -125,7 +125,7 @@
"efi/boot/"BOOTEFI_NAME"; "   \
"run boot_efi_binary; "   \
"echo EFI LOAD FAILED: continuing...; "   \
-   "fi; "
+   "fi; \0"
 #define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
 #else
 #define BOOTENV_SHARED_EFI
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Re: [U-Boot] [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT

2016-03-09 Thread Stuart Yoder


> -Original Message-
> From: york sun
> Sent: Wednesday, March 09, 2016 12:01 PM
> To: Stuart Yoder ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Yang-Leo Li 
> 
> Subject: Re: [RESEND PATCH 4/7 v5] pci/layerscape: add support for LUT
> 
> On 03/09/2016 08:24 AM, Stuart Yoder wrote:
> > From: Stuart Yoder 
> >
> > The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
> > that maps PCI requester IDs (bus/dev/fun) to a stream ID.
> >
> > This patch implements infrastructure to enable LUT initialization:
> >   -define registers offsets
> >   -add an index to 'struct ls_pcie' to track next available slot in LUT
> >   -add function to allocate the next available entry index
> >   -add function to program a LUT entry
> >
> > Signed-off-by: Stuart Yoder 
> > ---
> > -v5: check CONFIG_FSL_LSCH3 instead of SoC specific defines
> >
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +++
> >  drivers/pci/pcie_layerscape.c  |   30 
> > 
> >  2 files changed, 34 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 91f3ce8..d04e336 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -86,6 +86,10 @@
> >  #define PCIE_LUT_BASE  0x8
> >  #define PCIE_LUT_LCTRL00x7F8
> >  #define PCIE_LUT_DBG   0x7FC
> > +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> > +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> > +#define PCIE_LUT_ENABLE (1 << 31)
> > +#define PCIE_LUT_ENTRY_COUNT32
> >
> >  /* Device Configuration */
> >  #define DCFG_BASE  0x01e0
> > diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> > index bb29222..5cc6855 100644
> > --- a/drivers/pci/pcie_layerscape.c
> > +++ b/drivers/pci/pcie_layerscape.c
> > @@ -93,6 +93,7 @@ struct ls_pcie {
> > void __iomem *dbi;
> > void __iomem *va_cfg0;
> > void __iomem *va_cfg1;
> > +   int next_lut_index;
> > struct pci_controller hose;
> >  };
> >
> > @@ -482,6 +483,34 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, 
> > struct
> ls_pcie_info *info)
> > }
> >  }
> >
> > +#ifdef CONFIG_FSL_LSCH3
> > +/*
> > + * Return next available LUT index.
> > + */
> > +static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> > +{
> > +   if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
> > +   return pcie->next_lut_index++;
> > +   else
> > +   return -1;  /* LUT is full */
> > +}
> > +
> > +/*
> > + * Program a single LUT entry
> > + */
> > +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 
> > devid,
> > +u32 streamid)
> > +{
> > +   void __iomem *lut;
> > +
> > +   lut = pcie->dbi + PCIE_LUT_BASE;
> > +
> > +   /* leave mask as all zeroes, want to match all bits */
> > +   writel((devid << 16), lut + PCIE_LUT_UDR(index));
> > +   writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
> > +}
> > +#endif
> > +
> >  int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info 
> > *info)
> >  {
> > struct ls_pcie *pcie;
> > @@ -513,6 +542,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, 
> > struct
> ls_pcie_info *info)
> > pcie->va_cfg1 = map_physmem(info->cfg1_phys,
> > info->cfg1_size,
> > MAP_NOCACHE);
> > +   pcie->next_lut_index = 0;
> >
> > /* outbound memory */
> > pci_set_region(&hose->regions[0],
> >
> 
> Stuart,
> 
> This patch breaks git bisect. Please rearrange your changes.
>  warning: 'ls_pcie_next_lut_index' defined but not used [-Wunused-function]
>  static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
> ^
>  warning: 'ls_pcie_lut_set_mapping' defined but not used [-Wunused-function]
>  static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 
> devid,
>  ^

Ugh...will fix.

Stuart
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Re: [U-Boot] [PATCH v5 24/30] efi_loader: Add distro boot script for removable media

2016-03-09 Thread Tom Rini
On Thu, Mar 10, 2016 at 12:05:12AM +0100, Alexander Graf wrote:
> 
> 
> On 04.03.16 01:10, Alexander Graf wrote:
> > UEFI defines a simple boot protocol for removable media. There we should 
> > look
> > at the EFI (first GPT FAT) partition and search for /efi/boot/bootXXX.efi 
> > with
> > XXX being different between different platforms (x86, x64, arm, aa64, ...).
> > 
> > This patch implements a simple version of that protocol for the default 
> > distro
> > boot script. With this we can automatically boot from valid UEFI enabled
> > removable media.
> > 
> > Because from all I could see U-Boot by default doesn't deliver device tree
> > blobs with its firmware, we also need to load the dtb from somewhere. 
> > Traverse
> > the same EFI partition for an fdt file that fits our current board so that
> > an OS receives a valid device tree when booted automatically.
> > 
> > Signed-off-by: Alexander Graf 
> > Reviewed-by: Simon Glass 
> > ---
> >  include/config_distro_bootcmd.h | 47 
> > -
> >  1 file changed, 46 insertions(+), 1 deletion(-)
> > 
> > diff --git a/include/config_distro_bootcmd.h 
> > b/include/config_distro_bootcmd.h
> > index 37c6b43..c19f1b0 100644
> > --- a/include/config_distro_bootcmd.h
> > +++ b/include/config_distro_bootcmd.h
> > @@ -90,6 +90,48 @@
> > BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
> >  #endif
> >  
> > +#ifdef CONFIG_EFI_LOADER
> > +#if defined(CONFIG_ARM64)
> > +#define BOOTEFI_NAME "bootaa64.efi"
> > +#elif defined(CONFIG_ARM)
> > +#define BOOTEFI_NAME "bootarm.efi"
> > +#endif
> > +#endif
> > +
> > +#ifdef BOOTEFI_NAME
> > +#define BOOTENV_SHARED_EFI\
> > +   "boot_efi_binary="\
> > +   "load ${devtype} ${devnum}:${distro_bootpart} "   \
> > +   "${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "  \
> > +   "bootefi ${kernel_addr_r}\0"  \
> > +   \
> > +   "load_efi_dtb="   \
> > +   "load ${devtype} ${devnum}:${distro_bootpart} "   \
> > +   "${fdt_addr_r} ${prefix}${fdt_name}; "   \
> > +   "fdt addr ${fdt_addr_r}\0"\
> > +   \
> > +   "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"\
> > +   "scan_dev_for_efi="   \
> > +   "for prefix in ${efi_dtb_prefixes}; do "  \
> > +   "if test -e ${devtype} "  \
> > +   "${devnum}:${distro_bootpart} "   \
> > +   "${prefix}${fdt_name}; then " \
> > +   "run load_efi_dtb; "  \
> > +   "fi;" \
> > +   "done;"   \
> > +   "if test -e ${devtype} ${devnum}:${distro_bootpart} " \
> > +   "efi/boot/"BOOTEFI_NAME"; then "  \
> > +   "echo Found EFI removable media binary "  \
> > +   "efi/boot/"BOOTEFI_NAME"; "   \
> > +   "run boot_efi_binary; "   \
> > +   "echo EFI LOAD FAILED: continuing...; "   \
> > +   "fi; "
> 
> Whoever applies this, please also apply the patch below on top and
> squash it in (or tell me to resend). Without the fix, we end up slurping
> the boot_prefix variable into the scan_dev_for_efi variable.
> 
> 
> Alex
> 
> diff --git a/include/config_distro_bootcmd.h
> b/include/config_distro_bootcmd.h
> index e7d7002..ad9045e 100644
> --- a/include/config_distro_bootcmd.h
> +++ b/include/config_distro_bootcmd.h
> @@ -125,7 +125,7 @@
> "efi/boot/"BOOTEFI_NAME"; "   \
> "run boot_efi_binary; "   \
> "echo EFI LOAD FAILED: continuing...; "   \
> -   "fi; "
> +   "fi; \0"
>  #define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
>  #else
>  #define BOOTENV_SHARED_EFI

Please make just a v6 of this patch and re-post, thanks!

-- 
Tom


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[U-Boot] [PATCH v6 24/30] efi_loader: Add distro boot script for removable media

2016-03-09 Thread Alexander Graf
UEFI defines a simple boot protocol for removable media. There we should look
at the EFI (first GPT FAT) partition and search for /efi/boot/bootXXX.efi with
XXX being different between different platforms (x86, x64, arm, aa64, ...).

This patch implements a simple version of that protocol for the default distro
boot script. With this we can automatically boot from valid UEFI enabled
removable media.

Because from all I could see U-Boot by default doesn't deliver device tree
blobs with its firmware, we also need to load the dtb from somewhere. Traverse
the same EFI partition for an fdt file that fits our current board so that
an OS receives a valid device tree when booted automatically.

Signed-off-by: Alexander Graf 
Reviewed-by: Simon Glass 

---

v5 -> v6:

  - Fix missing 0-terminator
---
 include/config_distro_bootcmd.h | 47 -
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 37c6b43..5792d29 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -90,6 +90,48 @@
BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
 #endif
 
+#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_ARM64)
+#define BOOTEFI_NAME "bootaa64.efi"
+#elif defined(CONFIG_ARM)
+#define BOOTEFI_NAME "bootarm.efi"
+#endif
+#endif
+
+#ifdef BOOTEFI_NAME
+#define BOOTENV_SHARED_EFI\
+   "boot_efi_binary="\
+   "load ${devtype} ${devnum}:${distro_bootpart} "   \
+   "${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "  \
+   "bootefi ${kernel_addr_r}\0"  \
+   \
+   "load_efi_dtb="   \
+   "load ${devtype} ${devnum}:${distro_bootpart} "   \
+   "${fdt_addr_r} ${prefix}${fdt_name}; "   \
+   "fdt addr ${fdt_addr_r}\0"\
+   \
+   "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"\
+   "scan_dev_for_efi="   \
+   "for prefix in ${efi_dtb_prefixes}; do "  \
+   "if test -e ${devtype} "  \
+   "${devnum}:${distro_bootpart} "   \
+   "${prefix}${fdt_name}; then " \
+   "run load_efi_dtb; "  \
+   "fi;" \
+   "done;"   \
+   "if test -e ${devtype} ${devnum}:${distro_bootpart} " \
+   "efi/boot/"BOOTEFI_NAME"; then "  \
+   "echo Found EFI removable media binary "  \
+   "efi/boot/"BOOTEFI_NAME"; "   \
+   "run boot_efi_binary; "   \
+   "echo EFI LOAD FAILED: continuing...; "   \
+   "fi; \0"
+#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
+#else
+#define BOOTENV_SHARED_EFI
+#define SCAN_DEV_FOR_EFI
+#endif
+
 #ifdef CONFIG_CMD_SATA
 #define BOOTENV_SHARED_SATABOOTENV_SHARED_BLKDEV(sata)
 #define BOOTENV_DEV_SATA   BOOTENV_DEV_BLKDEV
@@ -217,6 +259,7 @@
BOOTENV_SHARED_SCSI \
BOOTENV_SHARED_IDE \
BOOTENV_SHARED_UBIFS \
+   BOOTENV_SHARED_EFI \
"boot_prefixes=/ /boot/\0" \
"boot_scripts=boot.scr.uimg boot.scr\0" \
"boot_script_dhcp=boot.scr.uimg\0" \
@@ -258,7 +301,9 @@
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_extlinux; " \
"run scan_dev_for_scripts; "  \
-   "done\0"  \
+   "done;"   \
+   SCAN_DEV_FOR_EFI  \
+   "\0"  \
\
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} -bootable devplist; " \
-- 
1.8.5.6

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[U-Boot] [PATCH v6 19/30] efi_loader: Add "bootefi" command

2016-03-09 Thread Alexander Graf
In order to execute an EFI application, we need to bridge the gap between
U-Boot's notion of executing images and EFI's notion of doing the same.

The best path forward IMHO here is to stick completely to the way U-Boot
deals with payloads. You manually load them using whatever method to RAM
and then have a simple boot command to execute them. So in our case, you
would do

  # load mmc 0:1 $loadaddr grub.efi
  # bootefi $loadaddr

which then gets you into a grub shell. Fdt information known to U-boot
via the fdt addr command is also passed to the EFI payload.

Signed-off-by: Alexander Graf 
Reviewed-by: Simon Glass 
Tested-by: Simon Glass 

---

v1 -> v2:

  - Move to GPLv2+

v2 -> v3:

  - Move to new cmd directory
  - Add kconfig option
  - Fix comment style
  - Add help text
  - s/-1/-ENOENT
  - Move obj list to lib

v4 -> v5:

  - Mark fdt memory as boot services data

v5 -> v6:

  - Reserve 2 additional pages for fdt

---
 cmd/Kconfig   |   7 +++
 cmd/Makefile  |   1 +
 cmd/bootefi.c | 180 ++
 3 files changed, 188 insertions(+)
 create mode 100644 cmd/bootefi.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2ed0263..7cdff04 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -148,6 +148,13 @@ config CMD_BOOTM
help
  Boot an application image from the memory.
 
+config CMD_BOOTEFI
+   bool "bootefi"
+   depends on EFI_LOADER
+   default y
+   help
+ Boot an EFI image from memory.
+
 config CMD_ELF
bool "bootelf, bootvx"
default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 03f7e0a..7604621 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CMD_SOURCE) += source.o
 obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
 obj-$(CONFIG_CMD_BMP) += bmp.o
+obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
 obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
 obj-$(CONFIG_CMD_BOOTLDR) += bootldr.o
 obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
new file mode 100644
index 000..38a1b46
--- /dev/null
+++ b/cmd/bootefi.c
@@ -0,0 +1,180 @@
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * When booting using the "bootefi" command, we don't know which
+ * physical device the file came from. So we create a pseudo-device
+ * called "bootefi" with the device path /bootefi.
+ *
+ * In addition to the originating device we also declare the file path
+ * of "bootefi" based loads to be /bootefi.
+ */
+static struct efi_device_path_file_path bootefi_dummy_path[] = {
+   {
+   .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+   .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+   .dp.length = sizeof(bootefi_dummy_path[0]),
+   .str = { 'b','o','o','t','e','f','i' },
+   }, {
+   .dp.type = DEVICE_PATH_TYPE_END,
+   .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+   .dp.length = sizeof(bootefi_dummy_path[0]),
+   }
+};
+
+static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
+   void **protocol_interface, void *agent_handle,
+   void *controller_handle, uint32_t attributes)
+{
+   *protocol_interface = bootefi_dummy_path;
+   return EFI_SUCCESS;
+}
+
+/* The EFI loaded_image interface for the image executed via "bootefi" */
+static struct efi_loaded_image loaded_image_info = {
+   .device_handle = bootefi_dummy_path,
+   .file_path = bootefi_dummy_path,
+};
+
+/* The EFI object struct for the image executed via "bootefi" */
+static struct efi_object loaded_image_info_obj = {
+   .handle = &loaded_image_info,
+   .protocols = {
+   {
+   /*
+* When asking for the loaded_image interface, just
+* return handle which points to loaded_image_info
+*/
+   .guid = &efi_guid_loaded_image,
+   .open = &efi_return_handle,
+   },
+   {
+   /*
+* When asking for the device path interface, return
+* bootefi_dummy_path
+*/
+   .guid = &efi_guid_device_path,
+   .open = &bootefi_open_dp,
+   },
+   },
+};
+
+/* The EFI object struct for the device the "bootefi" image was loaded from */
+static struct efi_object bootefi_device_obj = {
+   .handle = bootefi_dummy_path,
+   .protocols = {
+   {
+   /* When asking for the device path interface, return
+* bootefi_dummy_path */
+   .guid = &efi_guid_device_path,
+   .open = &bootefi_open_dp,
+

Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-09 Thread Marek Vasut
On 03/09/2016 10:40 PM, Dinh Nguyen wrote:
> On 03/09/2016 08:00 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
>> Hi Marek,
>>
>>> Perform usual test, disable cache (dcache off) .
>>
>> I tried and result is still the same.
>>
>> UPD: I did a little trick:
>> 1. I started ping from the board side. That made the board listen to 
>> incoming packets (calling in infinite loop eth_rx() ).
>> 2. Started ping from PC side.
>> 3. In this case board receive ICMP packets from PC:
>>
>> packet received
>> Receive from protocol 0x800
>> Got IP
>> len=60, v=45
>> Got ICMP ECHO REQUEST, return 74 bytes 
>>
>> So, ICMP packets are handled by the board, but ARP packets not.
>>
>> In my understanding it tells me that at least interface on the board side is 
>> alive.
>>
>> I'm now doing some low-level debugging, however I think this is not the best 
>> idea. :)
>> Now dw_eth_recv (designware.c) always returns 0 length of the packet.
>>
> 
> I was able to tftp an kernel image using mainline U-Boot on my Arria5
> board today. However, I wasn't able to dhcp, but I'm not sure if that's
> the board or my network.
> 
> 
> U-Boot 2016.03-rc3-8-g08b2472 (Mar 09 2016 - 13:37:27 -0600)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Arria V, D5, version 0x0
> BOOT:  SD/MMC External Transceiver (1.8V)
>Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   dwmmc0@ff704000: 0
> In:serial
> Out:   serial
> Err:   serial
> Model: Altera SOCFPGA Arria V SoC Development Kit
> Net:   eth0: ethernet@ff702000
> Hit any key to stop autoboot:  0
> => tftp ${loadaddr} zImage
> Speed: 1000, full duplex
> Using ethernet@ff702000 device
> TFTP from server 137.57.160.210; our IP address is 137.57.160.216
> Filename 'zImage'.
> Load address: 0x8000
> Loading:
>  #
>  552.7 KiB/s
> done
> Bytes transferred = 3491984 (354890 hex)
> =>

Thanks for the test!

The speed looks weird, it should be in the 2-3MiB range.

Are you booting using mainline U-Boot SPL ? :-)

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/3] imx: mx6ul_evk: default enable device tree support

2016-03-09 Thread Peng Fan
Hi Fabio,

On Wed, Mar 09, 2016 at 08:48:40AM -0300, Fabio Estevam wrote:
>Hi Peng,
>
>On Wed, Mar 9, 2016 at 3:01 AM, Peng Fan  wrote:
>> Default enable device tree for mx6ul_14x14_evk and
>> mx6ul_9x9_evk board. And sort the defconfig file to be in
>> alphabet order.
>>
>> Enable pinctrl driver for the two boards.
>>
>> Signed-off-by: Peng Fan 
>> Cc: Stefano Babic 
>> Cc: Fabio Estevam 
>
>Shouldn't board/freescale/mx6ul_14x14_evk/README be updated to take
>into account the new new method for flashing the image?

Will update u-boot.img to u-boot-dtb.img.

Wait for more comments on the patch set and will address this in V3.

Actually I am not very sure whether we need to introduce a full device tree
in U-Boot or not. It's too large a file, such as dtsi/clock header/pin header.

I just have an idea to introudce only needed part. Also I do not have
plan to implement a DM clk driver for i.MX, since it's not easy to
do clk management like linux kernel. If follow kernel, and add all the
gates/muxes, it's too complicated a driver, and not easy for us to
do bringup work. So I am thinking whether need to discard the clk
related property in device tree.

Thanks,
Peng.
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[U-Boot] [RESEND 2/2] stm32f746-disco: enable flash support

2016-03-09 Thread Vikas Manocha
This patch enables embedded flash for stm32f746 discovery board.

Signed-off-by: Vikas Manocha 
---
 arch/arm/include/asm/arch-stm32f7/stm32.h |  6 ++
 include/configs/stm32f746-disco.h | 11 ---
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h 
b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 713eb2e..68bdab0 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -50,6 +50,12 @@
 
 #define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A140)
 
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+   [0 ... 3] = 32 * 1024,
+   [4] =   128 * 1024,
+   [5 ... 7] = 256 * 1024
+};
+
 enum clock {
CLOCK_CORE,
CLOCK_AHB,
diff --git a/include/configs/stm32f746-disco.h 
b/include/configs/stm32f746-disco.h
index e1b8bcb..807ab65 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -9,7 +9,7 @@
 #define __CONFIG_H
 
 #define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_SYS_NO_FLASH
+/*#define CONFIG_SYS_NO_FLASH*/
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -33,17 +33,14 @@
 #define CONFIG_SYS_LOAD_ADDR   0x2000
 #define CONFIG_LOADADDR0x2000
 
-#define CONFIG_SYS_MAX_FLASH_SECT  12
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT  8
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_FLASH
-#else
 #define CONFIG_ENV_IS_NOWHERE
-#endif
 #define CONFIG_ENV_SIZE(8 << 10)
 
 #define CONFIG_STM32_GPIO
+#define CONFIG_STM32_FLASH
 #define CONFIG_STM32X7_SERIAL
 
 #define CONFIG_SYS_CLK_FREQ16*1000*1000 /* 180 MHz */
-- 
1.9.1

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[U-Boot] [PATCH 1/2] stm32: stm32f4: move flash driver to mtd driver location

2016-03-09 Thread Vikas Manocha
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.

Signed-off-by: Vikas Manocha 
---
 arch/arm/include/asm/arch-stm32f4/stm32.h  | 31 ++-
 arch/arm/mach-stm32/stm32f4/Makefile   |  2 +-
 arch/arm/mach-stm32/stm32f4/clock.c| 10 +--
 drivers/mtd/Makefile   |  1 +
 .../stm32f4/flash.c => drivers/mtd/stm32_flash.c   | 35 +++---
 drivers/mtd/stm32_flash.h  | 27 +
 include/configs/stm32f429-discovery.h  |  1 +
 include/flash.h|  2 +-
 8 files changed, 59 insertions(+), 50 deletions(-)
 rename arch/arm/mach-stm32/stm32f4/flash.c => drivers/mtd/stm32_flash.c (82%)
 create mode 100644 drivers/mtd/stm32_flash.h

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h 
b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 7d6331b..6cc1966 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -82,16 +82,6 @@ struct stm32_pwr_regs {
u32 csr;
 };
 
-struct stm32_flash_regs {
-   u32 acr;
-   u32 key;
-   u32 optkeyr;
-   u32 sr;
-   u32 cr;
-   u32 optcr;
-   u32 optcr1;
-};
-
 /*
  * Registers access macros
  */
@@ -104,18 +94,6 @@ struct stm32_flash_regs {
 #define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
 #define STM32_PWR  ((struct stm32_pwr_regs *)STM32_PWR_BASE)
 
-#define STM32_FLASH_BASE   (STM32_AHB1PERIPH_BASE + 0x3C00)
-#define STM32_FLASH((struct stm32_flash_regs *)STM32_FLASH_BASE)
-
-#define STM32_FLASH_SR_BSY (1 << 16)
-
-#define STM32_FLASH_CR_PG  (1 << 0)
-#define STM32_FLASH_CR_SER (1 << 1)
-#define STM32_FLASH_CR_STRT(1 << 16)
-#define STM32_FLASH_CR_LOCK(1 << 31)
-#define STM32_FLASH_CR_SNB_OFFSET  3
-#define STM32_FLASH_CR_SNB_MASK(15 << 
STM32_FLASH_CR_SNB_OFFSET)
-
 /*
  * Peripheral base addresses
  */
@@ -124,6 +102,14 @@ struct stm32_flash_regs {
 #define STM32_USART3_BASE  (STM32_APB1PERIPH_BASE + 0x4800)
 #define STM32_USART6_BASE  (STM32_APB2PERIPH_BASE + 0x1400)
 
+#define FLASH_CNTL_BASE(STM32_AHB1PERIPH_BASE + 0x3C00)
+
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+   [0 ... 3] = 16 * 1024,
+   [4] =   64 * 1024,
+   [5 ... 11] =128 * 1024
+};
+
 enum clock {
CLOCK_CORE,
CLOCK_AHB,
@@ -133,5 +119,6 @@ enum clock {
 
 int configure_clocks(void);
 unsigned long clock_get(enum clock clck);
+void stm32_flash_latency_cfg(int latency);
 
 #endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile 
b/arch/arm/mach-stm32/stm32f4/Makefile
index 42d01db..020e783 100644
--- a/arch/arm/mach-stm32/stm32f4/Makefile
+++ b/arch/arm/mach-stm32/stm32f4/Makefile
@@ -8,4 +8,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += soc.o clock.o timer.o flash.o
+obj-y += soc.o clock.o timer.o
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c 
b/arch/arm/mach-stm32/stm32f4/clock.c
index 631f36a..15fcadb 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -66,11 +66,6 @@
 #define PWR_CR_VOS_SCALE_MODE_2(PWR_CR_VOS1)
 #define PWR_CR_VOS_SCALE_MODE_3(PWR_CR_VOS0)
 
-#define FLASH_ACR_WS(n)n
-#define FLASH_ACR_PRFTEN   (1 << 8)
-#define FLASH_ACR_ICEN (1 << 9)
-#define FLASH_ACR_DCEN (1 << 10)
-
 /*
  * RCC GPIO specific definitions
  */
@@ -181,10 +176,7 @@ int configure_clocks(void)
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
 
-   /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-   writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-   | FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
+   stm32_flash_latency_cfg(5);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..703700a 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
+obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
diff --git a/arch/arm/mach-stm32/stm32f4/flash.c b/drivers/mtd/stm32_flash.c
similarity index 82%
rename from arch/arm/mach-stm32/stm32f4/flash.c
rename to drivers/mtd/stm32_flash.c
index a379f47..71f4854 100644
--- a/arch/arm/mach-stm32/stm32f4/flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -8,19 +8,20 @@
 #include 
 #include 
 #include 
-
-#define STM32_FLASH_KEY1   0x45670123
-#define STM32_FLASH_KEY2   0xCDEF89AB
+#include "stm32_flash.h"
 
 flash_info_t flash_info[CONFIG_SYS_

[U-Boot] [PATCH 2/2] stm32f746-disco: enable flash support

2016-03-09 Thread Vikas Manocha
This patch enables embedded flash for stm32f746 discovery board.

Signed-off-by: Vikas Manocha 
---
 arch/arm/include/asm/arch-stm32f7/stm32.h |  6 ++
 include/configs/stm32f746-disco.h | 11 ---
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h 
b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 713eb2e..68bdab0 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -50,6 +50,12 @@
 
 #define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A140)
 
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+   [0 ... 3] = 32 * 1024,
+   [4] =   128 * 1024,
+   [5 ... 7] = 256 * 1024
+};
+
 enum clock {
CLOCK_CORE,
CLOCK_AHB,
diff --git a/include/configs/stm32f746-disco.h 
b/include/configs/stm32f746-disco.h
index e1b8bcb..807ab65 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -9,7 +9,7 @@
 #define __CONFIG_H
 
 #define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_SYS_NO_FLASH
+/*#define CONFIG_SYS_NO_FLASH*/
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -33,17 +33,14 @@
 #define CONFIG_SYS_LOAD_ADDR   0x2000
 #define CONFIG_LOADADDR0x2000
 
-#define CONFIG_SYS_MAX_FLASH_SECT  12
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT  8
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_FLASH
-#else
 #define CONFIG_ENV_IS_NOWHERE
-#endif
 #define CONFIG_ENV_SIZE(8 << 10)
 
 #define CONFIG_STM32_GPIO
+#define CONFIG_STM32_FLASH
 #define CONFIG_STM32X7_SERIAL
 
 #define CONFIG_SYS_CLK_FREQ16*1000*1000 /* 180 MHz */
-- 
1.9.1

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[U-Boot] [RESEND 1/2] stm32: stm32f4: move flash driver to mtd driver location

2016-03-09 Thread Vikas Manocha
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.

Signed-off-by: Vikas Manocha 
---
 arch/arm/include/asm/arch-stm32f4/stm32.h  | 31 ++-
 arch/arm/mach-stm32/stm32f4/Makefile   |  2 +-
 arch/arm/mach-stm32/stm32f4/clock.c| 10 +--
 drivers/mtd/Makefile   |  1 +
 .../stm32f4/flash.c => drivers/mtd/stm32_flash.c   | 35 +++---
 drivers/mtd/stm32_flash.h  | 27 +
 include/configs/stm32f429-discovery.h  |  1 +
 include/flash.h|  2 +-
 8 files changed, 59 insertions(+), 50 deletions(-)
 rename arch/arm/mach-stm32/stm32f4/flash.c => drivers/mtd/stm32_flash.c (82%)
 create mode 100644 drivers/mtd/stm32_flash.h

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h 
b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 7d6331b..6cc1966 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -82,16 +82,6 @@ struct stm32_pwr_regs {
u32 csr;
 };
 
-struct stm32_flash_regs {
-   u32 acr;
-   u32 key;
-   u32 optkeyr;
-   u32 sr;
-   u32 cr;
-   u32 optcr;
-   u32 optcr1;
-};
-
 /*
  * Registers access macros
  */
@@ -104,18 +94,6 @@ struct stm32_flash_regs {
 #define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
 #define STM32_PWR  ((struct stm32_pwr_regs *)STM32_PWR_BASE)
 
-#define STM32_FLASH_BASE   (STM32_AHB1PERIPH_BASE + 0x3C00)
-#define STM32_FLASH((struct stm32_flash_regs *)STM32_FLASH_BASE)
-
-#define STM32_FLASH_SR_BSY (1 << 16)
-
-#define STM32_FLASH_CR_PG  (1 << 0)
-#define STM32_FLASH_CR_SER (1 << 1)
-#define STM32_FLASH_CR_STRT(1 << 16)
-#define STM32_FLASH_CR_LOCK(1 << 31)
-#define STM32_FLASH_CR_SNB_OFFSET  3
-#define STM32_FLASH_CR_SNB_MASK(15 << 
STM32_FLASH_CR_SNB_OFFSET)
-
 /*
  * Peripheral base addresses
  */
@@ -124,6 +102,14 @@ struct stm32_flash_regs {
 #define STM32_USART3_BASE  (STM32_APB1PERIPH_BASE + 0x4800)
 #define STM32_USART6_BASE  (STM32_APB2PERIPH_BASE + 0x1400)
 
+#define FLASH_CNTL_BASE(STM32_AHB1PERIPH_BASE + 0x3C00)
+
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+   [0 ... 3] = 16 * 1024,
+   [4] =   64 * 1024,
+   [5 ... 11] =128 * 1024
+};
+
 enum clock {
CLOCK_CORE,
CLOCK_AHB,
@@ -133,5 +119,6 @@ enum clock {
 
 int configure_clocks(void);
 unsigned long clock_get(enum clock clck);
+void stm32_flash_latency_cfg(int latency);
 
 #endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile 
b/arch/arm/mach-stm32/stm32f4/Makefile
index 42d01db..020e783 100644
--- a/arch/arm/mach-stm32/stm32f4/Makefile
+++ b/arch/arm/mach-stm32/stm32f4/Makefile
@@ -8,4 +8,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += soc.o clock.o timer.o flash.o
+obj-y += soc.o clock.o timer.o
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c 
b/arch/arm/mach-stm32/stm32f4/clock.c
index 631f36a..15fcadb 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -66,11 +66,6 @@
 #define PWR_CR_VOS_SCALE_MODE_2(PWR_CR_VOS1)
 #define PWR_CR_VOS_SCALE_MODE_3(PWR_CR_VOS0)
 
-#define FLASH_ACR_WS(n)n
-#define FLASH_ACR_PRFTEN   (1 << 8)
-#define FLASH_ACR_ICEN (1 << 9)
-#define FLASH_ACR_DCEN (1 << 10)
-
 /*
  * RCC GPIO specific definitions
  */
@@ -181,10 +176,7 @@ int configure_clocks(void)
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
 
-   /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-   writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-   | FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
+   stm32_flash_latency_cfg(5);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 7f018a4..703700a 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
+obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
diff --git a/arch/arm/mach-stm32/stm32f4/flash.c b/drivers/mtd/stm32_flash.c
similarity index 82%
rename from arch/arm/mach-stm32/stm32f4/flash.c
rename to drivers/mtd/stm32_flash.c
index a379f47..71f4854 100644
--- a/arch/arm/mach-stm32/stm32f4/flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -8,19 +8,20 @@
 #include 
 #include 
 #include 
-
-#define STM32_FLASH_KEY1   0x45670123
-#define STM32_FLASH_KEY2   0xCDEF89AB
+#include "stm32_flash.h"
 
 flash_info_t flash_info[CONFIG_SYS_

Re: [U-Boot] [RESEND 1/2] stm32: stm32f4: move flash driver to mtd driver location

2016-03-09 Thread Jagan Teki

On Thursday 10 March 2016 04:48 AM, Vikas Manocha wrote:

Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.


What kind of flash is it, parallel or serial NOR?



Signed-off-by: Vikas Manocha 
---
  arch/arm/include/asm/arch-stm32f4/stm32.h  | 31 ++-
  arch/arm/mach-stm32/stm32f4/Makefile   |  2 +-
  arch/arm/mach-stm32/stm32f4/clock.c| 10 +--
  drivers/mtd/Makefile   |  1 +
  .../stm32f4/flash.c => drivers/mtd/stm32_flash.c   | 35 +++---
  drivers/mtd/stm32_flash.h  | 27 +
  include/configs/stm32f429-discovery.h  |  1 +
  include/flash.h|  2 +-
  8 files changed, 59 insertions(+), 50 deletions(-)
  rename arch/arm/mach-stm32/stm32f4/flash.c => drivers/mtd/stm32_flash.c (82%)
  create mode 100644 drivers/mtd/stm32_flash.h


--
Jagan.
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Re: [U-Boot] [RESEND 1/2] stm32: stm32f4: move flash driver to mtd driver location

2016-03-09 Thread Vikas MANOCHA
Hi Jagan ,

> On Mar 9, 2016, at 6:53 PM, Jagan Teki  wrote:
> 
>> On Thursday 10 March 2016 04:48 AM, Vikas Manocha wrote:
>> Same flash driver can be used by other stm32 families like stm32f7.
>> Better place for this driver would be mtd driver location.
> 
> What kind of flash is it, parallel or serial NOR?

It is embedded 256 bit NOR flash.

Cheers,
Vikas 

> 
>> 
>> Signed-off-by: Vikas Manocha 
>> ---
>>  arch/arm/include/asm/arch-stm32f4/stm32.h  | 31 ++-
>>  arch/arm/mach-stm32/stm32f4/Makefile   |  2 +-
>>  arch/arm/mach-stm32/stm32f4/clock.c| 10 +--
>>  drivers/mtd/Makefile   |  1 +
>>  .../stm32f4/flash.c => drivers/mtd/stm32_flash.c   | 35 
>> +++---
>>  drivers/mtd/stm32_flash.h  | 27 +
>>  include/configs/stm32f429-discovery.h  |  1 +
>>  include/flash.h|  2 +-
>>  8 files changed, 59 insertions(+), 50 deletions(-)
>>  rename arch/arm/mach-stm32/stm32f4/flash.c => drivers/mtd/stm32_flash.c 
>> (82%)
>>  create mode 100644 drivers/mtd/stm32_flash.h
> 
> --
> Jagan.
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Re: [U-Boot] [RESEND 1/2] stm32: stm32f4: move flash driver to mtd driver location

2016-03-09 Thread jteki

On 2016-03-09 23:18, Vikas MANOCHA wrote:

Hi Jagan ,


On Mar 9, 2016, at 6:53 PM, Jagan Teki  wrote:


On Thursday 10 March 2016 04:48 AM, Vikas Manocha wrote:
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.


What kind of flash is it, parallel or serial NOR?


It is embedded 256 bit NOR flash.


OK, I thought it's similar to SST25L.

Can't we detect this through cfi_flash framework?

--
Jagan.

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Re: [U-Boot] [PATCH] armv8/fsl-lsch2: fix sdhc clock frequency value

2016-03-09 Thread Yangbo Lu
> -Original Message-
> From: york sun
> Sent: Tuesday, March 08, 2016 3:07 AM
> To: Yangbo Lu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/fsl-lsch2: fix sdhc clock frequency value
> 
> On 02/15/2016 07:03 PM, Yangbo Lu wrote:
> > The eSDHC could select to use platform clock or peripheral clock to
> > generate SD clock. The default selection is platform clock. So, fix
> > the clock frequency value that's calculated for eSDHC.
> >
> > Signed-off-by: Yangbo Lu 
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > index 6f6a588..453a93d 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > @@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
> >  #define HWA_CGA_M2_CLK_SEL 0x0007
> >  #define HWA_CGA_M2_CLK_SHIFT   0
> >  #ifdef CONFIG_FSL_ESDHC
> > +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> > rcw_tmp = in_be32(&gur->rcwsr[15]);
> > rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
> > sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
> > +#else
> > +   sys_info->freq_sdhc = sys_info->freq_systembus; #endif
> >  #endif
> >
> >  #if defined(CONFIG_FSL_IFC)
> >
> 
> Yango,
> 
> The change looks OK. But you didn't define
> CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> anywhere. Do you have another patch using this macro? So far, this macro
> is only used for T1040QDS and T208xQDS.
> 
> York

[Lu Yangbo-B47093] Hi York. You are right.
Although we don't use this macro presently, we will use it to support SD UHS 
mode in the future.
Now we could treat it as a bug fix.

Thanks. 
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