If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.
Signed-off-by: Peng Fan <van.free...@gmail.com>
Signed-off-by: Sandor Yu <sandor...@nxp.com>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@nxp.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a34675c..91a3deb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -548,7 +548,8 @@ void imx_setup_hdmi(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- int reg;
+ int reg, count;
+ u8 val;
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
@@ -565,6 +566,16 @@ void imx_setup_hdmi(void)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+ /* Clear the overflow condition */
+ if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
+ /* TMDS software reset */
+ writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
+ val = readb(&hdmi->fc_invidconf);
+ /* Need minimum 3 times to write to clear the register */
+ for (count = 0 ; count < 5 ; count++)
+ writeb(val, &hdmi->fc_invidconf);
+ }
}
#endif
--
2.6.2
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