Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
Dear Bo Shen,
On 02.07.12 05:35, Bo Shen wrote:
> Add at91sam9x5ek board support, this board support the following SoCs
> AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
>
> Using at91sam9x5ek_nandflash to configure for the board
> Now only supports NAND with software ECC boot up
>
> This patch is based on git://git.denx.de/u-boot-atmel.git
Please place this in comment section (after '---').
>
> Signed-off-by: Bo Shen
> ---
> Changed since v1
> Modify the code according to Andreas's suggestion
> ---
> MAINTAINERS|3 +
> arch/arm/cpu/arm926ejs/at91/Makefile |1 +
> arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 237 +++
> arch/arm/cpu/arm926ejs/at91/clock.c|7 +-
> arch/arm/include/asm/arch-at91/at91sam9_matrix.h |2 +
> arch/arm/include/asm/arch-at91/at91sam9x5.h| 172 +++
> arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | 91 ++
> arch/arm/include/asm/arch-at91/hardware.h |2 +
> board/atmel/at91sam9x5ek/Makefile | 48 +++
> board/atmel/at91sam9x5ek/at91sam9x5ek.c| 306
>
> board/atmel/at91sam9x5ek/config.mk |1 +
> boards.cfg |1 +
> drivers/net/macb.c |4 +-
> drivers/serial/atmel_usart.h |7 +-
> include/configs/at91sam9x5ek.h | 201 +
> 15 files changed, 1077 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
> create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5.h
> create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
> create mode 100644 board/atmel/at91sam9x5ek/Makefile
> create mode 100644 board/atmel/at91sam9x5ek/at91sam9x5ek.c
> create mode 100644 board/atmel/at91sam9x5ek/config.mk
> create mode 100644 include/configs/at91sam9x5ek.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6438e1c..a2fccbf 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -660,6 +660,9 @@ Sedji Gaouaou
> at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
> at91sam9m10g45ekARM926EJS (AT91SAM9G45 SoC)
>
> +Bo Shen
> + at91sam9x5ekARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
> +
> Simon Guinot
>
> inetspace_v2ARM926EJS (Kirkwood SoC)
> diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile
> b/arch/arm/cpu/arm926ejs/at91/Makefile
> index f333753..346e58f 100644
> --- a/arch/arm/cpu/arm926ejs/at91/Makefile
> +++ b/arch/arm/cpu/arm926ejs/at91/Makefile
> @@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
> COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
> COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
> COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
> +COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
> COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
> COBJS-$(CONFIG_AT91_LED) += led.o
> COBJS-y += clock.o
> diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
> b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
> new file mode 100644
> index 000..2c99a4e
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
> @@ -0,0 +1,237 @@
> +/*
> + * Copyright (C) 2012 Atmel Corporation
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include <../drivers/serial/atmel_usart.h>
> +
> +unsigned int get_chip_id(void)
> +{
> + atmel_usart3_t *dbgu = (atmel_usart3_t *)ATMEL_BASE_DBGU;
> +
> + /* cidr is the same location with fidi */
> + return readl(&dbgu->fidi) & ~AT91_CIDR_VERSION;
> +}
> +
> +unsigned int get_extension_chip_id(void)
> +{
> + atmel_usart3_t *dbgu = (struct atmel_usart3_t *)ATMEL_BASE_DBGU;
please use always the struct or leave it always, but not mixing the styles.
> +
> + /* ner is the same location with fidi */
> + return readl(&dbgu->ner);
> +}
NAK, I count this worse than before.
a) including relative path
b) cidr == fidi && ne
Re: [U-Boot] i.MX6Q SabreLite: Ethernet does not work at Gigabit speed
Hi Troy, On 06/28/2012 07:48 PM, Troy Kisky wrote: > On 6/28/2012 8:33 AM, Eric Nelson wrote: >> On 06/28/2012 06:50 AM, Wolfgang Grandegger wrote: >>> Hi, >>> >>> I just realized that I cannot download files on a Gitabit Ethernet >>> network. I'm getting timeouts: >>> >>>MX6QSABRELITE U-Boot> boot >>>Using FEC device >>>TFTP from server 172.16.0.1; our IP address is 172.16.0.100 >>>Filename 'wolf/uImage-mx6q-mainline'. >>>Load address: 0x1080 >>>Loading: error frame: 0x4fd76ca0 0x0804 >>>T error frame: 0x4fd77f00 0x0804 >>> >>> >>> Before I start digging, is this a known issue? > Also, I recently posted a patch for mainline u-boot. > I'll repost with you and Joe Hershberger in cc. Thanks for the patch. It help to some extend but I'm still getting timeouts. I need to fix the hardware as well, as Eric suggested. Wolfgang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
Hi Andreas,
On 7/2/2012 15:01, Andreas Bießmann wrote:
Dear Bo Shen,
On 02.07.12 05:35, Bo Shen wrote:
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
This patch is based on git://git.denx.de/u-boot-atmel.git
Please place this in comment section (after '---').
ok.
Signed-off-by: Bo Shen
---
Changed since v1
Modify the code according to Andreas's suggestion
---
MAINTAINERS|3 +
arch/arm/cpu/arm926ejs/at91/Makefile |1 +
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 237 +++
arch/arm/cpu/arm926ejs/at91/clock.c|7 +-
arch/arm/include/asm/arch-at91/at91sam9_matrix.h |2 +
arch/arm/include/asm/arch-at91/at91sam9x5.h| 172 +++
arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | 91 ++
arch/arm/include/asm/arch-at91/hardware.h |2 +
board/atmel/at91sam9x5ek/Makefile | 48 +++
board/atmel/at91sam9x5ek/at91sam9x5ek.c| 306
board/atmel/at91sam9x5ek/config.mk |1 +
boards.cfg |1 +
drivers/net/macb.c |4 +-
drivers/serial/atmel_usart.h |7 +-
include/configs/at91sam9x5ek.h | 201 +
15 files changed, 1077 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5.h
create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
create mode 100644 board/atmel/at91sam9x5ek/Makefile
create mode 100644 board/atmel/at91sam9x5ek/at91sam9x5ek.c
create mode 100644 board/atmel/at91sam9x5ek/config.mk
create mode 100644 include/configs/at91sam9x5ek.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6438e1c..a2fccbf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -660,6 +660,9 @@ Sedji Gaouaou
at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
at91sam9m10g45ekARM926EJS (AT91SAM9G45 SoC)
+Bo Shen
+ at91sam9x5ekARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+
Simon Guinot
inetspace_v2ARM926EJS (Kirkwood SoC)
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile
b/arch/arm/cpu/arm926ejs/at91/Makefile
index f333753..346e58f 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
COBJS-$(CONFIG_AT91SAM9RL)+= at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45)+= at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
COBJS-y += clock.o
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
new file mode 100644
index 000..2c99a4e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include <../drivers/serial/atmel_usart.h>
+
+unsigned int get_chip_id(void)
+{
+ atmel_usart3_t *dbgu = (atmel_usart3_t *)ATMEL_BASE_DBGU;
+
+ /* cidr is the same location with fidi */
+ return readl(&dbgu->fidi) & ~AT91_CIDR_VERSION;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ atmel_usart3_t *dbgu = (struct atmel_usart3_t *)ATMEL_BASE_DBGU;
please use always the struct or leave it always, but not mixing the styles.
+
+ /* ner is the same location with fidi */
+ return readl(&dbgu->ner);
+}
NAK, I count this worse than before.
a) including relative path
b) cidr == fidi && ner == fidi ??; how about exid?
c) struct atmel_usart3_t has same footprint in view of USART, but
Re: [U-Boot] [PATCH v2 0/3] Bug fixes for LaCie devices
On Thu, Jun 14, 2012 at 08:18:33AM -0700, Prafulla Wadaskar wrote: > > > > -Original Message- > > From: Simon Guinot [mailto:si...@sequanux.org] > > Sent: 14 June 2012 20:41 > > To: Simon Guinot > > Cc: Prafulla Wadaskar; u-boot@lists.denx.de > > Subject: Re: [U-Boot] [PATCH v2 0/3] Bug fixes for LaCie devices > > > > On Wed, Jun 06, 2012 at 01:15:57AM +0200, Simon Guinot wrote: > > > This patch series provides bug fixes for LaCie devices (mostly for > > > Internet Space v2 and 2Big Network v2). > > > > > > Changes for v2: > > > - Move bug fixes into a separate patch set. > > > > > > Simon Guinot (3): > > > lacie_kw: fix SDRAM banks number for net2big_v2 > > > lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2 > > > ARM: don't probe PHY address for LaCie boards > > > > > > board/LaCie/common/common.c | 23 +++--- > > - > > > board/LaCie/common/common.h |2 +- > > > board/LaCie/edminiv2/edminiv2.c |2 +- > > > board/LaCie/net2big_v2/net2big_v2.c |2 +- > > > board/LaCie/netspace_v2/netspace_v2.c |2 +- > > > include/configs/lacie_kw.h|6 +- > > > 6 files changed, 12 insertions(+), 25 deletions(-) > > > > Hi Prafulla, > > > > Please could you pick this patches ? > > > > Sure, I will do it. Hopefully by tomorrow Hi Prafulla, There is something more I can do to make this happen ? Simon signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: armv7: add compile option -mno-unaligned-access if available
Recent compiler generates unaligned memory access in armv7 default. But current U-Boot does not allow unaligned memory access, so it causes data abort exception. This patch add compile option "-mno-unaligned-access" if it is available. Signed-off-by: Tetsuyuki Kobayashi --- arch/arm/cpu/armv7/config.mk |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 5407cb6..560c084 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -26,6 +26,8 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # supported by more tool-chains PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) +PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED) # = # -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
On 02.07.2012 10:36, Bo Shen wrote:
> Hi Andreas,
>
> On 7/2/2012 15:01, Andreas Bießmann wrote:
>> Dear Bo Shen,
>>
>> On 02.07.12 05:35, Bo Shen wrote:
>>> diff --git a/drivers/serial/atmel_usart.h b/drivers/serial/atmel_usart.h
>>> index 7e4b2c9..ad1d9f0 100644
>>> --- a/drivers/serial/atmel_usart.h
>>> +++ b/drivers/serial/atmel_usart.h
>>> @@ -37,8 +37,8 @@ typedef struct atmel_usart3 {
>>> u32rtor;
>>> u32ttgr;
>>> u32reserved0[5];
>>> -u32fidi;
>>> -u32ner;
>>> +u32fidi;/* cidr for dbgu */
>>> +u32ner;/* exid for dbgu */
>> NAK
>>
>>> u32reserved1;
>>> u32ifr;
>>> u32man;
>>> @@ -289,6 +289,9 @@ typedef struct atmel_usart3 {
>>> /* Constants for FI_DI_RATIO */
>>> #define USART3_FI_DI_RATIO_DISABLE0
>>>
>>> +/* chip revision mask */
>>> +#define AT91_CIDR_VERSION0x1f
>>> +
>> NAK, this belongs to DBGU and not to USART. I think one of the specific
>> hardware.h would be a good place for that.
>
> I will move it into at91sam9x5.h file.
can we use something like AT91_CIDR_VERSION_MASK or
ATMEL_CIDR_VERSION_MASK? I guess this is in every DBGU integrated and
could later be used to identify different atmel devices.
>>
>>> +#define CONFIG_MACB_SEARCH_PHY
>>> +
>>> +#define CONFIG_SYS_LOAD_ADDR0x2200/* load address */
>>> +
>>> +#define CONFIG_SYS_MEMTEST_STARTCONFIG_SYS_SDRAM_BASE
>>> +#define CONFIG_SYS_MEMTEST_END0x26e0
>>> +
>>> +#ifdef CONFIG_SYS_USE_DATAFLASH
>>
>> dataflash is not implemented currently, is it?
>
> Yes. At this stage, it doesn't implement yet.
Ok, so can you remove it here and add it when you implement dataflash
support?
>
>>
>>> +
>>> +/* bootstrap + u-boot + env + linux in dataflash on CS0 */
>>> +#define CONFIG_ENV_IS_IN_SPI_FLASH
>>> +#define CONFIG_SYS_MONITOR_BASE(0x1000 + 0x8400)
>>> +#define CONFIG_ENV_OFFSET0x5000
>>> +#define CONFIG_ENV_ADDR(0x1000 + CONFIG_ENV_OFFSET)
>>> +#define CONFIG_ENV_SIZE0x3000
>>> +#define CONFIG_ENV_SECT_SIZE0x1000
>>> +#define CONFIG_BOOTCOMMAND"sf probe 0; " \
>>> +"sf read 0x2200 0x42000 0x30; " \
>>> +"bootm 0x2200"
>>> +#else /* CONFIG_SYS_USE_NANDFLASH */
>>> +
>>> +/* bootstrap + u-boot + env + linux in nandflash */
>>> +#define CONFIG_ENV_IS_IN_NAND
>>> +#define CONFIG_ENV_OFFSET0xc
>>> +#define CONFIG_ENV_OFFSET_REDUND0x10
>>> +#define CONFIG_ENV_SIZE0x2/* 1 sector = 128 kB */
>>> +#define CONFIG_BOOTCOMMAND"nand read.jffs2 " \
>>> +"0x2200 0x20 0x30; " \
>>> +"bootm 0x2200"
>>
>> Well, you read from jffs but work with ubifs later on? Is that ok?
>> BTW: I do not know 'nand read.jffs2', does this subcommand exist really?
>
> Using the read with subfix .jffs2 it to skip the bad block. This
> partition is for Linux kernel.
> I will remove the .jffs2 to avoid confusing.
Well, it is ok with me to use read.jffs2 (if it works). I just do not
know about that subcommand and I can only find some references about
that in two other boards. I guess these boards are just forgotten while
removing the 'nand read.jffs2' command. Please check, if that command
works, if yes let it as is, if not rewrite.
Best regards
Andreas Bießmann
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Re: [U-Boot] [PATCH 04/10 V4] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
2012/6/29 Rajeshwari Shinde : > Define additional registers for clock control in Exynos5250 Rev 1.0 > > Signed-off-by: Hatim Ali > Signed-off-by: Rajeshwari Shinde > --- > Changes in V2: > - None > Changes in V3: > - Modified Clocks as per Exynos5250 Rev 1.0. > Changes in V4: > - None > arch/arm/include/asm/arch-exynos/clock.h | 234 > -- > 1 files changed, 126 insertions(+), 108 deletions(-) Acked-by: Joonyoung Shim -- - Joonyoung Shim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 08/10 V4] EXYNOS5: CLOCK: Add BPLL support
2012/6/29 Rajeshwari Shinde : > This patch adds support for BPLL clock. > > Signed-off-by: Rajeshwari Shinde > --- > Changes in V3: > - New Patch > Changes in V4: > - Removed the warning message. > arch/arm/cpu/armv7/exynos/clock.c | 26 -- > arch/arm/include/asm/arch-exynos/clk.h | 1 + > arch/arm/include/asm/arch-exynos/clock.h | 2 ++ > 3 files changed, 23 insertions(+), 6 deletions(-) > Acked-by: Joonyoung Shim -- - Joonyoung Shim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/10 V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
2012/6/29 Rajeshwari Shinde :
> MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
> Adjust the divisor value to get 800MHz as needed by devices
> like UART etc
>
> Signed-off-by: Hatim Ali
> Signed-off-by: Rajeshwari Shinde
> ---
> Changes in V2:
> - None
> Changes in V3:
> - Incorported review comments from Minkyu Kang.
> Changes in V4:
> - None
> arch/arm/cpu/armv7/exynos/clock.c | 12 +++-
> arch/arm/include/asm/arch-exynos/clock.h | 3 +++
> 2 files changed, 14 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 330bd75..dbd5f11 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> unsigned long r, m, p, s, k = 0, mask, fout;
> - unsigned int freq;
> + unsigned int freq, pll_div2_sel, mpll_fout_sel;
>
> switch (pllreg) {
> case APLL:
> @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> fout = m * (freq / (p * (1 << (s - 1;
> }
>
> + /* According to the user manual, in EVT1 MPLL always gives
> + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
> + if (pllreg == MPLL) {
> + pll_div2_sel = readl(&clk->pll_div2_sel);
> + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> + & MPLL_FOUT_SEL_MASK;
> + if (mpll_fout_sel == 0)
> + fout /= 2;
> + }
> +
> return fout;
> }
>
> diff --git a/arch/arm/include/asm/arch-exynos/clock.h
> b/arch/arm/include/asm/arch-exynos/clock.h
> index 90271f1..bf41c19 100644
> --- a/arch/arm/include/asm/arch-exynos/clock.h
> +++ b/arch/arm/include/asm/arch-exynos/clock.h
> @@ -596,4 +596,7 @@ struct exynos5_clock {
> unsigned char res123[0xf5d8];
> };
> #endif
> +
> +#define MPLL_FOUT_SEL_SHIFT 4
> +#define MPLL_FOUT_SEL_MASK 0x1
> #endif
> --
> 1.7.4.4
>
Acked-by: Joonyoung Shim
--
- Joonyoung Shim
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Re: [U-Boot] [PATCH 09/10 V4] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
2012/6/29 Rajeshwari Shinde : > This patch modifies the pinmux settings of MMC and UART as per > Exynos5250 Rev 1.0. > It also corrects the gpio offset calculations. > > Signed-off-by: Rajeshwari Shinde > --- > Changes in V2: > - None. > Changes in V3: > - Corrected the pinmux settings and offset calcuation of gpio banks. > Changes in V4: > - None > arch/arm/cpu/armv7/exynos/pinmux.c | 22 +- > arch/arm/include/asm/arch-exynos/gpio.h | 7 +-- > 2 files changed, 18 insertions(+), 11 deletions(-) > Acked-by: Joonyoung Shim -- - Joonyoung Shim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
On 07/02/2012 11:47 AM, Andreas Bießmann : > On 02.07.2012 10:36, Bo Shen wrote: [..] +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET0xc +#define CONFIG_ENV_OFFSET_REDUND0x10 +#define CONFIG_ENV_SIZE0x2/* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND"nand read.jffs2 " \ +"0x2200 0x20 0x30; " \ +"bootm 0x2200" >>> >>> Well, you read from jffs but work with ubifs later on? Is that ok? >>> BTW: I do not know 'nand read.jffs2', does this subcommand exist really? >> >> Using the read with subfix .jffs2 it to skip the bad block. This >> partition is for Linux kernel. >> I will remove the .jffs2 to avoid confusing. > > Well, it is ok with me to use read.jffs2 (if it works). I just do not > know about that subcommand and I can only find some references about > that in two other boards. I guess these boards are just forgotten while > removing the 'nand read.jffs2' command. Please check, if that command > works, if yes let it as is, if not rewrite. I am in favor of using read.jffs2 because it is able to skip bad blocks. As the programming tool is also skipping bad blocks the same way, we have a configuration that is perfectly working even in case of bad block in the middle of the kernel image. So please, keep using read.jffs2 (or equivalent)! Best regards, -- Nicolas Ferre ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
Dear all, On 02.07.2012 11:53, Nicolas Ferre wrote: > On 07/02/2012 11:47 AM, Andreas Bießmann : >> On 02.07.2012 10:36, Bo Shen wrote: > > [..] > > +/* bootstrap + u-boot + env + linux in nandflash */ > +#define CONFIG_ENV_IS_IN_NAND > +#define CONFIG_ENV_OFFSET0xc > +#define CONFIG_ENV_OFFSET_REDUND0x10 > +#define CONFIG_ENV_SIZE0x2/* 1 sector = 128 kB */ > +#define CONFIG_BOOTCOMMAND"nand read.jffs2 " \ > +"0x2200 0x20 0x30; " \ > +"bootm 0x2200" Well, you read from jffs but work with ubifs later on? Is that ok? BTW: I do not know 'nand read.jffs2', does this subcommand exist really? >>> >>> Using the read with subfix .jffs2 it to skip the bad block. This >>> partition is for Linux kernel. >>> I will remove the .jffs2 to avoid confusing. >> >> Well, it is ok with me to use read.jffs2 (if it works). I just do not >> know about that subcommand and I can only find some references about >> that in two other boards. I guess these boards are just forgotten while >> removing the 'nand read.jffs2' command. Please check, if that command >> works, if yes let it as is, if not rewrite. > > I am in favor of using read.jffs2 because it is able to skip bad blocks. > As the programming tool is also skipping bad blocks the same way, we > have a configuration that is perfectly working even in case of bad block > in the middle of the kernel image. > > So please, keep using read.jffs2 (or equivalent)! I have the same opinion here, we should skip bad blocks. But I think 'nand read.jffs2' is not available any longer. from current common/cmd_nand.c: ---8<--- "nand read - addr off|partition size\n" "nand write - addr off|partition size\n" "read/write 'size' bytes starting at offset 'off'\n" "to/from memory address 'addr', skipping bad blocks.\n" "nand read.raw - addr off|partition [count]\n" "nand write.raw - addr off|partition [count]\n" "Use read.raw/write.raw to avoid ECC and access the flash as-is.\n" --->8--- Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
On 07/02/2012 12:02 PM, Andreas Bießmann : > Dear all, > > On 02.07.2012 11:53, Nicolas Ferre wrote: >> On 07/02/2012 11:47 AM, Andreas Bießmann : >>> On 02.07.2012 10:36, Bo Shen wrote: >> >> [..] >> >> +/* bootstrap + u-boot + env + linux in nandflash */ >> +#define CONFIG_ENV_IS_IN_NAND >> +#define CONFIG_ENV_OFFSET0xc >> +#define CONFIG_ENV_OFFSET_REDUND0x10 >> +#define CONFIG_ENV_SIZE0x2/* 1 sector = 128 kB */ >> +#define CONFIG_BOOTCOMMAND"nand read.jffs2 " \ >> +"0x2200 0x20 0x30; " \ >> +"bootm 0x2200" > > Well, you read from jffs but work with ubifs later on? Is that ok? > BTW: I do not know 'nand read.jffs2', does this subcommand exist really? Using the read with subfix .jffs2 it to skip the bad block. This partition is for Linux kernel. I will remove the .jffs2 to avoid confusing. >>> >>> Well, it is ok with me to use read.jffs2 (if it works). I just do not >>> know about that subcommand and I can only find some references about >>> that in two other boards. I guess these boards are just forgotten while >>> removing the 'nand read.jffs2' command. Please check, if that command >>> works, if yes let it as is, if not rewrite. >> >> I am in favor of using read.jffs2 because it is able to skip bad blocks. >> As the programming tool is also skipping bad blocks the same way, we >> have a configuration that is perfectly working even in case of bad block >> in the middle of the kernel image. >> >> So please, keep using read.jffs2 (or equivalent)! > > I have the same opinion here, we should skip bad blocks. But I think > 'nand read.jffs2' is not available any longer. > > from current common/cmd_nand.c: > ---8<--- > "nand read - addr off|partition size\n" > "nand write - addr off|partition size\n" > "read/write 'size' bytes starting at offset 'off'\n" > "to/from memory address 'addr', skipping bad blocks.\n" > "nand read.raw - addr off|partition [count]\n" > "nand write.raw - addr off|partition [count]\n" > "Use read.raw/write.raw to avoid ECC and access the flash as-is.\n" > --->8--- ..." skipping bad blocks."... So it seems that simple "nand read/write" is what we are looking for... in comparison with read.raw/write.raw. Fair enough: nand read/write is the way to go, now. Thanks, best regards, -- Nicolas Ferre ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 08/10 V4] EXYNOS5: CLOCK: Add BPLL support
Dear Rajeshwari Shinde,
On 29 June 2012 21:59, Rajeshwari Shinde wrote:
> This patch adds support for BPLL clock.
>
> Signed-off-by: Rajeshwari Shinde
> ---
> Changes in V3:
> - New Patch
> Changes in V4:
> - Removed the warning message.
> arch/arm/cpu/armv7/exynos/clock.c | 26 --
> arch/arm/include/asm/arch-exynos/clk.h | 1 +
> arch/arm/include/asm/arch-exynos/clock.h | 2 ++
> 3 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index dbd5f11..13e3641 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> unsigned long r, m, p, s, k = 0, mask, fout;
> - unsigned int freq, pll_div2_sel, mpll_fout_sel;
> + unsigned int freq, pll_div2_sel, fout_sel;
>
> switch (pllreg) {
> case APLL:
> @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> r = readl(&clk->vpll_con0);
> k = readl(&clk->vpll_con1);
> break;
> + case BPLL:
> + r = readl(&clk->bpll_con0);
> + break;
> default:
> printf("Unsupported PLL (%d)\n", pllreg);
> return 0;
> @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> * MPLL_CON: MIDV [25:16]
> * EPLL_CON: MIDV [24:16]
> * VPLL_CON: MIDV [24:16]
> + * BPLL_CON: MIDV [25:16]
> */
> - if (pllreg == APLL || pllreg == MPLL)
> + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> mask = 0x3ff;
> else
> mask = 0x1ff;
> @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> fout = m * (freq / (p * (1 << (s - 1;
> }
>
> - /* According to the user manual, in EVT1 MPLL always gives
> + /* According to the user manual, in EVT1 MPLL and BPLL always gives
> * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
> - if (pllreg == MPLL) {
> + if (pllreg == MPLL || pllreg == BPLL) {
> pll_div2_sel = readl(&clk->pll_div2_sel);
> - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> +
> + switch (pllreg) {
> + case MPLL:
> + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> & MPLL_FOUT_SEL_MASK;
> - if (mpll_fout_sel == 0)
> + break;
> + case BPLL:
> + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
> + & BPLL_FOUT_SEL_MASK;
> + break;
> + }
indentation error.
please fix it.
> +
> + if (fout_sel == 0)
> fout /= 2;
> }
>
Thanks.
Minkyu Kang.
--
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Re: [U-Boot] [PATCH v2] arm : Atmel : add at91sam9x5ek board support
Dear all, On 02.07.2012 12:02, Andreas Bießmann wrote: > Dear all, > > On 02.07.2012 11:53, Nicolas Ferre wrote: >> On 07/02/2012 11:47 AM, Andreas Bießmann : >>> On 02.07.2012 10:36, Bo Shen wrote: >> >> [..] >> >> +/* bootstrap + u-boot + env + linux in nandflash */ >> +#define CONFIG_ENV_IS_IN_NAND >> +#define CONFIG_ENV_OFFSET0xc >> +#define CONFIG_ENV_OFFSET_REDUND0x10 >> +#define CONFIG_ENV_SIZE0x2/* 1 sector = 128 kB */ >> +#define CONFIG_BOOTCOMMAND"nand read.jffs2 " \ >> +"0x2200 0x20 0x30; " \ >> +"bootm 0x2200" > > Well, you read from jffs but work with ubifs later on? Is that ok? > BTW: I do not know 'nand read.jffs2', does this subcommand exist really? Using the read with subfix .jffs2 it to skip the bad block. This partition is for Linux kernel. I will remove the .jffs2 to avoid confusing. >>> >>> Well, it is ok with me to use read.jffs2 (if it works). I just do not >>> know about that subcommand and I can only find some references about >>> that in two other boards. I guess these boards are just forgotten while >>> removing the 'nand read.jffs2' command. Please check, if that command >>> works, if yes let it as is, if not rewrite. >> >> I am in favor of using read.jffs2 because it is able to skip bad blocks. >> As the programming tool is also skipping bad blocks the same way, we >> have a configuration that is perfectly working even in case of bad block >> in the middle of the kernel image. >> >> So please, keep using read.jffs2 (or equivalent)! > > I have the same opinion here, we should skip bad blocks. But I think > 'nand read.jffs2' is not available any longer. > > from current common/cmd_nand.c: > ---8<--- > "nand read - addr off|partition size\n" > "nand write - addr off|partition size\n" > "read/write 'size' bytes starting at offset 'off'\n" > "to/from memory address 'addr', skipping bad blocks.\n" > "nand read.raw - addr off|partition [count]\n" > "nand write.raw - addr off|partition [count]\n" > "Use read.raw/write.raw to avoid ECC and access the flash as-is.\n" > --->8--- Ok, some investigation showed up that a) the default read/write should skip bad blocks since 984e03cdf1431bb593aeaa1b74c445d616f955d3 (mid of 2008!) b) the .jffs2 subcommand is still available, but not in the help -> in line 645: if (!s || !strcmp(s, ".jffs2") || Since the read.jffs2 seems to be a leftover from older days I tend to use just 'nand read' here. But as said before, I will also take the 'nand read.jffs2' if it works. My first objection was that I doubt it works at all. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/8] video: support newly exynos5 display feature
This patch set supports newly exynos5 display features. [1/8] EXYNOS5: support exynos5 lcd clock control [2/8] EXYNOS5: support display system register control [3/8] EXYNOS5: support display port phy control function [4/8] EXYNOS5: add display port base address [5/8] video: support exynos display port drivers [6/8] video: add dp_enabled variable in vidinfo structure [7/8] video: exynos fb driver supports display port feature -This patch depends on [PATCH] video: support exynos fimd driver for various exynos series. http://marc.info/?l=u-boot&m=134119605104467&w=2 [8/8] video: support exynos pwm backlight driver ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8] EXYNOS5: support exynos5 lcd clock control
This patch support exynos5 lcd clock control.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/cpu/armv7/exynos/clock.c | 108 -
1 files changed, 107 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 7326655..3143f7e 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -480,6 +480,48 @@ static unsigned long exynos4_get_lcd_clk(void)
return pclk;
}
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos5_get_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_LCD0
+* FIMD0_SEL [3:0]
+*/
+ sel = readl(&clk->src_disp1_0);
+ sel = sel & 0xf;
+
+ /*
+* 0x6: SCLK_MPLL
+* 0x7: SCLK_EPLL
+* 0x8: SCLK_VPLL
+*/
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+* CLK_DIV_LCD0
+* FIMD0_RATIO [3:0]
+*/
+ ratio = readl(&clk->div_disp1_0);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -542,6 +584,68 @@ void exynos4_set_lcd_clk(void)
writel(cfg, &clk->div_lcd0);
}
+void exynos5_set_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int cfg = 0;
+
+ /*
+* CLK_GATE_BLOCK
+* CLK_CAM [0]
+* CLK_TV [1]
+* CLK_MFC [2]
+* CLK_G3D [3]
+* CLK_LCD0 [4]
+* CLK_LCD1 [5]
+* CLK_GPS [7]
+*/
+ cfg = readl(&clk->gate_block);
+ cfg |= 1 << 4;
+ writel(cfg, &clk->gate_block);
+
+ /*
+* CLK_SRC_LCD0
+* FIMD0_SEL[3:0]
+* MDNIE0_SEL [7:4]
+* MDNIE_PWM0_SEL [8:11]
+* MIPI0_SEL[12:15]
+* set lcd0 src clock 0x6: SCLK_MPLL
+*/
+ cfg = readl(&clk->src_disp1_0);
+ cfg &= ~(0xf);
+ cfg |= 0x8;
+ writel(cfg, &clk->src_disp1_0);
+
+ /*
+* CLK_GATE_IP_LCD0
+* CLK_FIMD0[0]
+* CLK_MIE0 [1]
+* CLK_MDNIE0 [2]
+* CLK_DSIM0[3]
+* CLK_SMMUFIMD0[4]
+* CLK_PPMULCD0 [5]
+* Gating all clocks for FIMD0
+*/
+ cfg = readl(&clk->gate_ip_disp1);
+ cfg |= 1 << 0;
+ writel(cfg, &clk->gate_ip_disp1);
+
+ /*
+* CLK_DIV_LCD0
+* FIMD0_RATIO [3:0]
+* MDNIE0_RATIO [7:4]
+* MDNIE_PWM0_RATIO [11:8]
+* MDNIE_PWM_PRE_RATIO [15:12]
+* MIPI0_RATIO [19:16]
+* MIPI0_PRE_RATIO [23:20]
+* set fimd ratio
+*/
+ cfg &= ~(0xf);
+ cfg |= 0x0;
+ writel(cfg, &clk->div_disp1_0);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -680,13 +784,15 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else
- return 0;
+ return exynos5_get_lcd_clk();
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
+ else
+ exynos5_set_lcd_clk();
}
void set_mipi_clk(void)
--
1.7.4.1
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[U-Boot] [PATCH 2/8] EXYNOS5: support display system register control
This patch supports display block system regisger control.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/cpu/armv7/exynos/system.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/system.c
b/arch/arm/cpu/armv7/exynos/system.c
index cc6ee03..5a6747a 100644
--- a/arch/arm/cpu/armv7/exynos/system.c
+++ b/arch/arm/cpu/armv7/exynos/system.c
@@ -63,8 +63,26 @@ static void exynos4_set_system_display(void)
writel(cfg, &sysreg->display_ctrl);
}
+static void exynos5_set_system_display(void)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ unsigned int cfg = 0;
+
+ /*
+* system register path set
+* 0: MIE/MDNIE
+* 1: FIMD Bypass
+*/
+ cfg = readl(&sysreg->disp1blk_cfg);
+ cfg |= (1 << 15);
+ writel(cfg, &sysreg->disp1blk_cfg);
+}
+
void set_system_display_ctrl(void)
{
if (cpu_is_exynos4())
exynos4_set_system_display();
+ else
+ exynos5_set_system_display();
}
--
1.7.4.1
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[U-Boot] [PATCH 4/8] EXYNOS5: add display port base address
This patch add display port base address for EXYNOS5. In case of EXYNOS4, use DEVICE_NOT_AVAILABLE macro because DP is not supported. Signed-off-by: Donghwa Lee Signed-off-by: Kyungmin Park --- arch/arm/include/asm/arch-exynos/cpu.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 76ef776..0068bb5 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -57,6 +57,7 @@ #define EXYNOS4_USBPHY_CONTROL 0x10020704 #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE +#define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE /* EXYNOS5 */ #define EXYNOS5_GPIO_PART4_BASE0x0386 @@ -83,6 +84,7 @@ #define EXYNOS5_PWMTIMER_BASE 0x12DD #define EXYNOS5_GPIO_PART2_BASE0x1340 #define EXYNOS5_FIMD_BASE 0x1440 +#define EXYNOS5_DP_BASE0x145B #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE @@ -150,6 +152,7 @@ static inline unsigned int samsung_get_base_##device(void) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) SAMSUNG_BASE(i2c, I2C_BASE) -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/8] video: add dp_enabled variable in vidinfo structure
To support display port in exynos fb driver, added dp_enabled variable
in vidinfo structure that set in board file.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
include/lcd.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/lcd.h b/include/lcd.h
index 6e0a2a3..42070d7 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -240,6 +240,7 @@ typedef struct vidinfo {
unsigned int reset_delay;
unsigned int interface_mode;
unsigned int mipi_enabled;
+ unsigned int dp_enabled;
unsigned int cs_setup;
unsigned int wr_setup;
unsigned int wr_act;
--
1.7.4.1
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[U-Boot] [PATCH 3/8] EXYNOS5: support display port phy control function
This patch support display port phy control function.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/cpu/armv7/exynos/power.c| 21 +
arch/arm/include/asm/arch-exynos/power.h |5 +
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/power.c
b/arch/arm/cpu/armv7/exynos/power.c
index 4116781..d4bce6d 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -74,3 +74,24 @@ void set_usbhost_phy_ctrl(unsigned int enable)
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
}
+
+static void exynos5_dp_phy_control(unsigned int enable)
+{
+ unsigned int cfg;
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ cfg = readl(&power->dptx_phy_control);
+ if (enable)
+ cfg |= EXYNOS_DP_PHY_ENABLE;
+ else
+ cfg &= ~EXYNOS_DP_PHY_ENABLE;
+
+ writel(cfg, &power->dptx_phy_control);
+}
+
+void set_dp_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_dp_phy_control(enable);
+}
diff --git a/arch/arm/include/asm/arch-exynos/power.h
b/arch/arm/include/asm/arch-exynos/power.h
index e5467e2..d2fdb59 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -859,4 +859,9 @@ void set_usbhost_phy_ctrl(unsigned int enable);
#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
#define POWER_USB_HOST_PHY_CTRL_DISABLE(0 << 0)
+
+void set_dp_phy_ctrl(unsigned int enable);
+
+#define EXYNOS_DP_PHY_ENABLE (1 << 0)
+
#endif
--
1.7.4.1
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[U-Boot] [PATCH 7/8] video: exynos fb driver supports display port feature
If dp_enabled was set, exynos fb driver support display port feature.
This patch depends on [PATCH] video: support exynos fimd driver
for various exynos series.
http://marc.info/?l=u-boot&m=134119605104467&w=2
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/include/asm/arch-exynos/fb.h |1 +
drivers/video/exynos_fb.c |5 -
drivers/video/exynos_fimd.c | 15 +++
3 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/fb.h
b/arch/arm/include/asm/arch-exynos/fb.h
index bc0a4cb..a3790e2 100644
--- a/arch/arm/include/asm/arch-exynos/fb.h
+++ b/arch/arm/include/asm/arch-exynos/fb.h
@@ -152,6 +152,7 @@ struct exynos_fb {
unsigned char res15[156];
unsigned int dualrgb;
unsigned char res16[16];
+ unsigned int dp_mie_clkcon;
};
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index 49fdfec..e31a0fd 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include "exynos_fb.h"
@@ -91,6 +92,9 @@ static void lcd_panel_on(vidinfo_t *vid)
udelay(vid->power_on_delay);
+ if (vid->dp_enabled)
+ exynos_init_dp();
+
if (vid->reset_lcd) {
vid->reset_lcd();
udelay(vid->reset_delay);
@@ -130,7 +134,6 @@ void lcd_enable(void)
if (panel_info.logo_on) {
memset(lcd_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
-
draw_logo();
}
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index 989063d..6539902 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -57,6 +57,19 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled)
writel(cfg, &fimd_ctrl->dualrgb);
}
+static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
+{
+
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
+ unsigned int cfg = 0;
+
+ if (enabled)
+ cfg = EXYNOS_DP_CLK_ENABLE;
+
+ writel(cfg, &fimd_ctrl->dp_mie_clkcon);
+}
+
static void exynos_fimd_set_par(unsigned int win_id)
{
unsigned int cfg = 0;
@@ -363,6 +376,8 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
/* window on */
exynos_fimd_window_on(pvid->win_id);
+
+ exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
}
unsigned long exynos_fimd_calc_fbsize(void)
--
1.7.4.1
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[U-Boot] [PATCH 8/8] video: support exynos pwm backlight driver
This patch support exynos pwm backlight driver. It can control backlight
power and brightness by using pwm.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/include/asm/arch-exynos/pwm_backlight.h | 34 +
drivers/video/Makefile |1 +
drivers/video/exynos_pwm_bl.c| 57 ++
3 files changed, 92 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/pwm_backlight.h
create mode 100644 drivers/video/exynos_pwm_bl.c
diff --git a/arch/arm/include/asm/arch-exynos/pwm_backlight.h
b/arch/arm/include/asm/arch-exynos/pwm_backlight.h
new file mode 100644
index 000..368ffc5
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/pwm_backlight.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PWM_BACKLIGHT_H_
+#define _PWM_BACKLIGHT_H_
+
+struct pwm_backlight_data {
+ int pwm_id;
+ int period;
+ int max_brightness;
+ int brightness;
+};
+
+extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
+
+#endif /* _PWM_BACKLIGHT_H_ */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a7530a4..4a0a5b4 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o
\
exynos_mipi_dsi_lowlevel.o
+COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
diff --git a/drivers/video/exynos_pwm_bl.c b/drivers/video/exynos_pwm_bl.c
new file mode 100644
index 000..27fb0b5
--- /dev/null
+++ b/drivers/video/exynos_pwm_bl.c
@@ -0,0 +1,57 @@
+/*
+ * PWM BACKLIGHT driver for Board based on EXYNOS.
+ *
+ * Author: Donghwa Lee
+ *
+ * Derived from linux/drivers/video/backlight/pwm_backlight.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct pwm_backlight_data *pwm;
+
+static int exynos_pwm_backlight_update_status(void)
+{
+ int brightness = pwm->brightness;
+ int max = pwm->max_brightness;
+
+ if (brightness == 0) {
+ pwm_config(pwm->pwm_id, 0, pwm->period);
+ pwm_disable(pwm->pwm_id);
+ } else {
+ pwm_config(pwm->pwm_id,
+ brightness * pwm->period / max, pwm->period);
+ pwm_enable(pwm->pwm_id);
+ }
+ return 0;
+}
+
+int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
+{
+ pwm = pd;
+
+ exynos_pwm_backlight_update_status();
+
+ return 0;
+}
--
1.7.4.1
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[U-Boot] [PATCH] video: fixed exynos_mipi_dsi_init() declaration
To avoid compilers error in case of not using
CONFIG_EXYNOS_MIPI_DSIM, add no operation function.
Signed-off-by: Donghwa Lee
Signed-off-by: Kyungmin Park
---
arch/arm/include/asm/arch-exynos/mipi_dsim.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
index 9a7cbeb..b73263d 100644
--- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -358,7 +358,14 @@ struct mipi_dsim_lcd_driver {
void(*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
};
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
int exynos_mipi_dsi_init(void);
+#else
+int exynos_mipi_dsi_init(void)
+{
+ return 0;
+}
+#endif
/*
* register mipi_dsim_lcd_driver object defined by lcd panel driver
--
1.7.4.1
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[U-Boot] [PATCH 00/10 V5] EXYNOS5: Support for Exynos5250 Rev 1.0
This patch set adds support for Exynos5250 Rev 1.0. Exynos5250 Rev 1.0 supports DDR3 Memory configuration and support for LPDDR2 is removed. Exynos5250 Rev 1.0 supports DWMMC controller and does not support SDHCI controller. After DWMMC driver is added to Mainline support for generic S5P MMC driver will be removed. Due to Support of SDHCI controller currently still there for EXYNOS5 you can see the following error on boot. mmc_reset: timeout error mmc_change_clock: timeout error mmc_send_cmd: waiting for status update MMC init failed Changes in V2: - Included Paramateric structure with in #ifndef __ASSEMBLY__. Chnages in V3: - Incorporated the review comments. - Added support for BPLL. - Corrected the gpio pinmux settings. Changes in V4: - Fixed Warning message. Changes in V5: - Corrected indentation error. Rajeshwari Shinde (10): ARCH: SPL: Add parametric board initializer SMDK5250: SPL: Define parametric board initializer SMDK5250: Add smdk5250-uboot-spl.lds EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add BPLL support EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 arch/arm/cpu/armv7/exynos/clock.c | 28 +- arch/arm/cpu/armv7/exynos/pinmux.c| 22 +- arch/arm/include/asm/arch-exynos/clk.h|1 + arch/arm/include/asm/arch-exynos/clock.h | 237 + arch/arm/include/asm/arch-exynos/dmc.h| 65 +++ arch/arm/include/asm/arch-exynos/gpio.h |7 +- arch/arm/include/asm/arch-exynos/spl.h| 97 board/samsung/smdk5250/Makefile |3 +- board/samsung/smdk5250/clock_init.c | 714 +++ board/samsung/smdk5250/clock_init.h | 149 + board/samsung/smdk5250/dmc_common.c | 199 +++ board/samsung/smdk5250/dmc_init.c | 462 --- board/samsung/smdk5250/dmc_init_ddr3.c| 228 board/samsung/smdk5250/setup.h| 762 +++-- board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ board/samsung/smdk5250/smdk5250.c |6 +- board/samsung/smdk5250/smdk5250_spl.c | 68 +++ include/configs/smdk5250.h|7 +- 18 files changed, 2099 insertions(+), 1022 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h create mode 100644 board/samsung/smdk5250/clock_init.h create mode 100644 board/samsung/smdk5250/dmc_common.c delete mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds create mode 100644 board/samsung/smdk5250/smdk5250_spl.c -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10 V5] ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- Included Paramateric structure with in #ifndef __ASSEMBLY__.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
arch/arm/include/asm/arch-exynos/spl.h | 97
1 files changed, 97 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/spl.h
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000..306b41d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include
+
+enum boot_mode {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version;/* Version number */
+ u32 size; /* Size of block */
+ /**
+* Parameters we expect, in order, terminated with \0. Each parameter
+* is a single character representing one 32-bit word in this
+* structure.
+*
+* Valid characters in this string are:
+*
+* Code Name
+* vmem_iv_size
+* mmem_type
+* uuboot_size
+* bboot_source
+* ffrequency_mhz (memory frequency in MHz)
+* aARM clock frequency in MHz
+* sserial base address
+* ii2c base address for early access (meant for PMIC)
+* rboard rev GPIO numbers used to read board revision
+* (lower halfword=bit 0, upper=bit 1)
+* MMemory Manufacturer name
+* \0 termination
+*/
+ charparams[12]; /* Length must be word-aligned */
+ u32 mem_iv_size;/* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+* U-boot size - The iROM mmc copy function used by the SPL takes a
+* block count paramter to describe the u-boot size unlike the spi
+* boot copy function which just uses the u-boot size directly. Align
+* the u-boot size to block size (512 bytes) when populating the SPL
+* table only for mmc boot.
+*/
+ u32 uboot_size;
+ enum boot_mode boot_source;/* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsignedfrequency_mhz; /* Frequency of memory in MHz */
+ unsignedarm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base;/* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
--
1.7.4.4
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[U-Boot] [PATCH 02/10 V5] SMDK5250: SPL: Define parametric board initializer
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/smdk5250_spl.c | 68 +
2 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250_spl.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..3675fad 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
diff --git a/board/samsung/smdk5250/smdk5250_spl.c
b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000..1d453ca
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+* Set uboot_size to 0x10 bytes.
+*
+* This is an overly conservative value chosen to accommodate all
+* possible U-Boot image. You are advised to set this value to a
+* smaller realistic size via scripts that modifies the .machine_param
+* section of output U-Boot image.
+*/
+ .uboot_size = 0x10,
+
+ .boot_source= BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base= 0x12c3,
+ .i2c_base = 0x12c6,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
--
1.7.4.4
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[U-Boot] [PATCH 03/10 V5] SMDK5250: Add smdk5250-uboot-spl.lds
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None.
Changes in V3:
- None
Changes in V4:
- None.
Changes in V5:
- None
board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +
include/configs/smdk5250.h|5 ++
2 files changed, 71 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds
diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds
b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
new file mode 100644
index 000..d78dd77
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+ . = ALIGN(4);
+
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+ . = ALIGN(4);
+
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+
+ /* Align .machine_param on 256 byte boundary for easier searching */
+ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sram
+}
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 9659f9e..405abd5 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -105,6 +105,11 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR0x02020030
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_SIZE(14 * 1024)
+
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
/* Miscellaneous configurable options */
--
1.7.4.4
___
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[U-Boot] [PATCH 04/10 V5] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
Acked-by: Joonyoung Shim
---
Changes in V2:
- None.
Changes in V3:
- Modified Clocks as per Exynos5250 Rev 1.0.
Changes in V4:
- None.
Changes in V5:
- None
arch/arm/include/asm/arch-exynos/clock.h | 234 --
1 files changed, 126 insertions(+), 108 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 50da958..90271f1 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -273,8 +273,7 @@ struct exynos5_clock {
unsigned intclkout_cmu_cpu_div_stat;
unsigned char res8[0x5f8];
unsigned intarmclk_stopctrl;
- unsigned intatclk_stopctrl;
- unsigned char res9[0x8];
+ unsigned char res9[0x0c];
unsigned intparityfail_status;
unsigned intparityfail_clear;
unsigned char res10[0x8];
@@ -323,259 +322,278 @@ struct exynos5_clock {
unsigned char res19[0xf8];
unsigned intdiv_core0;
unsigned intdiv_core1;
- unsigned char res20[0xf8];
+ unsigned intdiv_sysrgt;
+ unsigned char res20[0xf4];
unsigned intdiv_stat_core0;
unsigned intdiv_stat_core1;
- unsigned char res21[0x2f8];
+ unsigned intdiv_stat_sysrgt;
+ unsigned char res21[0x2f4];
unsigned intgate_ip_core;
- unsigned char res22[0xfc];
+ unsigned intgate_ip_sysrgt;
+ unsigned char res22[0x8];
+ unsigned intc2c_monitor;
+ unsigned char res23[0xec];
unsigned intclkout_cmu_core;
unsigned intclkout_cmu_core_div_stat;
- unsigned char res23[0x5f8];
+ unsigned char res24[0x5f8];
unsigned intdcgidx_map0;
unsigned intdcgidx_map1;
unsigned intdcgidx_map2;
- unsigned char res24[0x14];
+ unsigned char res25[0x14];
unsigned intdcgperf_map0;
unsigned intdcgperf_map1;
- unsigned char res25[0x18];
+ unsigned char res26[0x18];
unsigned intdvcidx_map;
- unsigned char res26[0x1c];
+ unsigned char res27[0x1c];
unsigned intfreq_cpu;
unsigned intfreq_dpm;
- unsigned char res27[0x18];
+ unsigned char res28[0x18];
unsigned intdvsemclk_en;
unsigned intmaxperf;
- unsigned char res28[0x3478];
+ unsigned char res29[0xf78];
+ unsigned intc2c_config;
+ unsigned char res30[0x24fc];
unsigned intdiv_acp;
- unsigned char res29[0xfc];
+ unsigned char res31[0xfc];
unsigned intdiv_stat_acp;
- unsigned char res30[0x1fc];
+ unsigned char res32[0x1fc];
unsigned intgate_ip_acp;
- unsigned char res31[0x1fc];
+ unsigned char res33[0xfc];
+ unsigned intdiv_syslft;
+ unsigned char res34[0xc];
+ unsigned intdiv_stat_syslft;
+ unsigned char res35[0x1c];
+ unsigned intgate_ip_syslft;
+ unsigned char res36[0xcc];
unsigned intclkout_cmu_acp;
unsigned intclkout_cmu_acp_div_stat;
- unsigned char res32[0x38f8];
+ unsigned char res37[0x8];
+ unsigned intufmc_config;
+ unsigned char res38[0x38ec];
unsigned intdiv_isp0;
unsigned intdiv_isp1;
unsigned intdiv_isp2;
- unsigned char res33[0xf4];
+ unsigned char res39[0xf4];
unsigned intdiv_stat_isp0;
unsigned intdiv_stat_isp1;
unsigned intdiv_stat_isp2;
- unsigned char res34[0x3f4];
+ unsigned char res40[0x3f4];
unsigned intgate_ip_isp0;
unsigned intgate_ip_isp1;
- unsigned char res35[0xf8];
+ unsigned char res41[0xf8];
unsigned intgate_sclk_isp;
- unsigned char res36[0xc];
+ unsigned char res42[0xc];
unsigned intmcuisp_pwr_ctrl;
- unsigned char res37[0xec];
+ unsigned char res43[0xec];
unsigned intclkout_cmu_isp;
unsigned intclkout_cmu_isp_div_stat;
- unsigned char res38[0x3618];
+ unsigned char res44[0x3618];
unsigned intcpll_lock;
- unsigned char res39[0xc];
+ unsigned char res45[0xc];
unsigned intepll_lock;
- unsigned char res40[0xc];
+ unsigned char res46[0xc];
unsigned intvpll_lock;
- unsigned char res41[0xdc];
+ unsigned char res47[0xc];
+ unsigned intgpll_lock;
+ unsigned char res48[0xcc];
unsigned intcpll_con0;
unsigned intcpll_con1;
- unsigned char res42[0x8];
+ unsigned char res49[0x8];
uns
[U-Boot] [PATCH 05/10 V5] EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None.
Changes in V3:
- Set Peric3 clock for PWM Ratio.
Changes in V4:
- None.
Changes in V5:
- None
board/samsung/smdk5250/clock_init.c | 714 +--
board/samsung/smdk5250/clock_init.h | 149
board/samsung/smdk5250/setup.h | 715 ---
3 files changed, 1138 insertions(+), 440 deletions(-)
create mode 100644 board/samsung/smdk5250/clock_init.h
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index 305842d..c009ae5 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -22,181 +22,645 @@
* MA 02111-1307 USA
*/
+#include
#include
-#include
#include
+#include
#include
-#include
-#include
+#include
+
+#include "clock_init.h"
#include "setup.h"
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+ {
+ .arm_freq_mhz = 600,
+
+ .apll_mdiv = 0xc8,
+ .apll_pdiv = 0x4,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x2,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x1,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 800,
+
+ .apll_mdiv = 0x64,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x3,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1000,
+
+ .apll_mdiv = 0x7d,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x4,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1200,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x5,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1400,
+
+ .apll_mdiv = 0xaf,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1700,
+
+ .apll_mdiv = 0x1a9,
+ .apll_pdiv = 0x6,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }
+};
+struct mem_timings mem_timings[] = {
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x0003, 0x00010042, 0x0d70
+ },
+ .timing_ref = 0x00bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+
[U-Boot] [PATCH 06/10 V5] Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None.
Chnages in V3:
- None.
Changes in V4:
- None
Changes in V5:
- None.
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/samsung/smdk5250/dmc_init.c | 462
board/samsung/smdk5250/dmc_init_ddr3.c | 228
board/samsung/smdk5250/setup.h | 59 -
6 files changed, 551 insertions(+), 464 deletions(-)
create mode 100644 board/samsung/smdk5250/dmc_common.c
delete mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16..f65c676 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK(0x7 <<
PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 3675fad..1474fa8 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..109602a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,199 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+
+#include "clock_init.h"
+#include "setup.h"
+
+#define ZQ_INIT_TIMEOUT1
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_contro
[U-Boot] [PATCH 07/10 V5] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
Acked-by: Joonyoung Shim
---
Changes in V2:
- None
Changes in V3:
- Incorported review comments from Minkyu Kang.
Changes in V4:
- None.
Changes in V5:
- None
arch/arm/cpu/armv7/exynos/clock.c| 12 +++-
arch/arm/include/asm/arch-exynos/clock.h |3 +++
2 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..dbd5f11 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq;
+ unsigned int freq, pll_div2_sel, mpll_fout_sel;
switch (pllreg) {
case APLL:
@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1;
}
+ /* According to the user manual, in EVT1 MPLL always gives
+* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+ mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ if (mpll_fout_sel == 0)
+ fout /= 2;
+ }
+
return fout;
}
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 90271f1..bf41c19 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -596,4 +596,7 @@ struct exynos5_clock {
unsigned char res123[0xf5d8];
};
#endif
+
+#define MPLL_FOUT_SEL_SHIFT4
+#define MPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
___
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[U-Boot] [PATCH 09/10 V5] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.
Signed-off-by: Rajeshwari Shinde
Acked-by: Joonyoung Shim
---
Changes in V2:
- None.
Changes in V3:
- Corrected the pinmux settings and offset calcuation of gpio banks.
Changes in V4:
- None
Changes in V5:
- None.
arch/arm/cpu/armv7/exynos/pinmux.c | 22 +-
arch/arm/include/asm/arch-exynos/gpio.h |7 +--
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index d2b7d2c..822410e 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ bank = &gpio1->d0;
+ start = 0;
count = 4;
break;
case PERIPH_ID_UART2:
@@ -66,23 +66,27 @@ static int exynos5_mmc_config(int peripheral, int flags)
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start, gpio_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
+ start = 0;
+ gpio_func = GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c1;
+ bank = &gpio1->c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c2;
- bank_ext = &gpio1->c3;
+ bank = &gpio1->c3;
+ bank_ext = &gpio1->c4;
+ start = 3;
+ gpio_func = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
- bank = &gpio1->c3;
+ bank = &gpio1->c4;
bank_ext = NULL;
break;
}
@@ -92,8 +96,8 @@ static int exynos5_mmc_config(int peripheral, int flags)
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ for (i = start; i <= (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 7a9bb90..97be4ea 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -100,7 +100,9 @@ struct exynos5_gpio_part1 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x980];
+ struct s5p_gpio_bank res1[0x3];
+ struct s5p_gpio_bank c4;
+ struct s5p_gpio_bank res2[0x48];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
@@ -122,9 +124,10 @@ struct exynos5_gpio_part2 {
struct exynos5_gpio_part3 {
struct s5p_gpio_bank v0;
struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
struct s5p_gpio_bank v2;
struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res1[0x20];
+ struct s5p_gpio_bank res2[0x1];
struct s5p_gpio_bank v4;
};
--
1.7.4.4
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[U-Boot] [PATCH 08/10 V5] EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde
Acked-by: Joonyoung Shim
---
Changes in V3:
- New Patch.
Changes in V4:
- Removed warning message.
Changes in V5:
- fixed indentation error
arch/arm/cpu/armv7/exynos/clock.c| 28 +---
arch/arm/include/asm/arch-exynos/clk.h |1 +
arch/arm/include/asm/arch-exynos/clock.h |2 ++
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index dbd5f11..fc0ed5e 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq, pll_div2_sel, mpll_fout_sel;
+ unsigned int freq, pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
@@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+* BPLL_CON: MIDV [25:16]
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1;
}
- /* According to the user manual, in EVT1 MPLL always gives
+ /* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
- if (pllreg == MPLL) {
+ if (pllreg == MPLL || pllreg == BPLL) {
pll_div2_sel = readl(&clk->pll_div2_sel);
- mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
- & MPLL_FOUT_SEL_MASK;
- if (mpll_fout_sel == 0)
+
+ switch (pllreg) {
+ case MPLL:
+ fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ break;
+ case BPLL:
+ fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
+ & BPLL_FOUT_SEL_MASK;
+ break;
+ }
+
+ if (fout_sel == 0)
fout /= 2;
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..e99339a 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -27,6 +27,7 @@
#define EPLL 2
#define HPLL 3
#define VPLL 4
+#define BPLL 5
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index bf41c19..fce38ef 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -599,4 +599,6 @@ struct exynos5_clock {
#define MPLL_FOUT_SEL_SHIFT4
#define MPLL_FOUT_SEL_MASK 0x1
+#define BPLL_FOUT_SEL_SHIFT0
+#define BPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
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[U-Boot] [PATCH 10/10 V5] SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- None.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index 3b078da..b593325 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
{
int err;
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
- debug("SDMMC2 not configured\n");
+ debug("SDMMC0 not configured\n");
return err;
}
- err = s5p_mmc_init(2, 4);
+ err = s5p_mmc_init(0, 8);
return err;
}
#endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 405abd5..d4d370f 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -69,7 +69,7 @@
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1 /* use SERIAL 1 */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE115200
#define EXYNOS5_DEFAULT_UART_OFFSET0x01
--
1.7.4.4
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[U-Boot] [PATCH v6] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
On at91sam platforms, u-boot grew larger than the allocated size in
dataflash, the layout was:
bootstrap 0x
ubootenv 0x4200
uboot 0x8400
kernel 0x00042000
u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 =
0x39C00 bytes anymore.
Now, the layout is:
bootstrap 0x
ubootenv 0x4200
uboot 0x8400
kernel 0x00084000
Signed-off-by: Alexandre Belloni
---
Changes for v2:
- changed the layout as per Marek's recommendation
Changes for v3:
- prefixed the patch title with AT91SAM9*:
Changes for v4:
- changed the layout again as per Ulf Samuelsson's request:
http://lists.denx.de/pipermail/u-boot/2012-February/118988.html
Changes for v5:
- also update partition list
Changes for v6:
- rebase on latest u-boot-atmel
board/atmel/at91sam9260ek/partition.c |2 +-
board/atmel/at91sam9261ek/partition.c |2 +-
board/atmel/at91sam9263ek/partition.c |2 +-
board/atmel/at91sam9rlek/partition.c |2 +-
include/configs/at91sam9260ek.h |5 +++--
include/configs/at91sam9261ek.h |5 +++--
include/configs/at91sam9263ek.h |2 +-
include/configs/at91sam9rlek.h|3 ++-
8 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/board/atmel/at91sam9260ek/partition.c
b/board/atmel/at91sam9260ek/partition.c
index 2629c67..842bb89 100644
--- a/board/atmel/at91sam9260ek/partition.c
+++ b/board/atmel/at91sam9260ek/partition.c
@@ -35,6 +35,6 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00084000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9261ek/partition.c
b/board/atmel/at91sam9261ek/partition.c
index c739b11..96c4fcb 100644
--- a/board/atmel/at91sam9261ek/partition.c
+++ b/board/atmel/at91sam9261ek/partition.c
@@ -35,6 +35,6 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00084000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9263ek/partition.c
b/board/atmel/at91sam9263ek/partition.c
index 7e1d46f..7f11fd0 100644
--- a/board/atmel/at91sam9263ek/partition.c
+++ b/board/atmel/at91sam9263ek/partition.c
@@ -34,6 +34,6 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00084000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9rlek/partition.c
b/board/atmel/at91sam9rlek/partition.c
index 7e1d46f..7f11fd0 100644
--- a/board/atmel/at91sam9rlek/partition.c
+++ b/board/atmel/at91sam9rlek/partition.c
@@ -34,6 +34,6 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00084000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 07b1968..ef25fa5 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -187,7 +187,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 +
CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x2200 0x21; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x2200 0x21; bootm"
#define CONFIG_BOOTARGS"console=ttyS0,115200 "
\
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
@@ -201,7 +201,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 +
CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE0x4200
-#define
Re: [U-Boot] [PATCH v6] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
Dear Alexandre Belloni,
On 02.07.2012 13:37, Alexandre Belloni wrote:
> On at91sam platforms, u-boot grew larger than the allocated size in
> dataflash, the layout was:
> bootstrap 0x
> ubootenv 0x4200
> uboot 0x8400
> kernel 0x00042000
>
> u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 =
> 0x39C00 bytes anymore.
>
> Now, the layout is:
> bootstrap 0x
> ubootenv 0x4200
> uboot 0x8400
> kernel 0x00084000
>
> Signed-off-by: Alexandre Belloni
> ---
> Changes for v2:
> - changed the layout as per Marek's recommendation
> Changes for v3:
> - prefixed the patch title with AT91SAM9*:
> Changes for v4:
> - changed the layout again as per Ulf Samuelsson's request:
> http://lists.denx.de/pipermail/u-boot/2012-February/118988.html
> Changes for v5:
> - also update partition list
> Changes for v6:
> - rebase on latest u-boot-atmel
>
> board/atmel/at91sam9260ek/partition.c |2 +-
> board/atmel/at91sam9261ek/partition.c |2 +-
> board/atmel/at91sam9263ek/partition.c |2 +-
> board/atmel/at91sam9rlek/partition.c |2 +-
> include/configs/at91sam9260ek.h |5 +++--
> include/configs/at91sam9261ek.h |5 +++--
> include/configs/at91sam9263ek.h |2 +-
> include/configs/at91sam9rlek.h|3 ++-
> 8 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/board/atmel/at91sam9260ek/partition.c
> b/board/atmel/at91sam9260ek/partition.c
> index 2629c67..842bb89 100644
> --- a/board/atmel/at91sam9260ek/partition.c
> +++ b/board/atmel/at91sam9260ek/partition.c
> @@ -35,6 +35,6 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
> {0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
> {0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
> {0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
> - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
> + {0x00084000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
really sorry for that, I should have seen it before. Shouldn't we also
make the U-Boot partition greater when we move the start of kernel
partition?
Can you please send another version, rest is fine (checkpatch, apply
cleanly, no build errors).
> {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
> };
> diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
> index 07b1968..ef25fa5 100644
> --- a/include/configs/at91sam9260ek.h
> +++ b/include/configs/at91sam9260ek.h
> @@ -187,7 +187,7 @@
> #define CONFIG_ENV_OFFSET0x4200
> #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 +
> CONFIG_ENV_OFFSET)
> #define CONFIG_ENV_SIZE 0x4200
> -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x2200 0x21; bootm"
> +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x2200 0x21; bootm"
also sorry, but size is wrong here! We reduced the partition to
0x1CE000, it is about 1.8 MiB now and not 2 MiB as before.
Best regards
Andreas Bießmann
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Re: [U-Boot] [PATCH] arm: armv7: add compile option -mno-unaligned-access if available
Tetsuyuki Kobayashi writes: > Recent compiler generates unaligned memory access in armv7 default. > But current U-Boot does not allow unaligned memory access, so it causes > data abort exception. > This patch add compile option "-mno-unaligned-access" if it is available. Why not allow unaligned accesses instead? -- Måns Rullgård m...@mansr.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] i.mx28 can't power off in imx-boot
Dear alex, > Hi: >I can't power off the chip by function "mx28_powerdown", and I can't > find any error on it. So I want to know whether this issue is on your > side. The code is based on mainline imx-uboot. The system obviously won't powerdown as a usual ATX PC. It's only the chip will hang. > Best Regards, > Alex Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cm-t35: fix incorrect NAND_ECC layout selection
The current configuration selects an incorrect NAND ECC layout, which causes u-boot to write HW ECC data incorrectly. This patch selects the right layout. Signed-off-by: Nikita Kiryanov --- include/configs/cm_t35.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 1419f06..e0dd3fb 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -174,7 +174,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_ECC_LP_x8_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
On Mon, Jul 02, 2012 at 02:01:00PM +0200, Andreas Bießmann wrote :
> really sorry for that, I should have seen it before. Shouldn't we also
> make the U-Boot partition greater when we move the start of kernel
> partition?
> Can you please send another version, rest is fine (checkpatch, apply
> cleanly, no build errors).
>
> > {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
> > };
Ah, sure, I'll fix that.
>
>
>
> > diff --git a/include/configs/at91sam9260ek.h
> > b/include/configs/at91sam9260ek.h
> > index 07b1968..ef25fa5 100644
> > --- a/include/configs/at91sam9260ek.h
> > +++ b/include/configs/at91sam9260ek.h
> > @@ -187,7 +187,7 @@
> > #define CONFIG_ENV_OFFSET 0x4200
> > #define CONFIG_ENV_ADDR(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 +
> > CONFIG_ENV_OFFSET)
> > #define CONFIG_ENV_SIZE0x4200
> > -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x2200 0x21; bootm"
> > +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x2200 0x21; bootm"
>
> also sorry, but size is wrong here! We reduced the partition to
> 0x1CE000, it is about 1.8 MiB now and not 2 MiB as before.
>
Right, I didn't really care about the end of the kernel partition as the
9261ek has an 8MiB dataflash and my rootfs is in NAND. The kernel is
around 1.7MiB using the default configuration. Maybe, we should also
extend its partition ?
> Best regards
>
> Andreas Bießmann
>
--
Alexandre Belloni
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Re: [U-Boot] [PATCH v6] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
Dear Alexandre Belloni, On 02.07.2012 14:55, Alexandre Belloni wrote: > On Mon, Jul 02, 2012 at 02:01:00PM +0200, Andreas Bießmann wrote : >>> diff --git a/include/configs/at91sam9260ek.h >>> b/include/configs/at91sam9260ek.h >>> index 07b1968..ef25fa5 100644 >>> --- a/include/configs/at91sam9260ek.h >>> +++ b/include/configs/at91sam9260ek.h >>> @@ -187,7 +187,7 @@ >>> #define CONFIG_ENV_OFFSET 0x4200 >>> #define CONFIG_ENV_ADDR(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + >>> CONFIG_ENV_OFFSET) >>> #define CONFIG_ENV_SIZE0x4200 >>> -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x2200 0x21; bootm" >>> +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x2200 0x21; bootm" >> >> also sorry, but size is wrong here! We reduced the partition to >> 0x1CE000, it is about 1.8 MiB now and not 2 MiB as before. >> > > Right, I didn't really care about the end of the kernel partition as the > 9261ek has an 8MiB dataflash and my rootfs is in NAND. The kernel is > around 1.7MiB using the default configuration. Maybe, we should also > extend its partition ? well, I don't care about that too cause we usually don't have a dataflash in our devices. I think for the eval kits it would be nice to have a board support package which can be loaded from different media. Unfortunately I used to work with bare UBoot, vanilla kernel a.s.o. Therefore I have not such deep insight into the atmel provided bsp's. In short words: I tend to say we should increase the space for kernel partition but I fear to break some special bsp's. As I can see the kernel do not provide a special mapping here. If you are not aware of some other source (e.g. linux4sam), let us increase the space for kernel a bit. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] beagle: make get_expansion_id(), get_board_revision(), beagle_display_init() static
From: Peter Meerwald
Signed-off-by: Peter Meerwald
---
board/ti/beagle/beagle.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 9edd3c5..4611b8a 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -111,7 +111,7 @@ int board_init(void)
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
* GPIO173, GPIO172, GPIO171: 0 0 0 => xM
*/
-int get_board_revision(void)
+static int get_board_revision(void)
{
int revision;
@@ -210,7 +210,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32
*ctrlb, u32 *rfr_ctrl,
* bus 1 for the availability of an AT24C01B serial EEPROM.
* returns the device_vendor field from the EEPROM
*/
-unsigned int get_expansion_id(void)
+static unsigned int get_expansion_id(void)
{
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
@@ -233,7 +233,7 @@ unsigned int get_expansion_id(void)
* Configure DSS to display background color on DVID
* Configure VENC to display color bar on S-Video
*/
-void beagle_display_init(void)
+static void beagle_display_init(void)
{
omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
switch (get_board_revision()) {
--
1.7.5.4
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[U-Boot] [PATCH] beagle: fix termination of buddy env setting
From: Peter Meerwald Signed-off-by: Peter Meerwald --- include/configs/omap3_beagle.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 268215c..5fd67bc 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -222,7 +222,7 @@ "bootfile=uImage.beagle\0" \ "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ - "buddy=none "\ + "buddy=none\0" \ "optargs=\0" \ "camera=none\0" \ "vram=12M\0" \ -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
On Mon, Jul 02, 2012 at 03:07:55PM +0200, Andreas Bießmann wrote : > > Right, I didn't really care about the end of the kernel partition as the > > 9261ek has an 8MiB dataflash and my rootfs is in NAND. The kernel is > > around 1.7MiB using the default configuration. Maybe, we should also > > extend its partition ? > > well, I don't care about that too cause we usually don't have a > dataflash in our devices. > > I think for the eval kits it would be nice to have a board support > package which can be loaded from different media. Unfortunately I used > to work with bare UBoot, vanilla kernel a.s.o. Therefore I have not such > deep insight into the atmel provided bsp's. In short words: I tend to > say we should increase the space for kernel partition but I fear to > break some special bsp's. > As I can see the kernel do not provide a special mapping here. If you > are not aware of some other source (e.g. linux4sam), let us increase the > space for kernel a bit. > Actually, the two use cases listed on linux4sam are: - at91bootstrap, u-boot, kernel in dataflash and rootfs in nand - at91bootstrap, u-boot, kernel and rootfs in nand See: www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted Actually, the 9rlek, 9260ek and 9261ek have a 4MiB dataflash and the 9263ek doesn't have an embedded dataflash. I guess I'll change the mapping to still get 2MiB for the kernel. regards, -- Alexandre Belloni ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
On at91sam platforms, u-boot grew larger than the allocated size in
dataflash, the layout was:
bootstrap 0x
ubootenv 0x4200
uboot 0x8400
kernel 0x00042000
fs 0x00252000
u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 =
0x39C00 bytes anymore.
Now, the layout is:
bootstrap 0x
ubootenv 0x4200
uboot 0x8400
kernel 0x00084000
fs 0x00294000
Signed-off-by: Alexandre Belloni
---
Changes for v2:
- changed the layout as per Marek's recommendation
Changes for v3:
- prefixed the patch title with AT91SAM9*:
Changes for v4:
- changed the layout again as per Ulf Samuelsson's request:
http://lists.denx.de/pipermail/u-boot/2012-February/118988.html
Changes for v5:
- also update partition list
Changes for v6:
- rebase on latest u-boot-atmel
Changes for v7:
- Still allocate 0x0021 for the kernel
board/atmel/at91sam9260ek/partition.c |6 +++---
board/atmel/at91sam9261ek/partition.c |6 +++---
board/atmel/at91sam9263ek/partition.c |6 +++---
board/atmel/at91sam9rlek/partition.c |6 +++---
include/configs/at91sam9260ek.h |5 +++--
include/configs/at91sam9261ek.h |5 +++--
include/configs/at91sam9263ek.h |2 +-
include/configs/at91sam9rlek.h|3 ++-
8 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/board/atmel/at91sam9260ek/partition.c
b/board/atmel/at91sam9260ek/partition.c
index 2629c67..9ec054f 100644
--- a/board/atmel/at91sam9260ek/partition.c
+++ b/board/atmel/at91sam9260ek/partition.c
@@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x8400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9261ek/partition.c
b/board/atmel/at91sam9261ek/partition.c
index c739b11..51cac77 100644
--- a/board/atmel/at91sam9261ek/partition.c
+++ b/board/atmel/at91sam9261ek/partition.c
@@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x8400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9263ek/partition.c
b/board/atmel/at91sam9263ek/partition.c
index 7e1d46f..d48fab7 100644
--- a/board/atmel/at91sam9263ek/partition.c
+++ b/board/atmel/at91sam9263ek/partition.c
@@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x8400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/board/atmel/at91sam9rlek/partition.c
b/board/atmel/at91sam9rlek/partition.c
index 7e1d46f..d48fab7 100644
--- a/board/atmel/at91sam9rlek/partition.c
+++ b/board/atmel/at91sam9rlek/partition.c
@@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x, 0x41FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x4200, 0x83FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x8400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x8400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0x, FLAG_PROTECT_CLEAR, 0, "FS"},
};
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 07b1968..ef25fa5 100644
--- a/in
Re: [U-Boot] [PATCH v7] AT91SAM9*: Change kernel address in dataflash to match u-boot's size
Dear Alexandre Belloni, On 02.07.2012 16:26, Alexandre Belloni wrote: > On at91sam platforms, u-boot grew larger than the allocated size in > dataflash, the layout was: > bootstrap 0x > ubootenv 0x4200 > uboot 0x8400 > kernel 0x00042000 > fs 0x00252000 > > u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 = > 0x39C00 bytes anymore. > > Now, the layout is: > bootstrap 0x > ubootenv 0x4200 > uboot 0x8400 > kernel 0x00084000 > fs 0x00294000 > > Signed-off-by: Alexandre Belloni applied to u-boot-atmel/master, thanks! Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] doc/git-mailrc: update at91 and avr32
Signed-off-by: Andreas Bießmann --- doc/git-mailrc |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/git-mailrc b/doc/git-mailrc index c8a6390..743ce06 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -11,6 +11,7 @@ alias u-boot uboot # Maintainer aliases. Use the same alias here as patchwork to keep # things simple and easy to look up/coordinate. alias aaribaud Albert Aribaud +alias abiessmann Andreas Bießmann alias afleming Andy Fleming alias ag Anatolij Gustschin alias galak Kumar Gala @@ -39,7 +40,7 @@ alias arch arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, pow alias arches arch alias armuboot, aaribaud -alias at91 uboot, reinhardm +alias at91 uboot, abiessmann alias davinciti alias imxuboot, sbabic alias kirkwood uboot, prafulla @@ -52,7 +53,7 @@ alias tegra uboot, Simon Glass , Tom Warren , Tom Rini -alias avr32 uboot, Andreas Bießmann +alias avr32 uboot, abiessmann alias bfin uboot, vapier alias blackfin bfin -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/3] AM335x: Add USB support in u-boot.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/29/2012 08:58 PM, Marek Vasut wrote:
> Dear Harman Sohanpal,
>
>> On Sat, Jun 30, 2012 at 6:15 AM, Marek Vasut
>> wrote:
>>> Dear Harman Sohanpal,
>>>
These patches add USB support in u-boot for AM335x. The
support for host or device is selected depending on the
config selected from boards.cfg file. Host mode is selected
for USB1 and device mode is selected for USB0. Base addresses
are selected accordingly.
Gene Zarkhin (1): AM335x : Add USB support for AM335x in
u-boot
Harman Sohanpal (2): AM335x : Configs to add USB host
support. musb_udc : Fix compile warning.
>>>
>>> Dumb question ... but, can this not be made part of am35x USB
>>> ?
>>
>> Hi Marek, Well this can always be made part of am35x.c. But there
>> would be a lot of changes required in the file.
>
> Why? They use different IP block or something?
It's not an identical block so register maps have changed slightly.
More so if we get a later conversion of the other similar parts
(da850.c, davinci.c, omap3.c).
>> And also I believe it would not make much sense. It would require
>> ifdefs at a lot of places. Best example I can give to support
>> what i said is that the control register is at an offset of 4 in
>> am35x and 14 in am335x.
>
> So what, define two sets of register structures and pass them
> according to CPU ID.
>
>> I am sure adding an ifdef at that place would not seem good to
>> you to change address from 4 to 14 acc to platform.
>
> well ... struct regs_a { uint32_t padding[?]; uint32_t reg; ... };
>
> struct regs_b { uint32_t reg; ... };
>
> Create IO accessors ... like ... my_usb_writel() and my_usb_readl()
> to read and write the registers. And those accessors will cover the
> differences. Or is there more?
>
>> Is there much pain to add these 2 files?
>
> Yes, duplication of code is always bad.
>
>> In my opinion we must need to have a separate file for this.
>
> Why? If it's only about the registers, won't the approach above
> work?
>
>> This is as per my understanding. It could also cause confusions
>> to some due to name. maybe :)
>
> I'm no omap guru, Tom is. Tom?
I think what we need to do is take a shot at converting am35x.c and
am335x.c into a 'ti_musb.[ch]' and per-family header files that give
the register layout, etc, etc. We need to see how maintainable or not
such a setup will be.
- --
Tom
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Re: [U-Boot] [PATCH v2] arm,davinci: update for enbw_cmc board
On Sun, Jul 1, 2012 at 9:53 PM, Heiko Schocher wrote: > Hello Tom, > > On 15.05.2012 08:24, Heiko Schocher wrote: >> >> - change gpio pin settings: >> >> - gpio pin 6[13] (PLC reset) default value low >> - gpio pin 6[0] (TPM reset) default value low >> - 4 new GPIO pins >> pin i/o name >> - 3[9] input Board Type >> - 2[7] input HW-ID0 >> - 2[6] input HW-ID1 >> - 2[3] input HW-ID2 >> >> - read board type and hw id from gpio pins on the enbw_cmc board, >> and use board type for setting up different gpio pin settings. >> >> - do not pass "davinci_mmc.use_dma=0" to linux, as MMC now >> works with DMA. >> >> - update logbuf support: >> store post word in RTC scratch register >> >> - add support for configuring KSZ8864RMN switch through >> a config file on u-boot startup. For more infos see: >> doc/README.switch_config >> >> Signed-off-by: Heiko Schocher >> Cc: Wolfgang Denk >> Cc: Tom Rini >> Cc: Christian Riesch >> Cc: Sandeep Paulraj >> >> --- >> changes for v2: >> - add comment from Tom Rini: >> remove ELDK-4.2 compiler warning: >> enbw_cmc.c: In function 'enbw_cmc_getvalue': >> enbw_cmc.c:447: warning: dereferencing type-punned pointer will break >> strict-aliasing rules >> >> $ ./tools/checkpatch.pl 0001-arm-davinci-update-for-enbw_cmc-board.patch >> total: 0 errors, 0 warnings, 498 lines checked >> >> NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX >> MULTISTATEMENT_MACRO_USE_DO_WHILE >> >> 0001-arm-davinci-update-for-enbw_cmc-board.patch has no obvious style >> problems and is ready for submission. > > > Tom? Are there more issues with this patch? Currently sitting in u-boot-arm/master I believe. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: armv7: add compile option -mno-unaligned-access if available
Am Montag, den 02.07.2012, 10:53 +0100 schrieb Måns Rullgård: > Tetsuyuki Kobayashi writes: > > > Recent compiler generates unaligned memory access in armv7 default. > > But current U-Boot does not allow unaligned memory access, so it causes > > data abort exception. > > This patch add compile option "-mno-unaligned-access" if it is available. > > Why not allow unaligned accesses instead? > IMHO, our recent discussion showed that both ways are wrong. "-mno-unaligned-access" works around misaligned data on the software level, while allowing unaligned access does on the hardware level. What we really want is no unaligned access in U-Boot at all. Just because "-mno-unaligned-access" is the default on ARMv5, we should not consider it a gold standard. Thanks, Lucas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cm-t35: fix incorrect NAND_ECC layout selection
On Mon, Jul 02, 2012 at 03:27:59PM +0300, Nikita Kiryanov wrote: > The current configuration selects an incorrect NAND ECC layout, > which causes u-boot to write HW ECC data incorrectly. > This patch selects the right layout. > > Signed-off-by: Nikita Kiryanov This change is correct on all boards and not due to a change in NAND parts used in newer revisions or anything, correct? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: armv7: add compile option -mno-unaligned-access if available
Lucas Stach writes: > Am Montag, den 02.07.2012, 10:53 +0100 schrieb Måns Rullgård: >> Tetsuyuki Kobayashi writes: >> >> > Recent compiler generates unaligned memory access in armv7 default. >> > But current U-Boot does not allow unaligned memory access, so it causes >> > data abort exception. >> > This patch add compile option "-mno-unaligned-access" if it is available. >> >> Why not allow unaligned accesses instead? >> > IMHO, our recent discussion showed that both ways are wrong. > "-mno-unaligned-access" works around misaligned data on the software > level, while allowing unaligned access does on the hardware level. > > What we really want is no unaligned access in U-Boot at all. Just > because "-mno-unaligned-access" is the default on ARMv5, we should not > consider it a gold standard. It's slightly more complicated than that. Data can be misaligned for a variety of reasons: 1. Errors in software. 2. Specified by a file format or communication protocol. 3. Deliberately misaligned by the compiler. Misaligned data of type 1 should of course be fixed properly, not worked around in any way. Type 2 happens all the time, and has to be dealt with one way or another. If the hardware supports unaligned accesses, this is usually faster than reading a byte at a time. When targeting ARMv6 and later, recent gcc versions have started issuing deliberate unaligned accesses where previously byte by byte accesses would have been done. This happens with "packed" structs and sometimes to write multiple smaller values at once, typically when zero-initialising things. These unaligned accesses are *good*. They make code smaller and faster. The real problem here is that u-boot is setting the strict alignment checking flag, invalidating the assumption of the compiler that the system allows unaligned accesses. For ARMv5 and earlier, setting this flag is usually advisable since it makes finding accidental unaligned accesses much easier. This was debated in the context of the kernel a while ago, ultimately leading to strict alignment being disabled for ARMv6 and up [1]. [1] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=8428e84d42179c2a00f5f6450866e70d802d1d05 -- Måns Rullgård m...@mansr.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
On 19/06/2012 19:24, Fabio Estevam wrote: > commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits") > broke mx28evk boot. > > Fix it by properly adjusting the HW_DRAM_CTL29 register value. > > Suggested-by: Marek Vasut > Signed-off-by: Fabio Estevam > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] i.MX6 USDHC: Use the ESDHC clock
On 14/06/2012 15:44, Dirk Behme wrote: > From: Michael Langer > > The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces > support for the i.MX6Q MMC host controller USDHC. > > MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock > of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the > USDHC > IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 > times > higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()). > > Signed-off-by: Michael Langer > CC: Stefano Babic > CC: Jason Liu > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [GIT PULL] Pull request: u-boot-imx
Hi Albert, please pull from u-boot-imx. Thanks ! The following changes since commit 3e0cac6b5158b22248f57cdf7769bf8d610fec5e: EXYNOS: SMDK5250: Enable the pinmux setup (2012-06-25 22:51:36 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to c45272e25bdf241fbb27638465f16ce2342ed1b6: i.MX6 USDHC: Use the ESDHC clock (2012-07-02 19:53:20 +0200) Fabio Estevam (21): mx53loco: Fix revision of Dialog boards mx53: Fix mask for SATA reference clock mx53loco: Remove unused SOBJS mx53evk: Remove unused SOBJS mx53ard: Remove unused SOBJS mx53smd: Remove unused SOBJS mx51evk: Remove unused SOBJS efikamx: Remove unused SOBJS vision2: Remove unused SOBJS ima3-mx53: Remove unused SOBJS mx6qarm2: Remove unused SOBJS mx6qsabrelite: Remove unused SOBJS mx53ard: Remove unused CONFIG_MII_GASKET imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition mx28evk: Fix PSWITCH key position mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register Jason Liu (1): i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly Marek Vasut (1): i.MX28: Add function to adjust memory parameters Michael Langer (1): i.MX6 USDHC: Use the ESDHC clock Otavio Salvador (6): MX28: Fix a typo in mx28_reg_8 macro m28evk: fix board config include guardian macro name mx28evk: ensure command definition is in alphabetic order mx28evk: fix board config include guardian macro name m28evk: drop duplicated definition of CONFIG_OF_LIBFDT m28evk: use same notation to alloc the 128kB stack Vikram Narayanan (1): mx6: Avoid writing to read-only bits in imximage.cfg arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |8 arch/arm/cpu/armv7/imx-common/speed.c|4 arch/arm/cpu/armv7/mx5/clock.c |2 +- arch/arm/include/asm/arch-mx28/regs-common.h |2 +- arch/arm/include/asm/arch-mx6/mx6x_pins.h|4 ++-- board/efikamx/Makefile |7 +++ board/esg/ima3-mx53/Makefile |2 +- board/freescale/mx28evk/iomux.c | 14 ++ board/freescale/mx51evk/Makefile |7 +++ board/freescale/mx53ard/Makefile |7 +++ board/freescale/mx53evk/Makefile |7 +++ board/freescale/mx53loco/Makefile|7 +++ board/freescale/mx53loco/mx53loco.c | 12 +++- board/freescale/mx53smd/Makefile |7 +++ board/freescale/mx6qarm2/Makefile|7 +++ board/freescale/mx6qarm2/imximage.cfg|2 +- board/freescale/mx6qsabrelite/Makefile |7 +++ board/freescale/mx6qsabrelite/imximage.cfg |2 +- board/ttcontrol/vision2/Makefile |5 ++--- doc/README.mx28evk |2 +- include/configs/imx31_phycore.h |1 - include/configs/m28evk.h | 10 -- include/configs/mx28evk.h|8 include/configs/mx35pdk.h|1 - include/configs/mx53ard.h|2 -- include/configs/mx53evk.h|1 - include/configs/mx53loco.h |2 -- include/configs/mx53smd.h|1 - 28 files changed, 75 insertions(+), 66 deletions(-) -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sh/master
Dear Nobuhiro Iwamatsu, In message you wrote: > > The following changes since commit 436da3cd233e7166b5ce9293dbd28092cf37bcc9: > > ext2load: increase read speed (2012-06-21 22:49:33 +0200) > > are available in the git repository at: > > git://git.denx.de/u-boot-sh.git master > > for you to fetch changes up to 97e305cfc19c26e762e0c9d00a164db81fe23dff: > > sh: ap_sh4a_4a: Fix wrong register initialization value (2012-06-28 > 16:06:32 +0900) > > > Nobuhiro Iwamatsu (1): > sh: ap_sh4a_4a: Fix wrong register initialization value > > board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c |4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "There are three principal ways to lose money: wine, women, and engi- neers. While the first two are more pleasant, the third is by far the more certain." - Baron Rothschild, ca. 1800 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tools/mkenvimage.c: fix basename(3) usage
Dear =?UTF-8?q?Andreas=20Bie=C3=9Fmann?=, In message <1340863319-63074-1-git-send-email-andreas.de...@googlemail.com> you wrote: > Use the POSIX variant of basename due to BSD systems (e.g. OS X) do not > provide > GNU version of basename(3). It is save to use the POSIX variant here cause we > do > never use argv[0] later on which may be modified by the basename(3) POSIX > variant. > On systems providing GNU variant the GNU variant should be used since string.h > is included before libgen.h. Therefore let the _GNU_SOURCE as is. > > This patch fixes following warning (on OS X): > ---8<--- > mkenvimage.c: In function ‘main’: > mkenvimage.c:105: warning: implicit declaration of function ‘basename’ > mkenvimage.c:105: warning: assignment makes pointer from integer without a > cast > --->8--- > > Signed-off-by: Andreas Bießmann > cc: Keith Mok > --- > This was sent by Keith Mok before. Read > http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/126003 > > tools/mkenvimage.c | 1 + > 1 Datei geändert, 1 Zeile hinzugefügt(+) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Neckties strangle clear thinking. -- Lin Yutang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [STATUS] Final pull requests for -rc1?
Hello all, I would like to get out -rc1 ASAP. If you have any patches queued that should make it into the upcoming release, then plase send your pull requezts as soon as possible. Albert, what are your plans for an ARM pull req? Thanks! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You can observe a lot just by watching. - Yogi Berra ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Final pull requests for -rc1?
On Mon, Jul 02, 2012 at 08:41:56PM +0200, Wolfgang Denk wrote: > Hello all, > > I would like to get out -rc1 ASAP. If you have any patches queued > that should make it into the upcoming release, then plase send your > pull requezts as soon as possible. > > > Albert, what are your plans for an ARM pull req? I've got another round of fixes, pending a resolution for now on the USB issue that needs to come in, certainly for release and since USB isn't usable on my platforms, it'd be nice to be in -rc1. Ilya, Marek, have you guys agreed to something for now? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Issue with running commands
hi, While testing on hawkboard with the latest commit, i hit an issue of commands not being accepted. hawkboard > reset Unknown command '�' - try 'help' hawkboard > Running git bisect showed that this is caused due to commit 054ea170f271: cmd_mem: cmp: unify size code paths. Has anyone seen this issue -- i don't think this is board/arch specific. -sughosh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] microblaze: move ENV onto top of flash
Am Montag, den 02.07.2012, 07:52 +0200 schrieb Michal Simek: > 2012/7/1 Stephan Linz : > > On Microblaze systems with BPI configuration from CFI flash > > the first 1-10 MB will occupied by the FPGA configuration > > data (BIN file). So we can not use this area for the U-Boot > > environment. > > > > In most of all FPGA configuration cases the upper sector in > > flash memory will be free for individuell usage. > > is it based on any statistic? I don't think so. Hi Michal, yes, there isn't ... you are right ;) > > > > > Signed-off-by: Stephan Linz > > --- > > include/configs/microblaze-generic.h |8 +++- > > 1 files changed, 3 insertions(+), 5 deletions(-) > > nack for this. > One configuration file can't cover all fpga cases. > The reason why there is only one configuration file for microblaze is > that fpga variability. > If you want to use this option just create new board with your configuration > and use it. I can live with that, but the current configuration file defines a memory hole of 256kB in the first 2 sectors in flash. For what? -- The environment is placed in the 3rd sector. All other sectors are free for anything. I think it would be more plausible if the last sector on top will be used for environment and all other sectors down to the first would be free for anything, or not? br, Stephan > Generic microblaze board should be as simple as possible. > I am ok with adding new command/drivers and improving config but I don't want > to > support everything because it is not possible. > > Thanks, > Michal > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] nand: Hack to support 4k page in fsl_elbc_nand
On Fri, Jun 29, 2012 at 8:06 PM, Scott Wood wrote:
> On 06/28/2012 09:13 PM, Rafael Beims wrote:
>> On Thu, Jun 28, 2012 at 10:36 PM, Scott Wood wrote:
>>> On 06/28/2012 03:47 PM, Rafael Beims wrote:
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip with pagesize larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Because of this, the in flash layout of the oob is different from the
default for 4096kiB page sizes. Therefore, we need to migrate the
factory bad block markers from the original position to the new layout.
Signed-off-by: Shengzhou Liu
Signed-off-by: Liu Shuo
Signed-off-by: Rafael Beims
---
Changes in v2:
- Added check to disallow the migration code to run in devices with
page size <= 2048
drivers/mtd/nand/fsl_elbc_nand.c | 447
+++---
1 files changed, 419 insertions(+), 28 deletions(-)
>>>
>>> Thanks for working on this! I've been meaning to for a while, but have
>>> been busy with other things.
>>>
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c
b/drivers/mtd/nand/fsl_elbc_nand.c
index 9076ad4..3b6bb1d 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -76,15 +76,17 @@ struct fsl_elbc_ctrl {
/* device info */
fsl_lbc_t *regs;
- u8 __iomem *addr;/* Address of assigned FCM buffer*/
- unsigned int page; /* Last page written to / read from */
- unsigned int read_bytes; /* Number of bytes read during command */
- unsigned int column; /* Saved column from SEQIN */
- unsigned int index; /* Pointer to next byte to 'read'*/
- unsigned int status; /* status read from LTESR after last op */
- unsigned int mdr;/* UPM/FCM Data Register value */
- unsigned int use_mdr;/* Non zero if the MDR is to be set */
- unsigned int oob;/* Non zero if operating on OOB data */
+ u8 __iomem *addr; /* Address of assigned FCM buffer
*/
+ unsigned int page; /* Last page written to / read from
*/
+ unsigned int read_bytes;/* Number of bytes read during command
*/
+ unsigned int column;/* Saved column from SEQIN
*/
+ unsigned int index; /* Pointer to next byte to 'read'
*/
+ unsigned int status;/* status read from LTESR after last op
*/
+ unsigned int mdr; /* UPM/FCM Data Register value
*/
+ unsigned int use_mdr; /* Non zero if the MDR is to be set
*/
+ unsigned int oob; /* Non zero if operating on OOB data
*/
+ char *buffer; /* Just used when pagesize is greater
*/
+ /* than FCM RAM 2K limitation
*/
};
/* These map to the positions used by the FCM hardware ECC generator */
@@ -131,6 +133,15 @@ static struct nand_bbt_descr largepage_memorybased = {
.pattern = scan_ff_pattern,
};
+static u8 migrated_pattern[] = { 0xde, 0xad, 0xde, 0xad };
>>>
>>> Let's generate a proper random number here -- or at least a meaningful
>>> ASCII string. Things like the above are too common and invite magic
>>> number collision.
>>>
>>
>> Will do it.
>>
+static int fsl_elbc_migrate_badblocks(struct mtd_info *mtd,
+ struct nand_bbt_descr *bd)
+{
+ struct nand_chip *this = mtd->priv;
+ int len, numblocks, i;
+ int startblock;
+ loff_t from;
+ uint8_t *newoob, *buf;
+
+ struct fsl_elbc_mtd *priv = this->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+
+ int num_subpages = mtd->writesize / 2048-1;
+ len = mtd->writesize + mtd->oobsize;
+ numblocks = this->chipsize >> (this->phys_erase_shift - 1);
+ startblock = 0;
+ from = 0;
+
+ newoob = vmalloc(mtd->oobsize);
>>>
>>> Even if this were Linux, oobsize should never be big enough to need vmalloc.
>>>
+ memset(newoob, 0xff, mtd->writesize+mtd->oobsize);
>>>
>>> You're writing beyond the end of that buffer.
>>
>> I should have reviewed this code better... Will fix that.
>>
>>>
+ for (i = startblock; i < numblocks; i += 2) {
+ int page = (from >> this->page_shift) & this->pagemask;
+ fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ /* As we are already using the hack to read the bytes
+ * from NAND, the original badblock mar
[U-Boot] [PATCH v3 0/1] fsl_elbc support for 4k devices and factory badblock migration
This is my implementation of the factory badblock migration process for the fsl_elbc driver using the hack to support nand devices with page sizes bigger than 2048k. I would really appreciate any feedback related to the patch. Changes in v2: - Added check to disallow the migration code to run in devices with page size <= 2048 Changes in v3: - Corrected memset writing beyond newoob buffer - Corrected various code formatting errors - Cosmetic changes - Generated random magic number for migration marker - Removed direct references to nand_bbt.c code - Removed useless bbt free - Removed useless dir variable - Removed vmalloc and kmalloc calls. Only malloc() and free() used now - Start searching the migration marker from the end of NAND Rafael Beims (1): nand: Hack to support 4k page in fsl_elbc_nand drivers/mtd/nand/fsl_elbc_nand.c | 431 +++--- 1 files changed, 403 insertions(+), 28 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] nand: Hack to support 4k page in fsl_elbc_nand
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip with pagesize larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Because of this, the in flash layout of the oob is different from the
default for 4096kiB page sizes. Therefore, we need to migrate the
factory bad block markers from the original position to the new layout.
Signed-off-by: Shengzhou Liu
Signed-off-by: Liu Shuo
Signed-off-by: Rafael Beims
---
Changes in v2:
- Added check to disallow the migration code to run in devices with
page size <= 2048
Changes in v3:
- Corrected memset writing beyond newoob buffer
- Corrected various code formatting errors
- Cosmetic changes
- Generated random magic number for migration marker
- Removed direct references to nand_bbt.c code
- Removed useless bbt free
- Removed useless dir variable
- Removed vmalloc and kmalloc calls. Only malloc() and free() used now
- Start searching the migration marker from the end of NAND
drivers/mtd/nand/fsl_elbc_nand.c | 431 +++---
1 files changed, 403 insertions(+), 28 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 9076ad4..f7a9c31 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -76,15 +76,17 @@ struct fsl_elbc_ctrl {
/* device info */
fsl_lbc_t *regs;
- u8 __iomem *addr;/* Address of assigned FCM buffer*/
- unsigned int page; /* Last page written to / read from */
- unsigned int read_bytes; /* Number of bytes read during command */
- unsigned int column; /* Saved column from SEQIN */
- unsigned int index; /* Pointer to next byte to 'read'*/
- unsigned int status; /* status read from LTESR after last op */
- unsigned int mdr;/* UPM/FCM Data Register value */
- unsigned int use_mdr;/* Non zero if the MDR is to be set */
- unsigned int oob;/* Non zero if operating on OOB data */
+ u8 __iomem *addr; /* Address of assigned FCM buffer */
+ unsigned int page; /* Last page written to / read from */
+ unsigned int read_bytes;/* Number of bytes read during command */
+ unsigned int column;/* Saved column from SEQIN */
+ unsigned int index; /* Pointer to next byte to 'read' */
+ unsigned int status;/* status read from LTESR after last op */
+ unsigned int mdr; /* UPM/FCM Data Register value */
+ unsigned int use_mdr; /* Non zero if the MDR is to be set */
+ unsigned int oob; /* Non zero if operating on OOB data*/
+ uint8_t *buffer;/* Just used when pagesize is greater */
+ /* than FCM RAM 2K limitation */
};
/* These map to the positions used by the FCM hardware ECC generator */
@@ -131,6 +133,10 @@ static struct nand_bbt_descr largepage_memorybased = {
.pattern = scan_ff_pattern,
};
+static u8 migrated_pattern[] = { 0x61, 0xa1, 0x87, 0xf0 };
+#define BADBLOCK_MIGRATED_OFF 1
+#define BADBLOCK_MIGRATED_MB 3
+
/*
* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
* interfere with ECC positions, that's why we implement our own descriptors.
@@ -159,6 +165,35 @@ static struct nand_bbt_descr bbt_mirror_descr = {
.pattern = mirror_pattern,
};
+static void io_to_buffer(struct mtd_info *mtd, int subpage, int oob)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ void *src, *dst;
+ int len = oob ? 64 : 2048;
+
+ /* for emulating 4096+ bytes NAND using 2048-byte FCM RAM */
+ dst = ctrl->buffer + (oob ? mtd->writesize : 0) + subpage * len;
+ src = ctrl->addr + (oob ? 2048 : 0);
+ memcpy_fromio(dst, src, len);
+}
+
+static void buffer_to_io(struct mtd_info *mtd, int subpage, int oob)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ void *src, *dst;
+ int len = oob ? 64 : 2048;
+
+ src = ctrl->buffer + (oob ? mtd->writesize : 0) + subpage * len;
+ dst = ctrl->addr + (oob ? 2048 : 0);
+ memcpy_toio(dst, src, len);
+ /* See the in_8() in fsl_elbc_write_buf() */
+ in_8(ctrl->addr);
+}
+
/*=*/
/*
@@ -194,7 +229,7 @@ static void set_addr(struct mtd_info *mtd, int
column, int page_addr, int oob)
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl->index += priv->page_size ? 2048 : 512;
+ ctrl->index += mtd->writesize;
v
Re: [U-Boot] Issue with running commands
Dear Sughosh Ganu, In message you wrote: > > While testing on hawkboard with the latest commit, i hit an issue of > commands not being accepted. > > hawkboard > reset > Unknown command '�' - try 'help> ' > hawkboard > > > Running git bisect showed that this is caused due to commit 054ea170f271: > cmd_mem: cmp: unify size code paths. Has anyone seen this issue -- i don't > think this is board/arch specific. You must have a different kind of problem with your board. Commit 054ea170f271 is only changing the code of common/cmd_mem.c, which is not used in any way by the reset command or by the command handler or so - this cannot be causing such an effect; it could only trigger another problem by changing code size or alignment or such. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It is easier to write an incorrect program than understand a correct one. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] nand: Hack to support 4k page in fsl_elbc_nand
On 07/02/2012 04:00 PM, Rafael Beims wrote: > On Fri, Jun 29, 2012 at 8:06 PM, Scott Wood wrote: >> This raises the question of whether we should write the marker multiple >> times, or otherwise deal with the possibility that the marker gets >> bitflipped. We don't want the migration to run again, finding bogus bad >> block markes in what is now being used as a data area. >> > > Looking at the code again I realized that the intention was to have a > backup, as you said. So I guess it would be good to write the marker > more than once in other blocks for redundancy. As for the question of > whether 2 blocks is enough, I think I don't have enough experience to > tell that... Regardless of how many extras we have, if we find one but not all of the markers intact, we should repair it... which means we really need to dedicate a block to this. Simplest would be to write the marker in all pages of the block, if we're consuming the entire block anyway. Of course, to continue down the path of paranoia, what if we lose power during said repair, after erasing but before writing a marker? Make it two blocks. :-( > + /* Allocate a temporary buffer for one eraseblock incl. oob > */ > + len = (1 << this->phys_erase_shift); > + len += (len >> this->page_shift) * mtd->oobsize; > + buf = vmalloc(len); This code isn't going to be shared with Linux, so just malloc(). Likewise printf(...) instead of printk(KERN_ERR ...). BTW, should mention at least in the changelog that this is partially derived from code in nand_bbt.c. Also, using this code means we need to remove the "or later" from fsl_elbc_nand.c, because nand_bbt.c is GPL v2 only. Wolfgang probably won't be pleased. It might be better to just write it from scratch -- I'm not sure how much it really helps to be mimicking the bbt code here (without actually being able to share it), versus straightforwardly coding this specific task. >>> >>> I'm not shure I follow here. Is the use of the bbt descriptor a >>> problem? Aside from that, the code indeed is somewhat based on the >>> code on bbt (I used nand_bbt.c extensively for example code), but much >>> of it is just plain running through the blocks and searching for >>> patterns. >>> I just want to understand what needs to be different, so I can work on it. >> >> The license on nand_bbt.c is GPLv2 only. The license on fsl_elbc_nand.c >> is GPLv2 or later. So if we do use nand_bbt derived code, we need to >> change the license on fsl_elbc_nand.c, or move this code into a >> different v2-only file. The only reason I suggested that it might be >> better to just write new code is that the bbt code seems to be an >> imperfect fit, and a bit more complicated than it needs to be. >> > > I tried to remove all references to the nand_bbt code in the last > version of the patch (will follow after this). I hope that what I done > is enough. It needs to be not derived from the nand_bbt code if we're going to keep v2-or-later -- not just references removed. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-atmel/master
Dear Albert Aribaud, The following changes since commit 3e0cac6b5158b22248f57cdf7769bf8d610fec5e: EXYNOS: SMDK5250: Enable the pinmux setup (2012-06-25 22:51:36 +0200) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to f3f68232e709a1108b631410087d526cc23dfb55: AT91SAM9*: Change kernel address in dataflash to match u-boot's size (2012-07-02 22:15:05 +0200) Alexandre Belloni (1): AT91SAM9*: Change kernel address in dataflash to match u-boot's size Andreas Bießmann (1): ehci-atmel: fix compiler warning Bo Shen (3): Atmel : usb : add EHCI driver for Atmel SoC AT91: at91sam9m10g45ek : Enable EHCI instead OHCI ATMEL/PIO: Enable new feature of PIO on Atmel device e...@bus-elektronik.de (2): Fix: brocken boot message at serial line on AT91SAM9263-EK board Fix: AT91SAM9263 nor flash usage arch/arm/include/asm/arch-at91/at91_pio.h | 45 ++- board/atmel/at91sam9260ek/partition.c |6 +- board/atmel/at91sam9261ek/partition.c |6 +- board/atmel/at91sam9263ek/at91sam9263ek.c |2 +- board/atmel/at91sam9263ek/partition.c |6 +- board/atmel/at91sam9rlek/partition.c |6 +- drivers/gpio/at91_gpio.c | 125 - drivers/usb/host/Makefile |1 + drivers/usb/host/ehci-atmel.c | 89 include/configs/at91sam9260ek.h |5 +- include/configs/at91sam9261ek.h |5 +- include/configs/at91sam9263ek.h | 10 ++- include/configs/at91sam9m10g45ek.h| 20 + include/configs/at91sam9rlek.h|3 +- 14 files changed, 288 insertions(+), 41 deletions(-) create mode 100644 drivers/usb/host/ehci-atmel.c Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] beagle: removed unused pr_debug #define
From: Peter Meerwald Signed-off-by: Peter Meerwald --- board/ti/beagle/beagle.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 2214b7f..2b61cb8 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -50,8 +50,6 @@ #include #endif -#define pr_debug(fmt, args...) debug(fmt, ##args) - #define TWL4030_I2C_BUS0 #define EXPANSION_EEPROM_I2C_BUS 1 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB controllers at once
> -Original Message- > From: Stephen Warren [mailto:swar...@wwwdotorg.org] > Sent: Thursday, June 28, 2012 12:58 AM > To: Wolfgang Denk> > Cc: Jim Lin; 'U-Boot@lists.denx.de'; Tom Warren > Subject: Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB > controllers at once > > On 06/27/2012 12:55 AM, Wolfgang Denk wrote: > > Dear Jim Lin, > > > > sending the very same message eight (8!) times doesnot make it a bit > > more convincing - on contrary. > > > > In message <4b9c9637d5087840a465bdcb251780e9e2d6eda...@hkmail02.nvidia.com> > > you wrote: > >> > >>> U-Boot is not multi-tasking, so you can always access only a single > >>> USB device at a time ayway. And it is a decoumented design principle > >>> that U-Boot must not initialize any devices it does not use itself.> > >>> > >>> So why? > >> Because of this complaint and request for devices under different > >> controllers > >> to be working at same time. > > > > You make another claim here, but don't explain how this is supposed to > > work or whay the exact use case would be where this was needed. > > U-Boot will not be able to access multiple devices at the same time, > > so why would it be necessary to enable these? It should be sufficient > > to enable the controller that is responsible for the single device > > that is currently being used. > > > >> "One particularly annoying consequence of this is when you use the Seaboard > >> configuration on Springbank. > >> Seaboard selects Tegra's USB3 as "usb 0" device, which is the one you can > >> use, > >> in order not to conflict with the flashing USB port USB1. > >> However, Springbank only exposes USB1 since USB3 is used internally for the > >> USB keyboard/mouse. As such, you cannot use the USB port on Springbank > >> under > >> U-Boot at the moment. > >> " > > > > I have to admit that I cannot make any sense from this statement. The > > only thing I understand is that you are trying to use a configuration > > for one hardware (Seaboard) on another, incompatible hardware > > (Springbank). > > > > The simple answer to this problem is: don't do that, then. > Seaboard and Springbank are essentially the same board, and hence are > almost 100% SW compatible, so there's no problem running a Seaboard > build of U-Boot/kernel/... on Springbank. > The primary issue here is that many boards have multiple USB ports. > Users could plug e.g. a USB->Ethernet device into any of the ports. > Requiring the user to know which port is which ID so they can issue the > correct "usb start " command is painful; no other SW stack limits > itself to a single port and so most people don't have a clue which ports > are numbered what; they just want USB to work. > The specific issue on Springbank is that there are multiple USB ports > that are useful at the essentially the same time. One of the USB ports > hosts a built-in USB keyboard (inside a sealed clamshell/netbook case), > which we would like to use for the U-boot console. Another USB port is > external, and people will plug in a USB->Ethernet dongle or USB storage > device there. so, if I need to "usb start 0" to get the keyboard, and > "usb start 1" to get USB Ethernet, then as soon as I "usb start 1" to > get the Ethernet, I've just lost the console, and am unable to interact > with U-Boot any more.. Wolfgang, Any further thought about Stephen's request? Thanks. nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 00/13] split tegra20 arm7 code into separate SPL
Wolfgang, > -Original Message- > From: Allen Martin [mailto:amar...@nvidia.com] > Sent: Monday, June 25, 2012 3:55 PM > To: Tom Warren; swar...@wwwdotorg.org; s...@chromium.org; > thierry.red...@avionic-design.de > Cc: u-boot@lists.denx.de > Subject: [PATCH v5 00/13] split tegra20 arm7 code into separate SPL > > This patch series fixes a long standing problem with the tegra20 u-boot > build. Tegra20 contains an ARM7TDMI boot processor and a Cortex A9 main > processor. Prior to this patch series this was accomplished by #ifdefing > out any armv7 code from the early boot sequence and creating a single binary > that runs on both both the ARM7TDMI and A9. This was very fragile as > changes to compiler options or any additions or rearranging of the early > boot code could add additional armv7 specific code causing it to fail on the > ARM7TDMI. > > This patch series pulls all the armv4t code out into a separate SPL that > does nothing more than initialize the A9 and transfer control to it. The > resultint SPL and armv7 u-boot are concatenated together into a single > image. Any input on the validity of this patch series as a whole, and the changes to mkconfig/boards.cfg in particular, or any objections? I'd like to get it into u-boot-tegra/next soon. I'd also like to see all Tegra contributors sign-off or at least comment, as this is a major change (Simon, Thierry, Igor, Konstantin, Lucas, and anyone I've missed). Thanks, Tom > > This patch series is also available from: > git://github.com/arm000/u-boot.git > branch: tegra-spl-v5 > > Changes: > v5: > - added missing mkdir rules in all tegra20 board Makefiles that include > common code and changed them to be unconditional > - make new u-boot-dtb-t2.bin rule default for tegra20 and copy resulting > binary over u-boot.bin > v4: > - rebased to u-boot-tegra/next > - reordered entire patch series to preserve git bisect, verified build and > boot at each patch > - merged patches that add SPL config defines and removes duplicate code > from u-boot init, these have to go in atomically to preserve building at > each patch > - fixed compiler warnings introduced > - fixed blank line at end of file on cpu.c > - renamed u-boot.t2 to u-boot-t2.bin > - cleaned up config.mk generation in mkconfig to make it more readable > - added some text to clarify using arm720t code for arm7tdmi > - rearranged SPL memory map to make resulting SPL + u-boot image much > smaller > - removed separate PAD_TO define in favor of just using > CONFIG_SYS_TEXT_BASE > - moved warmboot_save_sdram_params() from dram_init() to board_init() > v3: > - git bisect still does not work across this series, I'm saving that for > the next revision, but I had enough changes that I wanted to get this out > for review > - expanded the tegra2 -> tegra20 rename to include functions/variables/ > defines > - rebased to u-boot-tegra/next > - removed some extra -march=armv4t flags, kept armv4t flags on > warmboot_avp since it's special > - removed bashisms from mkconfig > - renamed CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA > - moved SPL overrides to tegra2-common-post.h > - changed SPL base address to 0x108000, u-boot goes to 0x208000 > - moved warboot_save_sdram_params fix to separate patch > - remove USE_PRIVATE_LIBGCC from non SPL build > - expanded SPL support to all tegra20 boards, not just seaboard > v2: > - renamed tegra2 to tegra20 to match kernel and devicetree naming policy > - pulled all SPL related config overrides to a separate file to clean up > ifdefs from seabard.h > - rebased to TOT u-boot/master and fixed a bug related to init sequence > changes between this patch series and new EMC code > - made u-boot.t2 target work even if CONFIG_OF is disabled > - added back USE_PRIVATE_LIBGCC > > [PATCH v5 01/13] tegra20: rename tegra2 -> tegra20 [PATCH v5 02/13] tegra20: > move tegra20 SoC code to [PATCH v5 03/13] tegra20: rename > CONFIG_MACH_TEGRA_GENERIC [PATCH v5 04/13] tegra20: tec: add tegra20-common- > post.h [PATCH v5 05/13] tegra20: make board mkdir commands unconditional > [PATCH v5 06/13] mkconfig: add support for SPL CPU [PATCH v5 07/13] ARM: Fix > arm720t SPL build [PATCH v5 08/13] tegra20: remove timer_init from SPL build > [PATCH v5 09/13] ARM: add tegra20 support to arm720t [PATCH v5 10/13] > tegra20: add u-boot-t2.bin target [PATCH v5 11/13] tegra20: move SDRAM param > save to later in boot [PATCH v5 12/13] tegra20: enable SPL for tegra20 > boards [PATCH v5 13/13] tegra20: Remove armv4t build flags > > MAINTAINERS| 18 +-- > Makefile | 24 > arch/arm/cpu/arm720t/cpu.c |2 + > arch/arm/cpu/arm720t/interrupts.c |5 + > arch/arm/cpu/arm720t/start.S | 19 ++- > .../arm/cpu/arm720t/tegra20}/Makefile | 27 ++-- > .../arch-tegra2 => cpu/arm720t/tegra20}/board.h
[U-Boot] [PATCH] armv7: Fix infinite loop for the spl boot
From: Zhong Hongbo In the spl booting step, When __bss_start is equal to __bss_end__, The loop will clear all the things in CPU space. If there are have the same address for this symbol, To skip the clear bss section. Signed-off-by: Hongbo Zhong --- arch/arm/cpu/armv7/start.S |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 76ccef1..c72f337 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -258,6 +258,8 @@ clear_bss: /* No relocation for SPL */ ldr r0, =__bss_start ldr r1, =__bss_end__ + cmp r0, r1 + beq skip_clbss #else ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs @@ -271,6 +273,7 @@ clbss_l:str r2, [r0]/* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l +skip_clbss: /* * We are done. Do not return, instead branch to second part of board -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm/s5pxx: Fix get_timer_masked to get the time.
From: Zhong Hongbo
In general, The get_timer_masked function get the system time,
no the number of ticks. Such as the nand_wait_ready will use
get_timer_masked to delay the operations. And change the system
time to adopt to the CONFIG_SYS_HZ.
Signed-off-by: Hongbo Zhong
---
arch/arm/cpu/armv7/s5p-common/pwm.c |2 +-
arch/arm/cpu/armv7/s5p-common/timer.c | 20
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c
b/arch/arm/cpu/armv7/s5p-common/pwm.c
index 58d279e..44d7bc3 100644
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
@@ -170,7 +170,7 @@ int pwm_init(int pwm_id, int div, int invert)
timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
(div + 1));
- timer_rate_hz = timer_rate_hz / 100;
+ timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
/* set count value */
offset = pwm_id * 3;
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c
b/arch/arm/cpu/armv7/s5p-common/timer.c
index 359c21f..bb0e795 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -31,6 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
+unsigned long get_current_tick(void);
+
/* macro to read the 16 bit timer */
static inline struct s5p_timer *s5p_get_base_timer(void)
{
@@ -44,6 +46,8 @@ int timer_init(void)
pwm_config(4, 0, 0);
pwm_enable(4);
+ reset_timer_masked();
+
return 0;
}
@@ -72,16 +76,16 @@ void __udelay(unsigned long usec)
* 3. finish normalize.
*/
tmo = usec / 1000;
- tmo *= (CONFIG_SYS_HZ * count_value / 10);
+ tmo *= (CONFIG_SYS_HZ * count_value);
tmo /= 1000;
} else {
/* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ * count_value / 10;
+ tmo = usec * CONFIG_SYS_HZ * count_value;
tmo /= (1000 * 1000);
}
/* get current timestamp */
- tmp = get_timer(0);
+ tmp = get_current_tick();
/* if setting this fordward will roll time stamp */
/* reset "advancing" timestamp to 0, set lastinc value */
@@ -92,7 +96,7 @@ void __udelay(unsigned long usec)
tmo += tmp;
/* loop till event */
- while (get_timer_masked() < tmo)
+ while (get_current_tick() < tmo)
; /* nop */
}
@@ -108,6 +112,14 @@ void reset_timer_masked(void)
unsigned long get_timer_masked(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
+ unsigned long count_value = readl(&timer->tcntb4);
+
+ return get_current_tick() / count_value;
+}
+
+unsigned long get_current_tick(void)
+{
+ struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now = readl(&timer->tcnto4);
unsigned long count_value = readl(&timer->tcntb4);
--
1.7.5.4
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Re: [U-Boot] i.mx28 can't power off in imx-boot
Function "mx28_powerdown" can't work on my side, and uboot continue to execute next function... bootlet from freescale, relative function can power off. At 2012-07-02 20:17:26,"Marek Vasut" wrote: >Dear alex, > >> Hi: >>I can't power off the chip by function "mx28_powerdown", and I can't >> find any error on it. So I want to know whether this issue is on your >> side. The code is based on mainline imx-uboot. > >The system obviously won't powerdown as a usual ATX PC. It's only the chip >will >hang. > >> Best Regards, >> Alex > >Best regards, >Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] arm : Atmel : add at91sam9x5ek board support
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen
---
This patch is based on git://git.denx.de/u-boot-atmel.git
Changed since v1 and v2
Modify the code according to Andreas's suggestion
---
MAINTAINERS|3 +
arch/arm/cpu/arm926ejs/at91/Makefile |1 +
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 232 +++
arch/arm/cpu/arm926ejs/at91/clock.c| 12 +-
arch/arm/include/asm/arch-at91/at91sam9_matrix.h |2 +
arch/arm/include/asm/arch-at91/at91sam9x5.h| 170 +++
arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | 91 ++
arch/arm/include/asm/arch-at91/hardware.h |2 +
board/atmel/at91sam9x5ek/Makefile | 52
board/atmel/at91sam9x5ek/at91sam9x5ek.c| 299
board/atmel/at91sam9x5ek/config.mk |1 +
boards.cfg |1 +
drivers/net/macb.c |4 +-
include/configs/at91sam9x5ek.h | 184
14 files changed, 1050 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5.h
create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
create mode 100644 board/atmel/at91sam9x5ek/Makefile
create mode 100644 board/atmel/at91sam9x5ek/at91sam9x5ek.c
create mode 100644 board/atmel/at91sam9x5ek/config.mk
create mode 100644 include/configs/at91sam9x5ek.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6438e1c..a2fccbf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -660,6 +660,9 @@ Sedji Gaouaou
at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
at91sam9m10g45ekARM926EJS (AT91SAM9G45 SoC)
+Bo Shen
+ at91sam9x5ekARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+
Simon Guinot
inetspace_v2ARM926EJS (Kirkwood SoC)
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile
b/arch/arm/cpu/arm926ejs/at91/Makefile
index f333753..346e58f 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45)+= at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH)+= eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
COBJS-y += clock.o
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
new file mode 100644
index 000..7558ca2
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+unsigned int get_chip_id(void)
+{
+ /* The 0x40 is the offset of cidr in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ /* The 0x44 is the offset of exid in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1()
+{
+ return cpu_is_at91sam9x25();
+}
+
+unsigned int has_emac0()
+{
+ return !(cpu_is_at91sam9g15());
+}
+
+unsigned int has_lcdc()
+{
+ return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
+ || cpu_is_at91sam9x35();
+}
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_at91sam9x5()) {
+ switch (extension_id) {
+ case ARCH_EXID_AT91SAM9G15:
+ return CONFIG_SYS_AT91_G15_CPU_NAME;
+ case ARCH_EXID_AT91SAM9G25:
+ return CONFIG_SYS_AT91_G25_CPU_NAME;
+ case ARCH_EXID_
[U-Boot] [PATCH] mmc: dw-mmc: support DesignWare MMC controller
This patch is supported DesginWare MMC Controller.
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
Signed-off-by: Rajeshawari Shinde
---
drivers/mmc/dw_mmc.c | 388 ++
include/dwmmc.h | 186
2 files changed, 574 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/dw_mmc.c
create mode 100644 include/dwmmc.h
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
new file mode 100644
index 000..8159234
--- /dev/null
+++ b/drivers/mmc/dw_mmc.c
@@ -0,0 +1,388 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung
+ * Rajeshawari Shinde
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PAGE_SIZE 4096
+
+static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
+{
+ unsigned long timeout = 1000;
+ u32 ctrl;
+
+ dwmci_writel(host, DWMCI_CTRL, value);
+
+ while (timeout--) {
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ if (!(ctrl & DWMCI_RESET_ALL))
+ return 1;
+ if (timeout == 0)
+ break;
+ }
+ return 0;
+}
+
+static void dwmci_set_idma_desc(u8 *idmac, unsigned int des0,
+ unsigned int des1, unsigned int des2)
+{
+ struct dwmci_idmac *desc = (struct dwmci_idmac *)idmac;
+
+ desc->des0 = des0;
+ desc->des1 = des1;
+ desc->des2 = des2;
+ desc->des3 = (unsigned int)desc + sizeof(struct dwmci_idmac);
+}
+
+static void dwmci_prepare_data(struct dwmci_host *host,
+ struct mmc_data *data)
+{
+ unsigned long ctrl;
+ unsigned int i = 0, flag, cnt, blk_cnt;
+ struct dwmci_idmac *p;
+ ulong data_start, data_end, start_addr;
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, idmac, 65565);
+
+
+ p = idmac;
+ blk_cnt = data->blocks;
+
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+
+ if (data->flags == MMC_DATA_READ)
+ start_addr = (unsigned int)data->dest;
+ else
+ start_addr = (unsigned int)data->src;
+
+ do {
+ flag = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
+ flag |= (i == 0) ? DWMCI_IDMAC_FS : 0;
+ if (blk_cnt <= 8) {
+ flag |= DWMCI_IDMAC_LD;
+ cnt = data->blocksize * blk_cnt;
+ } else {
+ flag &= ~DWMCI_IDMAC_LD;
+ cnt = data->blocksize * 8;
+ }
+
+ dwmci_set_idma_desc((u8 *)p, flag, cnt,
+ start_addr + (i * PAGE_SIZE));
+
+ if (blk_cnt <= 8)
+ break;
+ blk_cnt -= 8;
+ p++;
+ i++;
+ } while(1);
+
+ data_start = (ulong)idmac;
+ data_end = (ulong)p;
+ flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+
+ dwmci_writel(host, DWMCI_DBADDR, (unsigned int)(idmac));
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ ctrl = dwmci_readl(host, DWMCI_BMOD);
+ ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
+ dwmci_writel(host, DWMCI_BMOD, ctrl);
+
+ dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+ dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
+}
+
+static int dwmci_set_transfer_mode(struct dwmci_host *host,
+ struct mmc_data *data)
+{
+ unsigned long mode;
+
+ mode = DWMCI_CMD_DATA_EXP;
+ if (data->flags & MMC_DATA_WRITE)
+ mode |= DWMCI_CMD_RW;
+
+ return mode;
+}
+
+static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ int flags = 0, i;
+ unsigned int timeout = 10;
+ u32 retry = 1;
+ u32 mask, ctrl;
+
+ while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
+ if (timeout == 0) {
+ printf("Timeout on data busy\n");
+ return TIMEOUT;
+ }
+
[U-Boot] [PATCH 0/2] EXYNOS: support the DesignWare MMC Controller
These patches is depend on [PATCH]mmc: dw-mmc: support DesignWare MMC controller. For using dw-mmc controller, need to add the some samsung specific code. Exynos specific code should be presented into exynos_dw_mmc.c Jaehoon Chung (2): EXYNOS: clock: add the get_mmc_clk function EXYNOS: mmc: support DesignWare Controller for Samsung-SoC arch/arm/cpu/armv7/exynos/clock.c| 78 ++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++ drivers/mmc/exynos_dw_mmc.c | 60 +++ 4 files changed, 175 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h create mode 100644 drivers/mmc/exynos_dw_mmc.c -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] EXYNOS: clock: add the get_mmc_clk function
To get more exactly sclk value, used the get_mmc_clk.
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/cpu/armv7/exynos/clock.c | 78
arch/arm/include/asm/arch-exynos/clk.h |1 +
2 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 2f7048b..90fa45c 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -360,6 +360,44 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
return uclk;
}
+/* exynos4: return mmc clock frequency */
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+ unsigned int pre_ratio;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ if (dev_index == 0) {
+ ratio = readl(&clk->div_fsys0);
+ pre_ratio = readl(&clk->div_fsys0);
+ } else if (dev_index == 4) {
+ ratio = readl(&clk->div_fsys3);
+ pre_ratio = readl(&clk->div_fsys3);
+ } else
+ return 0;
+
+ ratio = ratio & 0xf;
+ pre_ratio = (pre_ratio >> (dev_index + 8)) & 0xff;
+ uclk = (sclk /(ratio + 1))/(pre_ratio + 1);
+
+ return uclk;
+}
+
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -387,6 +425,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned
int div)
writel(val, addr);
}
+/* exynos5: return mmc clock frequency */
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+ unsigned int pre_ratio;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ ratio = readl(&clk->div_fsys1);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+ pre_ratio = readl(&clk->div_fsys1);
+ pre_ratio = (pre_ratio >> ((dev_index<< 4) + 8)) & 0xff;
+
+ uclk = (sclk /(ratio + 1))/(pre_ratio + 1);
+
+ return uclk;
+}
+
/* exynos5: set the mmc clock */
static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -446,6 +516,14 @@ unsigned long get_uart_clk(int dev_index)
return exynos4_get_uart_clk(dev_index);
}
+unsigned long get_mmc_clk(int dev_index)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_mmc_clk(dev_index);
+ else
+ return exynos4_get_mmc_clk(dev_index);
+}
+
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ff0f641..9e9d390 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -31,6 +31,7 @@
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_pwm_clk(void);
+unsigned long get_mmc_clk(int dev_index);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
--
1.7.4.1
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[U-Boot] [PATCH 2/2] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Support DesignWare MMC Controller for Samsung Specific.
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
Signed-off-by: Rajeshawari Shinde
---
arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++
drivers/mmc/exynos_dw_mmc.c | 60 ++
2 files changed, 96 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h
create mode 100644 drivers/mmc/exynos_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
new file mode 100644
index 000..2e4354d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#define DWMCI_CLKSEL 0x09C
+#define DWMCI_SHIFT_0 0x0
+#define DWMCI_SHIFT_1 0x1
+#define DWMCI_SHIFT_2 0x2
+#define DWMCI_SHIFT_3 0x3
+#define DWMCI_SET_SAMPLE_CLK(x)(x)
+#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+
+int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index);
+
+static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
+{
+ unsigned int base = samsung_get_base_mmc() + (0x1 * index);
+ return exynos_dwmci_init(base, 5000, 40, index);
+}
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
new file mode 100644
index 000..e9b0e1d
--- /dev/null
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static char *EXYNOS_NAME = "EXYNOS DWMMC";
+
+static void exynos_dwmci_clksel(struct dwmci_host *host)
+{
+ u32 val;
+ val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
+ DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+
+ dwmci_writel(host, DWMCI_CLKSEL, val);
+}
+
+int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index)
+{
+ struct dwmci_host *host = NULL;
+ host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ printf("dwmci_host malloc fail!\n");
+ return 1;
+ }
+
+ host->name = EXYNOS_NAME;
+ host->ioaddr = (void *)regbase;
+ host->quirks = quirks;
+ host->buswidth = bus_width;
+ host->fifoth_val = 0x20100010;
+ host->clksel = exynos_dwmci_clksel;
+ host->dev_index = index;
+ host->get_mmc_clk = get_mmc_clk;
+
+ add_dwmci(host, 5200, 40, index);
+
+ return 0;
+}
+
--
1.7.4.1
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Re: [U-Boot] [PATCH 2/2] microblaze: move ENV onto top of flash
On 07/02/2012 09:36 PM, Stephan Linz wrote: Am Montag, den 02.07.2012, 07:52 +0200 schrieb Michal Simek: 2012/7/1 Stephan Linz: On Microblaze systems with BPI configuration from CFI flash the first 1-10 MB will occupied by the FPGA configuration data (BIN file). So we can not use this area for the U-Boot environment. In most of all FPGA configuration cases the upper sector in flash memory will be free for individuell usage. is it based on any statistic? I don't think so. Hi Michal, yes, there isn't ... you are right ;) Signed-off-by: Stephan Linz --- include/configs/microblaze-generic.h |8 +++- 1 files changed, 3 insertions(+), 5 deletions(-) nack for this. One configuration file can't cover all fpga cases. The reason why there is only one configuration file for microblaze is that fpga variability. If you want to use this option just create new board with your configuration and use it. I can live with that, but the current configuration file defines a memory hole of 256kB in the first 2 sectors in flash. For what? -- The environment is placed in the 3rd sector. All other sectors are free for anything. For u-boot itself. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] microblaze: Wire up fdt emaclite initialization
On 06/29/2012 10:22 PM, Stephan Linz wrote:
Am Freitag, den 29.06.2012, 09:37 +0200 schrieb Michal Simek:
Call emaclite FDT registration when CONFIG_OF_CONTROL is used.
Signed-off-by: Michal Simek
---
.../xilinx/microblaze-generic/microblaze-generic.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c
b/board/xilinx/microblaze-generic/microblaze-generic.c
index a1e2bfe..4a719ba 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -73,6 +73,9 @@ int board_eth_init(bd_t *bis)
{
int ret = 0;
+#ifdef CONFIG_OF_CONTROL
+ ret |= xilinx_emaclite_init(bis);
+#else
First of all: I've successful tested on an AXI system on Avnet S6LX9
micro-module.
Now some words to the different configuration strategy. I prefer a
seperation between the ongoing development without device tree support
and the upcoming development with fdt support.
Could you split the development in the context of boards, for example:
OLD: Development w/o fdt in:
- board/xilinx/microblaze-generic/*
- configuration in include/configs/microblaze-generic.h
NEW: Development with fdt in:
- board/xilinx/microblaze-fdt/*
- configuration in include/configs/microblaze-fdt.h
So you can start with a really clean and slimmed board configuration for
fdt development (especially the content of config header) and the old
generic board support would be retained. Anytime in the future, when the
generic configuration will become obsolete you can remove it.
I don't think this is good idea to split it.
All the time when you split development to different trees/configuration they
start
to diverge and then you just need to spend more a more time to manage both.
My strategy will be to add both configuration together.
It will have also demonstration purpose to show up differences.
If you want to use two boards you can.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
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Re: [U-Boot] [PATCH 2/2] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Hi Jaehoon Chung,
On Tue, Jul 3, 2012 at 10:27 AM, Jaehoon Chung wrote:
> Support DesignWare MMC Controller for Samsung Specific.
>
> Signed-off-by: Jaehoon Chung
> Signed-off-by: Kyungmin Park
> Signed-off-by: Rajeshawari Shinde
> ---
> arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++
> drivers/mmc/exynos_dw_mmc.c | 60
> ++
> 2 files changed, 96 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h
> create mode 100644 drivers/mmc/exynos_dw_mmc.c
>
> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
> b/arch/arm/include/asm/arch-exynos/dwmmc.h
> new file mode 100644
> index 000..2e4354d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
> @@ -0,0 +1,36 @@
> +/*
> + * (C) Copyright 2012 SAMSUNG Electronics
> + * Jaehoon Chung
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#define DWMCI_CLKSEL 0x09C
> +#define DWMCI_SHIFT_0 0x0
> +#define DWMCI_SHIFT_1 0x1
> +#define DWMCI_SHIFT_2 0x2
> +#define DWMCI_SHIFT_3 0x3
> +#define DWMCI_SET_SAMPLE_CLK(x)(x)
> +#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
> +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
> +
> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index);
> +
> +static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
> +{
> + unsigned int base = samsung_get_base_mmc() + (0x1 * index);
> + return exynos_dwmci_init(base, 5000, 40, index);
We donot use bus_width here ?
> +}
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> new file mode 100644
> index 000..e9b0e1d
> --- /dev/null
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -0,0 +1,60 @@
> +/*
> + * (C) Copyright 2012 SAMSUNG Electronics
> + * Jaehoon Chung
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static char *EXYNOS_NAME = "EXYNOS DWMMC";
> +
> +static void exynos_dwmci_clksel(struct dwmci_host *host)
> +{
> + u32 val;
> + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
> + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
> +
> + dwmci_writel(host, DWMCI_CLKSEL, val);
> +}
> +
> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index)
> +{
> + struct dwmci_host *host = NULL;
> + host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host));
> + if (!host) {
> + printf("dwmci_host malloc fail!\n");
> + return 1;
> + }
> +
> + host->name = EXYNOS_NAME;
> + host->ioaddr = (void *)regbase;
> + host->quirks = quirks;
> + host->buswidth = bus_width;
> + host->fifoth_val = 0x20100010;
Can this hard coding be removed?
> + host->clksel = exynos_dwmci_clksel;
> + host->dev_index = index;
> + host->get_mmc_clk = get_mmc_clk;
Can this be just mmc_clk, just a suggestion.
> +
> + add_dwmci(host, 5200, 40, index);
> +
> + return 0;
> +}
> +
> --
> 1.7.4.1
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Re: [U-Boot] [PATCH 2/2] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Hi,
On 07/03/2012 02:39 PM, Rajeshwari Birje wrote:
> Hi Jaehoon Chung,
>
>
> On Tue, Jul 3, 2012 at 10:27 AM, Jaehoon Chung wrote:
>> Support DesignWare MMC Controller for Samsung Specific.
>>
>> Signed-off-by: Jaehoon Chung
>> Signed-off-by: Kyungmin Park
>> Signed-off-by: Rajeshawari Shinde
>> ---
>> arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++
>> drivers/mmc/exynos_dw_mmc.c | 60
>> ++
>> 2 files changed, 96 insertions(+), 0 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h
>> create mode 100644 drivers/mmc/exynos_dw_mmc.c
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
>> b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> new file mode 100644
>> index 000..2e4354d
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>> @@ -0,0 +1,36 @@
>> +/*
>> + * (C) Copyright 2012 SAMSUNG Electronics
>> + * Jaehoon Chung
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> + *
>> + */
>> +
>> +#define DWMCI_CLKSEL 0x09C
>> +#define DWMCI_SHIFT_0 0x0
>> +#define DWMCI_SHIFT_1 0x1
>> +#define DWMCI_SHIFT_2 0x2
>> +#define DWMCI_SHIFT_3 0x3
>> +#define DWMCI_SET_SAMPLE_CLK(x)(x)
>> +#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>> +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>> +
>> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index);
>> +
>> +static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
>> +{
>> + unsigned int base = samsung_get_base_mmc() + (0x1 * index);
>> + return exynos_dwmci_init(base, 5000, 40, index);
> We donot use bus_width here ?
It's missing.
>> +}
>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>> new file mode 100644
>> index 000..e9b0e1d
>> --- /dev/null
>> +++ b/drivers/mmc/exynos_dw_mmc.c
>> @@ -0,0 +1,60 @@
>> +/*
>> + * (C) Copyright 2012 SAMSUNG Electronics
>> + * Jaehoon Chung
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +static char *EXYNOS_NAME = "EXYNOS DWMMC";
>> +
>> +static void exynos_dwmci_clksel(struct dwmci_host *host)
>> +{
>> + u32 val;
>> + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
>> + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
>> +
>> + dwmci_writel(host, DWMCI_CLKSEL, val);
>> +}
>> +
>> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index)
>> +{
>> + struct dwmci_host *host = NULL;
>> + host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host));
>> + if (!host) {
>> + printf("dwmci_host malloc fail!\n");
>> + return 1;
>> + }
>> +
>> + host->name = EXYNOS_NAME;
>> + host->ioaddr = (void *)regbase;
>> + host->quirks = quirks;
>> + host->buswidth = bus_width;
>> + host->fifoth_val = 0x20100010;
> Can this hard coding be removed?
Sure, we can remove this, then should be calculated with register's value at
dw_mmc.c.
But we have two approaches..
1) Use the register value.
2) Set the fifoth_Val.
If you want to remove, don't mind..but i didn't ensure to work well.
>> + host->clksel = exynos_dwmci_clksel;
>> + host->dev_index = index;
>> + host->get_mmc_clk = get_mmc_clk;
> Can this be just mmc_clk, just a suggestion.
Sure..i will change the host->mmc_clk.
>> +
>> + add_dwmci(host, 5200, 40, index);
>
[U-Boot] [PATCH v6 03/15] tegra20: rename CONFIG_MACH_TEGRA_GENERIC
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA. The meaning of the config options is now: CONFIG_TEGRA - Any tegra chip CONFIG_TEGRA20 - A tegra20 family chip CONFIG_TEGRA30 - A tegra30 family chip (not added yet) Signed-off-by: Allen Martin Acked-by: Stephen Warren --- include/configs/tegra20-common.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index f3e7d46..731ab52 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -38,7 +38,7 @@ */ #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ -#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ +#define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ #define CONFIG_SYS_CACHELINE_SIZE 32 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 13/15] arm: enable libgcc build for SPL
Enable the building of private libgcc for SPL Signed-off-by: Allen Martin --- arch/arm/lib/Makefile |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 39a9550..bd3b77f 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(ARCH).o LIBGCC = $(obj)libgcc.o -ifndef CONFIG_SPL_BUILD GLSOBJS+= _ashldi3.o GLSOBJS+= _ashrdi3.o GLSOBJS+= _divsi3.o @@ -37,6 +36,7 @@ GLSOBJS += _umodsi3.o GLCOBJS+= div0.o +ifndef CONFIG_SPL_BUILD COBJS-y+= board.o COBJS-y+= bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 04/15] tegra20: tec: add tegra20-common-post.h
Add tegra20-common-post.h to be consistent with other tegra20 boards. Signed-off-by: Allen Martin Acked-by: Thierry Reding Acked-by: Stephen Warren --- include/configs/tec.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tec.h b/include/configs/tec.h index 39400d9..9b3f88d 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -79,4 +79,6 @@ "ext2load mmc 0 0x1700 /boot/uImage;" \ "bootm" +#include "tegra20-common-post.h" + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 06/15] mkconfig: add support for SPL CPU
Add support for specifying a different CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
Signed-off-by: Allen Martin
Acked-by: Stephen Warren
---
boards.cfg |5 +
doc/README.SPL | 12
mkconfig | 24
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index f7f1190..8958ba2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -11,6 +11,11 @@
# Lines starting with '#' are comments.
# Blank lines are ignored.
#
+# The CPU field takes the form:
+# cpu[:spl_cpu]
+# If spl_cpu is specified the make variable CPU will be set to this
+# during the SPL build.
+#
# The options field takes the form:
# [:comma separated config options]
# Each config option has the form (value defaults to "1"):
diff --git a/doc/README.SPL b/doc/README.SPL
index 0276953..e4a5ac3 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -66,3 +66,15 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
+
+
+Normally CPU is assumed to be the same between the SPL and normal
+u-boot build. However it is possible to specify a different CPU for
+the SPL build for cases where the SPL is expected to run on a
+different CPU model from the main u-boot. This is done by specifying
+an SPL CPU in boards.cfg as follows:
+
+ normal_cpu:spl_cpu
+
+This this case CPU will be set to "normal_cpu" during the main u-boot
+build and "spl_cpu" during the SPL build.
diff --git a/mkconfig b/mkconfig
index 3e9c695..cc77a56 100755
--- a/mkconfig
+++ b/mkconfig
@@ -59,7 +59,8 @@ CONFIG_NAME="${1%_config}"
[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
arch="$2"
-cpu="$3"
+cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
+spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
if [ "$4" = "-" ] ; then
board=${BOARD_NAME}
else
@@ -130,13 +131,20 @@ fi
#
# Create include file for Make
#
-echo "ARCH = ${arch}" > config.mk
-echo "CPU= ${cpu}" >> config.mk
-echo "BOARD = ${board}" >> config.mk
-
-[ "${vendor}" ] && echo "VENDOR = ${vendor}" >> config.mk
-
-[ "${soc}"] && echo "SOC= ${soc}">> config.mk
+( echo "ARCH = ${arch}"
+if [ ! -z "$spl_cpu" ] ; then
+ echo 'ifeq ($(CONFIG_SPL_BUILD),y)'
+ echo "CPU= ${spl_cpu}"
+ echo "else"
+ echo "CPU= ${cpu}"
+ echo "endif"
+else
+ echo "CPU= ${cpu}"
+fi
+echo "BOARD = ${board}"
+
+[ "${vendor}" ] && echo "VENDOR = ${vendor}"
+[ "${soc}"] && echo "SOC= ${soc}" ) > config.mk
# Assign board directory to BOARDIR variable
if [ -z "${vendor}" ] ; then
--
1.7.9.5
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[U-Boot] [PATCH v6 08/15] tegra20: remove timer_init from SPL build
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin
Acked-by: Stephen Warren
---
board/nvidia/common/board.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 90a77e2..f349243 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -49,6 +49,7 @@ const struct tegra20_sysinfo sysinfo = {
CONFIG_TEGRA20_BOARD_STRING
};
+#ifndef CONFIG_SPL_BUILD
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
@@ -57,6 +58,7 @@ int timer_init(void)
{
return 0;
}
+#endif
void __pin_mux_usb(void)
{
--
1.7.9.5
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[U-Boot] [PATCH v6 10/15] tegra20: add u-boot-*-tegra.bin targets
Add target for tegra20 u-boot image. This is a concatenation of tegra
spl and normal u-boot binaries. For non-devicetree builds this is
named "u-boot-nodtb-tegra.bin" for devicetree builds is named
"u-boot-dtb-tegra.bin".
Signed-off-by: Allen Martin
---
Makefile | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Makefile b/Makefile
index f371dac..18c1465 100644
--- a/Makefile
+++ b/Makefile
@@ -456,6 +456,20 @@ $(obj)u-boot.sb: $(obj)u-boot.bin
$(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin:$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(obj)u-boot.dtb
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin
$(obj)u-boot.dtb > $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+else
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+endif
+endif
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
--
1.7.9.5
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[U-Boot] [PATCH v6 15/15] tegra20: Remove armv4t build flags
These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin Acked-by: Stephen Warren --- arch/arm/cpu/armv7/tegra20/config.mk | 12 arch/arm/cpu/tegra20-common/Makefile |2 -- 2 files changed, 14 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra20/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk index 714daaf..6432e75 100644 --- a/arch/arm/cpu/armv7/tegra20/config.mk +++ b/arch/arm/cpu/armv7/tegra20/config.mk @@ -23,16 +23,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these -# files with compatible flags -ifdef CONFIG_TEGRA20 -CFLAGS_arch/arm/lib/board.o += -march=armv4t -CFLAGS_arch/arm/lib/memset.o += -march=armv4t -CFLAGS_lib/string.o += -march=armv4t -CFLAGS_common/cmd_nvedit.o += -march=armv4t -endif - -USE_PRIVATE_LIBGCC = yes - CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 60be2a6..43c96c6 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -27,8 +27,6 @@ include $(TOPDIR)/config.mk # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/tegra20-common/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/tegra20-common/clock.o += -march=armv4t CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t LIB= $(obj)lib$(SOC)-common.o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 00/15] split tegra20 arm7 code into separate SPL
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series this was
accomplished by #ifdefing out any armv7 code from the early boot
sequence and creating a single binary that runs on both both the
ARM7TDMI and A9. This was very fragile as changes to compiler options
or any additions or rearranging of the early boot code could add
additional armv7 specific code causing it to fail on the ARM7TDMI.
This patch series pulls all the armv4t code out into a separate SPL
that does nothing more than initialize the A9 and transfer control to
it. The resultint SPL and armv7 u-boot are concatenated together into
a single image.
This patch series is also available from:
git://github.com/arm000/u-boot.git
branch: tegra-spl-v6
Changes:
v6:
- changed combined SPL/u-boot target names to u-boot-dtb-tegra.bin
and u-boot-nodtb-tegra.bin
- fixed regression introduced in v5 that caused git bisect to fail to
build at one of the patches
- fix USE_PRIVATE_LIBGCC for SPL build and enable it
- fix libtegra20-common.so link so it works if building with out of
tree OBJDIR
v5:
- added missing mkdir rules in all tegra20 board Makefiles that
include common code and changed them to be unconditional
- make new u-boot-dtb-t2.bin rule default for tegra20 and copy
resulting binary over u-boot.bin
v4:
- rebased to u-boot-tegra/next
- reordered entire patch series to preserve git bisect, verified
build and boot at each patch
- merged patches that add SPL config defines and removes duplicate
code from u-boot init, these have to go in atomically to preserve
building at each patch
- fixed compiler warnings introduced
- fixed blank line at end of file on cpu.c
- renamed u-boot.t2 to u-boot-t2.bin
- cleaned up config.mk generation in mkconfig to make it more
readable
- added some text to clarify using arm720t code for arm7tdmi
- rearranged SPL memory map to make resulting SPL + u-boot image much
smaller
- removed separate PAD_TO define in favor of just using
CONFIG_SYS_TEXT_BASE
- moved warmboot_save_sdram_params() from dram_init() to board_init()
v3:
- git bisect still does not work across this series, I'm saving that
for the next revision, but I had enough changes that I wanted to get
this out for review
- expanded the tegra2 -> tegra20 rename to include
functions/variables/
defines
- rebased to u-boot-tegra/next
- removed some extra -march=armv4t flags, kept armv4t flags on
warmboot_avp since it's special
- removed bashisms from mkconfig
- renamed CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA
- moved SPL overrides to tegra2-common-post.h
- changed SPL base address to 0x108000, u-boot goes to 0x208000
- moved warboot_save_sdram_params fix to separate patch
- remove USE_PRIVATE_LIBGCC from non SPL build
- expanded SPL support to all tegra20 boards, not just seaboard
v2:
- renamed tegra2 to tegra20 to match kernel and devicetree naming
policy
- pulled all SPL related config overrides to a separate file to clean
up ifdefs from seabard.h
- rebased to TOT u-boot/master and fixed a bug related to init
sequence changes between this patch series and new EMC code
- made u-boot.t2 target work even if CONFIG_OF is disabled
- added back USE_PRIVATE_LIBGCC
[PATCH v6 01/15] tegra20: rename tegra2 -> tegra20
[PATCH v6 02/15] tegra20: move tegra20 SoC code to
[PATCH v6 03/15] tegra20: rename CONFIG_MACH_TEGRA_GENERIC
[PATCH v6 04/15] tegra20: tec: add tegra20-common-post.h
[PATCH v6 05/15] tegra20: make board mkdir commands unconditional
[PATCH v6 06/15] mkconfig: add support for SPL CPU
[PATCH v6 07/15] ARM: Fix arm720t SPL build
[PATCH v6 08/15] tegra20: remove timer_init from SPL build
[PATCH v6 09/15] ARM: add tegra20 support to arm720t
[PATCH v6 10/15] tegra20: add u-boot-*-tegra.bin targets
[PATCH v6 11/15] tegra20: move SDRAM param save to later in boot
[PATCH v6 12/15] tegra20: enable SPL for tegra20 boards
[PATCH v6 13/15] arm: enable libgcc build for SPL
[PATCH v6 14/15] spl: fix SPL build of private libgcc
[PATCH v6 15/15] tegra20: Remove armv4t build flags
MAINTAINERS| 18 +--
Makefile | 26
arch/arm/cpu/arm720t/cpu.c |2 +
arch/arm/cpu/arm720t/interrupts.c |5 +
arch/arm/cpu/arm720t/start.S | 19 ++-
.../arm/cpu/arm720t/tegra20}/Makefile | 27 ++--
.../arch-tegra2 => cpu/arm720t/tegra20}/board.h| 11 +-
.../{armv7/tegra2 => arm720t/tegra20}/config.mk| 12 --
.../{armv7/tegra2/ap20.c => arm720t/tegra20/cpu.c} | 148 ++--
.../ap20.h => cpu/arm720t/tegra20/cpu.h} | 15 +-
arch/arm/cpu/arm720t/tegra20/spl.c | 132 +
arch/arm/cpu/armv7/start.S |2 -
arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile
[U-Boot] [PATCH v6 07/15] ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code Signed-off-by: Allen Martin Acked-by: Stephen Warren --- arch/arm/cpu/arm720t/start.S | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 540e3c2..df66946 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -51,6 +51,15 @@ _start: breset ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +67,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -167,6 +177,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs @@ -425,6 +436,7 @@ lock_loop: mov pc, lr +#ifndef CONFIG_SPL_BUILD /* * * @@ -587,6 +599,7 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_NETARM) .align 5 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 11/15] tegra20: move SDRAM param save to later in boot
Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin Acked-by: Stephen Warren --- arch/arm/cpu/tegra20-common/ap20.c |5 - board/nvidia/common/board.c|3 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 8b6afbc..6ff71e0 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -345,11 +345,6 @@ void init_pmc_scratch(void) /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ odmdata = get_odmdata(); writel(odmdata, &pmc->pmc_scratch20); - -#ifdef CONFIG_TEGRA20_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif } void tegra20_start(void) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index f349243..03f629d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -126,6 +126,9 @@ int board_init(void) #endif #ifdef CONFIG_TEGRA20_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 12/15] tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin
---
Makefile |9 ++
arch/arm/cpu/armv7/start.S|2 -
arch/arm/cpu/tegra20-common/ap20.c| 258 +
arch/arm/cpu/tegra20-common/board.c | 23 +--
boards.cfg| 18 +--
include/configs/tegra20-common-post.h | 65 +
include/configs/tegra20-common.h | 22 ++-
7 files changed, 104 insertions(+), 293 deletions(-)
diff --git a/Makefile b/Makefile
index 18c1465..ff04503 100644
--- a/Makefile
+++ b/Makefile
@@ -381,6 +381,15 @@ ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
+# enable combined SPL/u-boot/dtb rules for tegra
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += $(obj)u-boot-dtb-tegra.bin
+else
+ALL-y += $(obj)u-boot-nodtb-tegra.bin
+endif
+endif
+
all: $(ALL-y) $(SUBDIR_EXAMPLES)
$(obj)u-boot.dtb: $(obj)u-boot
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5b88c55..786152f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -133,7 +133,6 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA20)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -149,7 +148,6 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra20 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/cpu/tegra20-common/ap20.c
b/arch/arm/cpu/tegra20-common/ap20.c
index 6ff71e0..2d4705a 100644
--- a/arch/arm/cpu/tegra20-common/ap20.c
+++ b/arch/arm/cpu/tegra20-common/ap20.c
@@ -20,16 +20,11 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#include
-#include
#include
-#include
-#include
#include
#include
#include
-#include
#include
#include
#include
@@ -68,235 +63,7 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_UNKNOWN;
}
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll =
- &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
- reg |= 1000 << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
-* NOTE:
-* Regardless of whether the request is to enable or disable the CPU
-* clock, every processor in the CPU complex except the master (CPU 0)
-* will have it's clock stopped because the AVP only talks to the
-* master. The AVP does not know (nor does it need to know) that there
-* are multiple processors in the CPU complex.
-*/
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
-* Read the register containing the individual CPU clock enables and
-* always stop the clock to CPU 1.
-*/
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
- u32 reg;
-
- /* R
[U-Boot] [PATCH v6 05/15] tegra20: make board mkdir commands unconditional
Change the mkdir commands for the object directories to be unconditional. This fixes an issue when building for SPL where SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE. Signed-off-by: Allen Martin --- board/avionic-design/medcom/Makefile |2 -- board/avionic-design/plutux/Makefile |2 -- board/avionic-design/tec/Makefile|2 -- board/compal/paz00/Makefile |2 -- board/compulab/trimslice/Makefile|2 -- 5 files changed, 10 deletions(-) diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/medcom/Makefile +++ b/board/avionic-design/medcom/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index 488e381..7f7287e 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -16,9 +16,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index bf624f4..ff07879 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -24,9 +24,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 02/15] tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin
Acked-by: Stephen Warren
---
Makefile |3 ++
arch/arm/cpu/armv7/tegra20/Makefile| 15 ++
.../cpu/{armv7/tegra20 => tegra20-common}/Makefile | 31 +---
.../cpu/{armv7/tegra20 => tegra20-common}/ap20.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/board.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/clock.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/crypto.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/crypto.h |0
.../cpu/{armv7/tegra20 => tegra20-common}/emc.c|0
.../{armv7/tegra20 => tegra20-common}/funcmux.c|0
.../tegra20 => tegra20-common}/lowlevel_init.S |0
.../cpu/{armv7/tegra20 => tegra20-common}/pinmux.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/pmu.c|0
.../{armv7/tegra20 => tegra20-common}/sys_info.c |0
.../cpu/{armv7/tegra20 => tegra20-common}/timer.c |0
.../{armv7/tegra20 => tegra20-common}/warmboot.c |0
.../tegra20 => tegra20-common}/warmboot_avp.c |0
.../tegra20 => tegra20-common}/warmboot_avp.h |0
spl/Makefile |4 +++
19 files changed, 23 insertions(+), 30 deletions(-)
copy arch/arm/cpu/{armv7/tegra20 => tegra20-common}/Makefile (66%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/ap20.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/board.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/clock.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/crypto.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/crypto.h (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/emc.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/funcmux.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/lowlevel_init.S (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/pinmux.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/pmu.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/sys_info.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/timer.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot_avp.c (100%)
rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot_avp.h (100%)
diff --git a/Makefile b/Makefile
index 351a8f0..f371dac 100644
--- a/Makefile
+++ b/Makefile
@@ -319,6 +319,9 @@ endif
ifeq ($(SOC),exynos)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
+ifeq ($(SOC),tegra20)
+LIBS += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+endif
LIBS := $(addprefix $(obj),$(sort $(LIBS)))
.PHONY : $(LIBS)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile
b/arch/arm/cpu/armv7/tegra20/Makefile
index da62646..5f4035d 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -23,27 +23,16 @@
# MA 02111-1307 USA
#
-# The AVP is ARMv4T architecture so we must use special compiler
-# flags for any startup files it might use.
-CFLAGS_arch/arm/cpu/armv7/tegra20/ap20.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra20/clock.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra20/warmboot_avp.o += -march=armv4t
-
include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-SOBJS := lowlevel_init.o
-COBJS-y:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
-COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
-COBJS-$(CONFIG_TEGRA20_LP0) += crypto.o warmboot.o warmboot_avp.o
COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
COBJS := $(COBJS-y)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all:$(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile
b/arch/arm/cpu/tegra20-common/Makefile
similarity index 66%
copy from arch/arm/cpu/armv7/tegra20/Makefile
copy to arch/arm/cpu/tegra20-common/Makefile
index da62646..60be2a6 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -1,7 +1,7 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -14,7 +14,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General
[U-Boot] [PATCH v6 14/15] spl: fix SPL build of private libgcc
This fixes the SPL build to link with the SPL version of libgcc if
USE_PRIVATE_LIBGCC is set to "yes". Previously it was linking with
the libgcc from the normal u-boot build because it gets set in
PLATFORM_LIBS and passed down the to the SPL build.
Signed-off-by: Allen Martin
---
spl/Makefile |6 ++
1 file changed, 6 insertions(+)
diff --git a/spl/Makefile b/spl/Makefile
index d04d2f2..c82e9de 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -66,6 +66,12 @@ ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
endif
+# Add GCC lib
+ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
+PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc,
$(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
+endif
+
START := $(addprefix $(SPLTREE)/,$(START))
LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
--
1.7.9.5
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[U-Boot] [PATCH v6 09/15] ARM: add tegra20 support to arm720t
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin Acked-by: Stephen Warren --- arch/arm/cpu/arm720t/cpu.c |2 + arch/arm/cpu/arm720t/interrupts.c|5 + arch/arm/cpu/arm720t/start.S |6 +- arch/arm/cpu/arm720t/tegra20/Makefile| 48 + arch/arm/cpu/arm720t/tegra20/board.h | 25 +++ arch/arm/cpu/arm720t/tegra20/config.mk | 26 +++ arch/arm/cpu/arm720t/tegra20/cpu.c | 258 ++ arch/arm/cpu/arm720t/tegra20/cpu.h | 100 ++ arch/arm/cpu/arm720t/tegra20/spl.c | 132 + arch/arm/include/asm/arch-tegra20/hardware.h | 29 +++ 10 files changed, 630 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm720t/tegra20/Makefile create mode 100644 arch/arm/cpu/arm720t/tegra20/board.h create mode 100644 arch/arm/cpu/arm720t/tegra20/config.mk create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.c create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.h create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 974f288..b6eee7e 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -51,6 +51,8 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_TEGRA) + /* No cleanup before linux for tegra as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 464dd30..c2f898f 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -180,6 +180,9 @@ int timer_init (void) PUT32(T0TC, 0); PUT32(T0TCR, 1);/* enable timer0 */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ + lastdec = 0; #else #error No timer_init() defined for this CPU type #endif @@ -282,6 +285,8 @@ void __udelay (unsigned long usec) #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ #else #error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index df66946..3371d3d 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -407,6 +407,8 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_TEGRA) + /* No cpu_init_crit for tegra as yet */ #else #error No cpu_init_crit() defined for current CPU type #endif @@ -422,7 +424,7 @@ lock_loop: str r1, [r0] #endif -#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -631,6 +633,8 @@ reset_cpu: .globl reset_cpu reset_cpu: mov pc, r0 +#elif defined(CONFIG_TEGRA) + /* No specific reset actions for tegra as yet */ #else #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile new file mode 100644 index 000..6e48475 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS-y+= cpu.o +CO
Re: [U-Boot] [PATCH 2/2] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Hi Jaehoon Chung,
On Tue, Jul 3, 2012 at 11:18 AM, Jaehoon Chung wrote:
> Hi,
>
> On 07/03/2012 02:39 PM, Rajeshwari Birje wrote:
>
>> Hi Jaehoon Chung,
>>
>>
>> On Tue, Jul 3, 2012 at 10:27 AM, Jaehoon Chung
>> wrote:
>>> Support DesignWare MMC Controller for Samsung Specific.
>>>
>>> Signed-off-by: Jaehoon Chung
>>> Signed-off-by: Kyungmin Park
>>> Signed-off-by: Rajeshawari Shinde
>>> ---
>>> arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++
>>> drivers/mmc/exynos_dw_mmc.c | 60
>>> ++
>>> 2 files changed, 96 insertions(+), 0 deletions(-)
>>> create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h
>>> create mode 100644 drivers/mmc/exynos_dw_mmc.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> new file mode 100644
>>> index 000..2e4354d
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
>>> @@ -0,0 +1,36 @@
>>> +/*
>>> + * (C) Copyright 2012 SAMSUNG Electronics
>>> + * Jaehoon Chung
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
>>> USA
>>> + *
>>> + */
>>> +
>>> +#define DWMCI_CLKSEL 0x09C
>>> +#define DWMCI_SHIFT_0 0x0
>>> +#define DWMCI_SHIFT_1 0x1
>>> +#define DWMCI_SHIFT_2 0x2
>>> +#define DWMCI_SHIFT_3 0x3
>>> +#define DWMCI_SET_SAMPLE_CLK(x)(x)
>>> +#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
>>> +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>>> +
>>> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index);
>>> +
>>> +static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
>>> +{
>>> + unsigned int base = samsung_get_base_mmc() + (0x1 * index);
>>> + return exynos_dwmci_init(base, 5000, 40, index);
>> We donot use bus_width here ?
>
> It's missing.
ok
>
>>> +}
>>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
>>> new file mode 100644
>>> index 000..e9b0e1d
>>> --- /dev/null
>>> +++ b/drivers/mmc/exynos_dw_mmc.c
>>> @@ -0,0 +1,60 @@
>>> +/*
>>> + * (C) Copyright 2012 SAMSUNG Electronics
>>> + * Jaehoon Chung
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>>> + *
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +static char *EXYNOS_NAME = "EXYNOS DWMMC";
>>> +
>>> +static void exynos_dwmci_clksel(struct dwmci_host *host)
>>> +{
>>> + u32 val;
>>> + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
>>> + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
>>> +
>>> + dwmci_writel(host, DWMCI_CLKSEL, val);
>>> +}
>>> +
>>> +int exynos_dwmci_init(u32 regbase, u32 quirks, int bus_width, int index)
>>> +{
>>> + struct dwmci_host *host = NULL;
>>> + host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host));
>>> + if (!host) {
>>> + printf("dwmci_host malloc fail!\n");
>>> + return 1;
>>> + }
>>> +
>>> + host->name = EXYNOS_NAME;
>>> + host->ioaddr = (void *)regbase;
>>> + host->quirks = quirks;
>>> + host->buswidth = bus_width;
>>> + host->fifoth_val = 0x20100010;
>> Can this hard coding be removed?
>
> Sure, we can remove this, then should be calculated with register's value at
> dw_mmc.c.
> But we have two approaches..
> 1) Use the register value.
> 2) Set the fifoth_Val.
> If you want to remove, don't mind..but i didn't ensure to work well.
If not working well, we can at least define it in
Re: [U-Boot] Issue with running commands
Hi Sughosh, On Mon, Jul 2, 2012 at 9:24 PM, Sughosh Ganu wrote: > hi, > While testing on hawkboard with the latest commit, i hit an issue of > commands not being accepted. > > hawkboard > reset > Unknown command '�' - try 'help' > hawkboard > > > Running git bisect showed that this is caused due to commit 054ea170f271: > cmd_mem: cmp: unify size code paths. Has anyone seen this issue -- i don't > think this is board/arch specific. I tried to reproduce this on the calimain board (AM1808 SoC), but without success. The reset command works fine with current mainline u-boot. Regards, Christian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
