Dear Rajeshwari Shinde,
On 29 June 2012 21:59, Rajeshwari Shinde <rajeshwar...@samsung.com> wrote:
> This patch adds support for BPLL clock.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwar...@samsung.com>
> ---
> Changes in V3:
> - New Patch
> Changes in V4:
> - Removed the warning message.
> arch/arm/cpu/armv7/exynos/clock.c | 26 ++++++++++++++++++++------
> arch/arm/include/asm/arch-exynos/clk.h | 1 +
> arch/arm/include/asm/arch-exynos/clock.h | 2 ++
> 3 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index dbd5f11..13e3641 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> unsigned long r, m, p, s, k = 0, mask, fout;
> - unsigned int freq, pll_div2_sel, mpll_fout_sel;
> + unsigned int freq, pll_div2_sel, fout_sel;
>
> switch (pllreg) {
> case APLL:
> @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> r = readl(&clk->vpll_con0);
> k = readl(&clk->vpll_con1);
> break;
> + case BPLL:
> + r = readl(&clk->bpll_con0);
> + break;
> default:
> printf("Unsupported PLL (%d)\n", pllreg);
> return 0;
> @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> * MPLL_CON: MIDV [25:16]
> * EPLL_CON: MIDV [24:16]
> * VPLL_CON: MIDV [24:16]
> + * BPLL_CON: MIDV [25:16]
> */
> - if (pllreg == APLL || pllreg == MPLL)
> + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> mask = 0x3ff;
> else
> mask = 0x1ff;
> @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> fout = m * (freq / (p * (1 << (s - 1))));
> }
>
> - /* According to the user manual, in EVT1 MPLL always gives
> + /* According to the user manual, in EVT1 MPLL and BPLL always gives
> * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
> - if (pllreg == MPLL) {
> + if (pllreg == MPLL || pllreg == BPLL) {
> pll_div2_sel = readl(&clk->pll_div2_sel);
> - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> +
> + switch (pllreg) {
> + case MPLL:
> + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> & MPLL_FOUT_SEL_MASK;
> - if (mpll_fout_sel == 0)
> + break;
> + case BPLL:
> + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
> + & BPLL_FOUT_SEL_MASK;
> + break;
> + }
indentation error.
please fix it.
> +
> + if (fout_sel == 0)
> fout /= 2;
> }
>
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
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