[clang] [clang][analyzer] Support `fputc` in StreamChecker (PR #71518)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland closed 
https://github.com/llvm/llvm-project/pull/71518
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[clang] [mlir] [llvm] [llvm][TypeSize] Consider TypeSize of '0' to be fixed/scalable-agnostic. (PR #72994)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> TypeSize::Scalable(0) + TypeSize::Fixed(4) == TypeSize::Fixed(4)

>From the [docs](https://llvm.org/docs/LangRef.html#t-vector)
> The number of elements is a constant integer value larger than 0; elementtype 
> may be any integer, floating-point or pointer type. Vectors of size zero are 
> not allowed. For scalable vectors, the total number of elements is a constant 
> multiple (called vscale) of the specified number of elements; vscale is a 
> positive integer that is unknown at compile time and the same 
> hardware-dependent constant for all scalable vectors at run time. The size of 
> a specific scalable vector type is thus constant within IR, even if the exact 
> size in bytes cannot be determined until run time.

Creating a scalable vector of size 0 should not even be allowed.

https://github.com/llvm/llvm-project/pull/72994
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[llvm] [clang] [mlir] [llvm][TypeSize] Consider TypeSize of '0' to be fixed/scalable-agnostic. (PR #72994)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> Correct, but that is no reason to disallow a value of '0' for TypeSize. 

Fair enough!

https://github.com/llvm/llvm-project/pull/72994
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[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland created 
https://github.com/llvm/llvm-project/pull/76575

Builtins.def says that bfloat should be represented by the 'y' character, not 
the 'b' character. The 'b' character is specified to use 'b'. The 
implementation currently uses 'b' correctly for boolean and incorrectly re-uses 
'b' for bfloat.

This was not caught since no builtins are emitted in 
build/tools/clang/include/clang/Basic/riscv_sifive_vector_builtins.inc. Don't 
know that we can test this without creating builtins that expose this issue, 
although I'm not sure we really want to do that.

>From 913ad0a5fc48429cdcd09bdbff88023427813760 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Fri, 29 Dec 2023 10:11:34 -0800
Subject: [PATCH] [Clang][RISCV] bfloat uses 'y' instead of 'b'

Builtins.def says that bfloat should be represented by the 'y'
character, not the 'b' character. The 'b' character is specified to use
'b'. The implementation currently uses 'b' correctly for boolean and incorrectly
re-uses 'b' for bfloat.

This was not caught since no builtins are emitted in
build/tools/clang/include/clang/Basic/riscv_sifive_vector_builtins.inc.
Don't know that we can test this without creating builtins that expose
this issue, although I'm not sure we really want to do that.
---
 clang/include/clang/Basic/riscv_sifive_vector.td | 2 +-
 clang/include/clang/Basic/riscv_vector_common.td | 2 +-
 clang/lib/Support/RISCVVIntrinsicUtils.cpp   | 2 +-
 clang/utils/TableGen/RISCVVEmitter.cpp   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td 
b/clang/include/clang/Basic/riscv_sifive_vector.td
index e19a34f7632fdc..0d471f6c554c22 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -109,7 +109,7 @@ multiclass RVVVFWMACCBuiltinSet> 
suffixes_prototypes> {
   Name = NAME,
   HasMasked = false,
   Log2LMUL = [-2, -1, 0, 1, 2] in
-defm NAME : RVVOutOp1Op2BuiltinSet;
+defm NAME : RVVOutOp1Op2BuiltinSet;
 }
 
 multiclass RVVVQMACCDODBuiltinSet> suffixes_prototypes> {
diff --git a/clang/include/clang/Basic/riscv_vector_common.td 
b/clang/include/clang/Basic/riscv_vector_common.td
index 4036ce8e6903f4..040db6f0cdbfb0 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -41,7 +41,7 @@
 //   x: float16_t (half)
 //   f: float32_t (float)
 //   d: float64_t (double)
-//   b: bfloat16_t (bfloat16)
+//   y: bfloat16_t (bfloat16)
 //
 // This way, given an LMUL, a record with a TypeRange "sil" will cause the
 // definition of 3 builtins. Each type "t" in the TypeRange (in this example
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp 
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index bf47461b59e0ad..2de977a3dc720b 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -203,7 +203,7 @@ void RVVType::initBuiltinStr() {
 }
 break;
   case ScalarTypeKind::BFloat:
-BuiltinStr += "b";
+BuiltinStr += "y";
 break;
   default:
 llvm_unreachable("ScalarType is invalid!");
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp 
b/clang/utils/TableGen/RISCVVEmitter.cpp
index da2a885ce8512f..d570bcae8d8636 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -151,7 +151,7 @@ static BasicType ParseBasicType(char c) {
   case 'd':
 return BasicType::Float64;
 break;
-  case 'b':
+  case 'y':
 return BasicType::BFloat16;
 break;
   default:

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[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/76575
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[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> > The 'b' character is specified to use 'b'.
> 
> Was this sentence supposed to say `bool`?

yes, updated.

https://github.com/llvm/llvm-project/pull/76575
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[clang] [Clang][RISCV] bfloat uses 'y' instead of 'b' (PR #76575)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland closed 
https://github.com/llvm/llvm-project/pull/76575
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

[Michael Maitland via cfe-commits]

@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool 
EnableExperimentalExtension,
  "string must be lowercase");
   }
 
+  bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+   Arch.starts_with("rvb") || Arch.starts_with("rvm");
+  std::string NewArch;
+  if (IsProfile) {
+const auto *FoundProfile =
+llvm::find_if(SupportedProfiles, [&](const RISCVProfile &Profile) {
+  return Arch.starts_with(Profile.Name);
+});
+
+if (FoundProfile == std::end(SupportedProfiles))
+  return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->MArch;

michaelmaitland wrote:

Do you need to declare `std::string NewArch;` above or can you introduce it 
here since it is not used above?

https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

[Michael Maitland via cfe-commits]

@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool 
EnableExperimentalExtension,
  "string must be lowercase");
   }
 
+  bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+   Arch.starts_with("rvb") || Arch.starts_with("rvm");
+  std::string NewArch;
+  if (IsProfile) {
+const auto *FoundProfile =
+llvm::find_if(SupportedProfiles, [&](const RISCVProfile &Profile) {
+  return Arch.starts_with(Profile.Name);
+});
+
+if (FoundProfile == std::end(SupportedProfiles))
+  return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->MArch;

michaelmaitland wrote:

Nevermind, I didn't see it was declared in a different scope

https://github.com/llvm/llvm-project/pull/76357
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Michael Maitland via cfe-commits]

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
 }
   }
 
-  if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+  if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);

michaelmaitland wrote:

Would it make sense to store a `Map` so 
`RISCVTargetInfo::initFeatureMap` only builds the feature map one time per 
FunctionDecl?

https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Michael Maitland via cfe-commits]

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
 }
   }
 
-  if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+  if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);

michaelmaitland wrote:

@4vtomat if the MCPU has a feature but the function explicitly disables it then 
I think we want the `-`

https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Michael Maitland via cfe-commits]

@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
 }
   }
 
-  if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+  if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);

michaelmaitland wrote:

> But we don't have the FunctionDecl info in the 
> RISCVTargetInfo::initFeatureMap call.

What about keeping this map in ASTContext instead?

https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84877
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[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> Should you also update the riscv32-toolchain-extra.c and 
> riscv64-toolchain-extra.c?

It is not immediately obvious to me what you had in mind for changing those 
tests. Could you please clarify?

https://github.com/llvm/llvm-project/pull/79929
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[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79929

>From bc844fb4e033063c0d7b5ab361c44e4823e76fa3 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 29 Jan 2024 12:33:59 -0800
Subject: [PATCH 1/3] [RISCV] Add support for RISC-V Pointer Masking

This patch implements the v0.8.1 specification. This includes support of
the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up
RISC-V pointer masking.

All of these extensions only require emitting attribute containing
correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a
2-bit WARL field (PMM). The extension does not specify how PMM is set,
and therefore this patch does not need to address this. One example of
how it *could* be set is using the Zicsr instructions to update the PMM
bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
---
 .../test/Preprocessor/riscv-target-features.c | 45 +++
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp |  6 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 34 ++
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  5 +++
 7 files changed, 114 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 2361c83a5a610..82d2efd51a091 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -142,6 +142,11 @@
 
 // Experimental extensions
 
+// CHECK-NOT: __riscv_smmpm{{.*$}}
+// CHECK-NOT: __riscv_smnpm{{.*$}}
+// CHECK-NOT: __riscv_ssnpm{{.*$}}
+// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
 // CHECK-NOT: __riscv_zalrsc {{.*$}}
@@ -1405,6 +1410,46 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
 // CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_sspm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_supm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 06292f05b90b8..d07f0480f7024 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -226,6 +226,9 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose one, a

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79929

>From fafae54117daf3d871e9df63cc4f1430a433edf0 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 29 Jan 2024 12:33:59 -0800
Subject: [PATCH 1/3] [RISCV] Add support for RISC-V Pointer Masking

This patch implements the v0.8.1 specification. This includes support of
the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up
RISC-V pointer masking.

All of these extensions only require emitting attribute containing
correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a
2-bit WARL field (PMM). The extension does not specify how PMM is set,
and therefore this patch does not need to address this. One example of
how it *could* be set is using the Zicsr instructions to update the PMM
bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
---
 .../test/Preprocessor/riscv-target-features.c | 45 +++
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.rst|  2 +
 llvm/lib/Support/RISCVISAInfo.cpp |  6 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 34 ++
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  5 +++
 7 files changed, 115 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index f81ec7ac4532f2..add96c0046cc73 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -159,6 +159,11 @@
 
 // Experimental extensions
 
+// CHECK-NOT: __riscv_smmpm{{.*$}}
+// CHECK-NOT: __riscv_smnpm{{.*$}}
+// CHECK-NOT: __riscv_ssnpm{{.*$}}
+// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
 // CHECK-NOT: __riscv_zalasr {{.*$}}
@@ -1567,6 +1572,46 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
 // CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_sspm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_supm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index e6d1f41849302e..ae043315aaae20 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -243,6 +243,9 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose on

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79929

>From e5e34889db5d64e5b918f434f16408756e8cb90d Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 29 Jan 2024 12:33:59 -0800
Subject: [PATCH] [RISCV] Add support for RISC-V Pointer Masking

This patch implements the v0.8.1 specification. This includes support of
the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up
RISC-V pointer masking.

All of these extensions only require emitting attribute containing
correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a
2-bit WARL field (PMM). The extension does not specify how PMM is set,
and therefore this patch does not need to address this. One example of
how it *could* be set is using the Zicsr instructions to update the PMM
bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
---
 .../test/Preprocessor/riscv-target-features.c | 45 +++
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp |  6 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 34 ++
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  5 +++
 7 files changed, 114 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index f81ec7ac4532f..add96c0046cc7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -159,6 +159,11 @@
 
 // Experimental extensions
 
+// CHECK-NOT: __riscv_smmpm{{.*$}}
+// CHECK-NOT: __riscv_smnpm{{.*$}}
+// CHECK-NOT: __riscv_ssnpm{{.*$}}
+// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
 // CHECK-NOT: __riscv_zalasr {{.*$}}
@@ -1567,6 +1572,46 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
 // CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_sspm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_supm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index e6d1f41849302..c9e99c9b98e37 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -243,6 +243,9 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose one, atten

[llvm] [clang] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland closed 
https://github.com/llvm/llvm-project/pull/79929
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s

michaelmaitland wrote:

updated.

https://github.com/llvm/llvm-project/pull/79015
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79015

>From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH 1/5] [RISCV] Add sifive-p670 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

This CPU prefers to not sink splat operands since it requires a s2V
transfer buffer to move scalars into buffers.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb585070..666a3e2beabeb1e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de2..84aed5c9c36fe47 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFea

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

@@ -1082,6 +1082,13 @@ def TuneShortForwardBranchOpt
 def HasShortForwardBranchOpt : 
Predicate<"Subtarget->hasShortForwardBranchOpt()">;
 def NoShortForwardBranchOpt : 
Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
 
+// P670 requires a S2V transfer buffer to move scalars into vectors.
+// FIXME: Forming .vx/.vf can reduce register pressure.
+def TuneDontSinkSplatOperands

michaelmaitland wrote:

https://github.com/llvm/llvm-project/pull/79199

https://github.com/llvm/llvm-project/pull/79015
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[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79015

>From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH 1/6] [RISCV] Add sifive-p670 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

This CPU prefers to not sink splat operands since it requires a s2V
transfer buffer to move scalars into buffers.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb585070..666a3e2beabeb1e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de2..84aed5c9c36fe47 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFea

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/79015
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands(
   if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())
 return false;
 
+  // Don't sink splat operands if the target prefers it. Some targets requires

michaelmaitland wrote:

I took the changes out of this patch. I will work on the next patch once this 
lands since there are a few fixups here and it will be easier to work off the 
squashed commit.

https://github.com/llvm/llvm-project/pull/79015
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[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland created 
https://github.com/llvm/llvm-project/pull/79929

This patch implements the v0.8.1 specification. This patch reports version 0.8 
in llvm since `RISCVISAInfo::ExtensionVersion` only has a `Major` and `Minor` 
version number. This patch includes includes support of the `Ssnpm`, `Smnpm`, 
`Smmpm`, `Sspm` and `Supm` extensions that make up RISC-V pointer masking.

All of these extensions require emitting attribute containing correct `march` 
string.

`Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM). The 
extension does not specify how PMM is set, and therefore this patch does not 
need to address this. One example of how it *could* be set is using the Zicsr 
instructions to update the PMM bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf

>From 0d1c71afab487cc1028fcfc678c111205140ac21 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 29 Jan 2024 12:33:59 -0800
Subject: [PATCH] [RISCV] Add support for RISC-V Pointer Masking

This patch implements the v0.8.1 specification. This includes support of
the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up
RISC-V pointer masking.

All of these extensions only require emitting attribute containing
correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a
2-bit WARL field (PMM). The extension does not specify how PMM is set,
and therefore this patch does not need to address this. One example of
how it *could* be set is using the Zicsr instructions to update the PMM
bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
---
 .../test/Preprocessor/riscv-target-features.c | 45 +++
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp |  6 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 34 ++
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  5 +++
 7 files changed, 114 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 2361c83a5a610..82d2efd51a091 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -142,6 +142,11 @@
 
 // Experimental extensions
 
+// CHECK-NOT: __riscv_smmpm{{.*$}}
+// CHECK-NOT: __riscv_smnpm{{.*$}}
+// CHECK-NOT: __riscv_ssnpm{{.*$}}
+// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
 // CHECK-NOT: __riscv_zalrsc {{.*$}}
@@ -1405,6 +1410,46 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
 // CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_sspm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_supm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32

[clang] [llvm] [RISCV] Add support for RISC-V Pointer Masking (PR #79929)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79929

>From 0d1c71afab487cc1028fcfc678c111205140ac21 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 29 Jan 2024 12:33:59 -0800
Subject: [PATCH 1/2] [RISCV] Add support for RISC-V Pointer Masking

This patch implements the v0.8.1 specification. This includes support of
the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up
RISC-V pointer masking.

All of these extensions only require emitting attribute containing
correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a
2-bit WARL field (PMM). The extension does not specify how PMM is set,
and therefore this patch does not need to address this. One example of
how it *could* be set is using the Zicsr instructions to update the PMM
bits of the described registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
---
 .../test/Preprocessor/riscv-target-features.c | 45 +++
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Support/RISCVISAInfo.cpp |  6 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 34 ++
 llvm/test/CodeGen/RISCV/attributes.ll | 20 +
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |  5 +++
 7 files changed, 114 insertions(+)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 2361c83a5a6102..82d2efd51a091a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -142,6 +142,11 @@
 
 // Experimental extensions
 
+// CHECK-NOT: __riscv_smmpm{{.*$}}
+// CHECK-NOT: __riscv_smnpm{{.*$}}
+// CHECK-NOT: __riscv_ssnpm{{.*$}}
+// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
 // CHECK-NOT: __riscv_zalrsc {{.*$}}
@@ -1405,6 +1410,46 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
 // CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_ssnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
+// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smnpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
+// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_smmpm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
+// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_sspm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
+// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_supm0p8 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
+// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 06292f05b90b82..d07f0480f70240 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -226,6 +226,9 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose on

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

I think this was discussed in 
https://reviews.llvm.org/D150253?id=523696#inline-1464348

https://github.com/llvm/llvm-project/pull/77866
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[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

[Michael Maitland via cfe-commits]

@@ -482,5 +482,35 @@ ParsedTargetAttr 
RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
   Ret.Tune = AttrString;
 }
   }
+
+  StringRef MCPU = this->getTargetOpts().CPU;
+  StringRef MTune = this->getTargetOpts().TuneCPU;
+
+  // attr-cpu override march only if arch isn't present.
+  if (FoundArch) {
+// If tune-cpu infer from CPU, then try to keep it.
+// Otherwise, just use current tune option.
+if (Ret.Tune.empty() && MTune.empty()) {
+  if (!Ret.CPU.empty())
+Ret.Tune = Ret.CPU; // Keep attr-cpu in tune-cpu
+  else if (!MCPU.empty())
+Ret.Tune = MCPU; // Keep mcpu in tune-cpu
+}
+
+// Reassign mcpu due to attr-arch= need
+// target-feature from mcpu/march.
+// Use attr-cpu will affect target-feature.
+Ret.CPU = MCPU;
+
+// arch= need keep target feature clean,
+// use the baseline cpu.
+if (llvm::find(Ret.Features, "__RISCV_TargetAttrNeedOverride") !=
+Ret.Features.end())
+  Ret.CPU =

michaelmaitland wrote:

I think this here is confusing because it is possible to specify a CPU that 
gets overridden if there is a full arch string. I think this drops the 
scheduler model which was not intended?

https://github.com/llvm/llvm-project/pull/75804
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[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

[Michael Maitland via cfe-commits]

@@ -482,5 +482,35 @@ ParsedTargetAttr 
RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
   Ret.Tune = AttrString;
 }
   }
+
+  StringRef MCPU = this->getTargetOpts().CPU;
+  StringRef MTune = this->getTargetOpts().TuneCPU;
+
+  // attr-cpu override march only if arch isn't present.
+  if (FoundArch) {
+// If tune-cpu infer from CPU, then try to keep it.
+// Otherwise, just use current tune option.
+if (Ret.Tune.empty() && MTune.empty()) {
+  if (!Ret.CPU.empty())
+Ret.Tune = Ret.CPU; // Keep attr-cpu in tune-cpu
+  else if (!MCPU.empty())
+Ret.Tune = MCPU; // Keep mcpu in tune-cpu
+}
+
+// Reassign mcpu due to attr-arch= need
+// target-feature from mcpu/march.
+// Use attr-cpu will affect target-feature.
+Ret.CPU = MCPU;
+
+// arch= need keep target feature clean,
+// use the baseline cpu.
+if (llvm::find(Ret.Features, "__RISCV_TargetAttrNeedOverride") !=
+Ret.Features.end())
+  Ret.CPU =

michaelmaitland wrote:

It looks like `RISCVProcessorModel` takes a name `n` which I think corresponds 
to the mcpu name, and a `SchedMachineModel m` which I thought was the 
SchedModel. But I also see that `RISCVTuneProcessorModel` seems to tie the 
SchedModel to the Tune. So maybe the answer is that it can come from both?



https://github.com/llvm/llvm-project/pull/75804
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[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

[Michael Maitland via cfe-commits]

@@ -482,5 +482,35 @@ ParsedTargetAttr 
RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
   Ret.Tune = AttrString;
 }
   }
+
+  StringRef MCPU = this->getTargetOpts().CPU;
+  StringRef MTune = this->getTargetOpts().TuneCPU;
+
+  // attr-cpu override march only if arch isn't present.
+  if (FoundArch) {
+// If tune-cpu infer from CPU, then try to keep it.
+// Otherwise, just use current tune option.
+if (Ret.Tune.empty() && MTune.empty()) {
+  if (!Ret.CPU.empty())
+Ret.Tune = Ret.CPU; // Keep attr-cpu in tune-cpu
+  else if (!MCPU.empty())
+Ret.Tune = MCPU; // Keep mcpu in tune-cpu
+}
+
+// Reassign mcpu due to attr-arch= need
+// target-feature from mcpu/march.
+// Use attr-cpu will affect target-feature.
+Ret.CPU = MCPU;
+
+// arch= need keep target feature clean,
+// use the baseline cpu.
+if (llvm::find(Ret.Features, "__RISCV_TargetAttrNeedOverride") !=
+Ret.Features.end())
+  Ret.CPU =

michaelmaitland wrote:

Thanks for sharing this code. I was looking around for it but couldn't quite 
find it.

https://github.com/llvm/llvm-project/pull/75804
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland created 
https://github.com/llvm/llvm-project/pull/79015

This is an OOO core that has a vector unit. For more information see 
https://www.sifive.com/cores/performance-p650-670.

Scheduler model and other tuning will come in separate patches.

>From abaf154799d8d739a62c5922c0d6494863432fc0 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH] [RISCV] Add sifive-p670 processor

This is an OOO core that supports vector and vector crypto. For more information
see https://www.sifive.com/cores/performance-p650-670.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb585070..666a3e2beabeb1e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de2..84aed5c9c36fe47 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
d

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79015

>From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH 1/2] [RISCV] Add sifive-p670 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

This CPU prefers to not sink splat operands since it requires a s2V
transfer buffer to move scalars into buffers.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb58507..666a3e2beabeb1 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de..84aed5c9c36fe4 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeature

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/79015
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

@@ -237,6 +237,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", 
SiFiveP400Model,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion]>;
 
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtZa64rs,
+   FeatureStdExtZic64b,
+   FeatureStdExtZicbop,
+   FeatureStdExtZicbom,
+   FeatureStdExtZicboz,
+   FeatureStdExtZiccamoa,
+   FeatureStdExtZiccif,
+   FeatureStdExtZicclsm,
+   FeatureStdExtZiccrse,
+   FeatureStdExtZihintntl,
+   FeatureStdExtZihintpause,
+   FeatureStdExtZihpm,
+   FeatureStdExtZba,
+   FeatureStdExtZbb,
+   FeatureStdExtZbs,
+   FeatureStdExtZfhmin,
+   FeatureStdExtV,
+   FeatureStdExtZvl128b,
+   FeatureStdExtZvbb,
+   FeatureStdExtZvknc,
+   FeatureStdExtZvkng,
+   FeatureStdExtZvksc,
+   FeatureStdExtZvksg,
+   FeatureFastUnalignedAccess],
+  [TuneNoDefaultUnroll,
+   TuneConditionalCompressedMoveFusion,
+   TuneLUIADDIFusion,

michaelmaitland wrote:

Updated.

https://github.com/llvm/llvm-project/pull/79015
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[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands(
   if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())
 return false;
 
+  // Don't sink splat operands if the target prefers it. Some targets requires

michaelmaitland wrote:

Updated.

https://github.com/llvm/llvm-project/pull/79015
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[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79015

>From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH 1/3] [RISCV] Add sifive-p670 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

This CPU prefers to not sink splat operands since it requires a s2V
transfer buffer to move scalars into buffers.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb585070..666a3e2beabeb1e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de2..84aed5c9c36fe47 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFea

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/79015

>From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 22 Jan 2024 07:53:55 -0800
Subject: [PATCH 1/4] [RISCV] Add sifive-p670 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

This CPU prefers to not sink splat operands since it requires a s2V
transfer buffer to move scalars into buffers.

Scheduler model and other tuning will come in separate patches.
---
 clang/test/Driver/riscv-cpus.c|  12 +-
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|   7 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   8 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  37 ++
 .../RISCV/rvv/dont-sink-splat-operands.ll | 353 ++
 6 files changed, 418 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index d181755bb58507..666a3e2beabeb1 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -241,7 +241,17 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+za64rs" "-target-feature" 
"+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03de..84aed5c9c36fe4 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeature

[clang] [llvm] [RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and Za64rs to sifive-p450. (PR #79030)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/79030
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Michael Maitland via cfe-commits]

@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
 foreach Ext = FExts in {
-  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {

michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Michael Maitland via cfe-commits]

@@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
 } // Predicates = [HasStdExtD]
 
 foreach Ext = DExts in {
-  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
+  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {

michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232
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[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> [Merge branch 'llvm:main' into 
> mgudim_veyron_def](https://github.com/llvm/llvm-project/pull/65535/commits/454b41eea50a3583ab5c29bffbd46bcd633b)

The [LLVM GitHub User Guide](https://llvm.org/docs//GitHub.html) recommends to 
rebase on main instead of merge main.

https://github.com/llvm/llvm-project/pull/65535
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[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> Is there a way to fix this now?

I think you can drop the merge commit using `git rebase -i`. You may have to 
pass `--rebase-merges` to have the ability to drop the merge commit. Then you 
can pull upstream and `git rebase upstream/main`.

https://github.com/llvm/llvm-project/pull/65535
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[clang-tools-extra] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland resolved 
https://github.com/llvm/llvm-project/pull/65535
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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

> > I think you can drop the merge commit using `git rebase -i`. You may have 
> > to pass `--rebase-merges` to have the ability to drop the merge commit. 
> > Then you can pull upstream and `git rebase upstream/main`.
> 
> Thanks Michael, I tried but messed it up (I see more changes than I 
> intended). Let me try again. If I mess it up again, is it OK if I just close 
> this PR and start over?

I think you could drop 
[5fe9e82](https://github.com/llvm/llvm-project/pull/65535/commits/5fe9e82d849b85022a0a95016c65066dbae27e4d)
 using `git rebase -i`, recommit it, and then follow the LLVM GitHub User Guide 
on how to rebase on main. 

But if you want to close this PR and make another PR, thats fine by me.

https://github.com/llvm/llvm-project/pull/65535
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[clang] [RISCV] Recognize veyron-v1 processor in clang driver. (PR #66703)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/66703
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[clang] [RISCV][GISel] Select G_SELECT (PR #67614)

[Michael Maitland via cfe-commits]

@@ -239,6 +245,11 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   }
   case TargetOpcode::G_SEXT_INREG:
 return selectSExtInreg(MI, MIB);
+  case TargetOpcode::G_SELECT:
+if (!selectSelect(MI, MIB, MRI))
+  return false;
+MI.eraseFromParent();

michaelmaitland wrote:

Looks like other `select` functions (i.e. selectSExtInreg) do 
`MI.eraseFromParent();` in `selectXX`. Should we move this one into 
`selectSelect` in the `true` cases for consistency and simplification here?

https://github.com/llvm/llvm-project/pull/67614
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[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

[Michael Maitland via cfe-commits]

@@ -318,6 +345,16 @@ multiclass VPseudoVC_XVW {
+  def "Pseudo" # NAME # "_VV_" # mx : VPseudoTernaryNoMaskWithPolicy;

michaelmaitland wrote:

Is there an 80 character limitation for TableGen? IIRC we haven't set style 
guidelines for TableGen which is why theres lots of TableGen with lines > 80 
chars.

https://github.com/llvm/llvm-project/pull/68295
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[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland unlabeled 
https://github.com/llvm/llvm-project/pull/65283
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[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland unlabeled 
https://github.com/llvm/llvm-project/pull/65283
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[clang] [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (PR #65283)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland unlabeled 
https://github.com/llvm/llvm-project/pull/65283
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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland review_requested 
https://github.com/llvm/llvm-project/pull/65535
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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

[Michael Maitland via cfe-commits]

@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}, veyron-v1

michaelmaitland wrote:

I think this should go before the end of line marker?

https://github.com/llvm/llvm-project/pull/65535
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[clang] 003078b - [Clang][Driver] Add -mcpu=help and -mtune=help to clang

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-02-28T10:45:35-08:00
New Revision: 003078b62d8d40fc000462a97c3b70e01cbe4458

URL: 
https://github.com/llvm/llvm-project/commit/003078b62d8d40fc000462a97c3b70e01cbe4458
DIFF: 
https://github.com/llvm/llvm-project/commit/003078b62d8d40fc000462a97c3b70e01cbe4458.diff

LOG: [Clang][Driver] Add -mcpu=help and -mtune=help to clang

Clang currently uses `-mcpu=?` and `-mtune=?`. The `?` causes errors on some
shells such as zsh since it is a special character. In order for it to work on
shells such as zsh, the option must be passed in quotes or escaped. This patch
adds `-mcpu=help` and `-mtune=help` as another alias for 
`--print-supported-cpus`.
In llc, `-mcpu=help` is an alias to print supported cpus.

Differential Revision: https://reviews.llvm.org/D144914

Added: 


Modified: 
clang/docs/CommandGuide/clang.rst
clang/include/clang/Driver/Options.td
clang/test/Driver/print-supported-cpus.c

Removed: 




diff  --git a/clang/docs/CommandGuide/clang.rst 
b/clang/docs/CommandGuide/clang.rst
index 7277b598f0cad..7fae1b5cec53c 100644
--- a/clang/docs/CommandGuide/clang.rst
+++ b/clang/docs/CommandGuide/clang.rst
@@ -373,6 +373,10 @@ number of cross compilers, or may only support a native 
target.
 
   Acts as an alias for :option:`--print-supported-cpus`.
 
+.. option:: -mcpu=help, -mtune=help
+
+  Acts as an alias for :option:`--print-supported-cpus`.
+
 .. option:: -march=
 
   Specify that Clang should generate code for a specific processor family

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 5b6c0e6e914d0..6bf5fafd6d7cc 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4347,6 +4347,8 @@ def print_supported_cpus : Flag<["-", "--"], 
"print-supported-cpus">,
   MarshallingInfoFlag>;
 def mcpu_EQ_QUESTION : Flag<["-"], "mcpu=?">, Alias;
 def mtune_EQ_QUESTION : Flag<["-"], "mtune=?">, Alias;
+def mcpu_EQ_help : Flag<["-"], "mcpu=help">, Alias;
+def mtune_EQ_help : Flag<["-"], "mtune=help">, Alias;
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,

diff  --git a/clang/test/Driver/print-supported-cpus.c 
b/clang/test/Driver/print-supported-cpus.c
index 468382cd955fe..8e79a011fbec8 100644
--- a/clang/test/Driver/print-supported-cpus.c
+++ b/clang/test/Driver/print-supported-cpus.c
@@ -13,6 +13,13 @@
 // RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=? -fuse-ld=dummy 2>&1 
| \
 // RUN:   FileCheck %s --check-prefix=CHECK-X86
 
+// Test -mcpu=help and -mtune=help alises.
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mcpu=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
+// RUN: %clang --target=x86_64-unknown-linux-gnu -mtune=help -fuse-ld=dummy 
2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+
 // CHECK-NOT: warning: argument unused during compilation
 // CHECK-X86: Target: x86_64-unknown-linux-gnu
 // CHECK-X86: corei7



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[clang] 55e196e - [RISCV] Add sifive-x280 processor with all of its extensions

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-05-05T07:55:07-07:00
New Revision: 55e196e7718c543b4492f2949c13de003a4ba443

URL: 
https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443
DIFF: 
https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443.diff

LOG: [RISCV] Add sifive-x280 processor with all of its extensions

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 76325311668d8..a484b07ce330a 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c764a50f88b22..845cee9e75455 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,6 +175,7 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
+* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --

diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 67b0364aa2fd7..69edacc4058c1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtV,
+   FeatureStdExtZvl512b,
+   FeatureStdExtZfh,
+   FeatureStdExtZvfh,
+   FeatureStdExtZba,
+   FeatureStdExtZbb],
+  [TuneSiFive7]>;
+
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
   SyntacoreSCR1Model,
   [Feature32Bit,



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[clang] d6bd4ea - Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-05-05T08:20:18-07:00
New Revision: d6bd4ea35437b1d39933e9526779e8c6e03125e0

URL: 
https://github.com/llvm/llvm-project/commit/d6bd4ea35437b1d39933e9526779e8c6e03125e0
DIFF: 
https://github.com/llvm/llvm-project/commit/d6bd4ea35437b1d39933e9526779e8c6e03125e0.diff

LOG: Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

This commit causes tests to fail.

This reverts commit 55e196e7718c543b4492f2949c13de003a4ba443.

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index a484b07ce330a..76325311668d8 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,20 +167,6 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
-// mcpu with default march include experimental extensions
-// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
-// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
-// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
-
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 845cee9e75455..c764a50f88b22 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,7 +175,6 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
-* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --

diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 69edacc4058c1..67b0364aa2fd7 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,22 +166,6 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
   FeatureStdExtC],
  [TuneSiFive7]>;
 
-def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
-  [Feature64Bit,
-   FeatureStdExtZifencei,
-   FeatureStdExtM,
-   FeatureStdExtA,
-   FeatureStdExtF,
-   FeatureStdExtD,
-   FeatureStdExtC,
-   FeatureStdExtV,
-   FeatureStdExtZvl512b,
-   FeatureStdExtZfh,
-   FeatureStdExtZvfh,
-   FeatureStdExtZba,
-   FeatureStdExtZbb],
-  [TuneSiFive7]>;
-
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
   SyntacoreSCR1Model,
   [Feature32Bit,



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[clang] a11dfd0 - [RISCV] Add sifive-x280 processor with all of its extensions

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-05-05T08:47:57-07:00
New Revision: a11dfd0fe6b1c38495f7de9858a2d1839d2902b9

URL: 
https://github.com/llvm/llvm-project/commit/a11dfd0fe6b1c38495f7de9858a2d1839d2902b9
DIFF: 
https://github.com/llvm/llvm-project/commit/a11dfd0fe6b1c38495f7de9858a2d1839d2902b9.diff

LOG: [RISCV] Add sifive-x280 processor with all of its extensions

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 76325311668d8..a484b07ce330a 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 1f205163a966e..ba43ba50accd9 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}, 
sifive-x280
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c764a50f88b22..845cee9e75455 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,6 +175,7 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
+* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --

diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 67b0364aa2fd7..69edacc4058c1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   Feat

[clang] 6e7ca68 - Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-05-05T09:03:06-07:00
New Revision: 6e7ca6839def260e57334040a586934011f0098d

URL: 
https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d
DIFF: 
https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d.diff

LOG: Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

Test still not working...

This reverts commit a11dfd0fe6b1c38495f7de9858a2d1839d2902b9.

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index a484b07ce330a..76325311668d8 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,20 +167,6 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
-// mcpu with default march include experimental extensions
-// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
-// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
-// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
-
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index ba43ba50accd9..1f205163a966e 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}, 
sifive-x280
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, generic, rocket, sifive-7-series{{$}}

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 845cee9e75455..c764a50f88b22 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,7 +175,6 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
-* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --

diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 69edacc4058c1..67b0364aa2fd7 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,22 +166,6 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
   FeatureStdExtC],
  [TuneSiFive7]>;
 
-def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
-  [Feature64Bit,
-   FeatureStdExtZifencei,
-   FeatureStdExtM,
-   

[clang] 8394694 - [RISCV] Add sifive-x280 processor with all of its extensions

[Michael Maitland via cfe-commits]

Author: Michael Maitland
Date: 2023-05-05T10:02:28-07:00
New Revision: 839469436afcbdf5bb6dc9b081b1bcf3a1b22fea

URL: 
https://github.com/llvm/llvm-project/commit/839469436afcbdf5bb6dc9b081b1bcf3a1b22fea
DIFF: 
https://github.com/llvm/llvm-project/commit/839469436afcbdf5bb6dc9b081b1bcf3a1b22fea.diff

LOG: [RISCV] Add sifive-x280 processor with all of its extensions

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 76325311668d8..a484b07ce330a 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,6 +167,20 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
+// mcpu with default march include experimental extensions
+// RUN: %clang -target riscv64 -### -c %s 2>&1 
-menable-experimental-extensions -mcpu=sifive-x280 | FileCheck 
-check-prefix=MCPU-SIFIVE-X280 %s
+// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" 
"+zvl32b"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" 
"+zvl64b"
+// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | 
FileCheck -check-prefix=FAIL-MCPU-NAME %s

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 1f205163a966e..ddc639dc60a80 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, 
sifive-x280{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index c764a50f88b22..845cee9e75455 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,6 +175,7 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
+* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 --

diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 67b0364aa2fd7..69edacc4058c1 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,6 +166,22 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
   FeatureStdExtC],
  [TuneSiFive7]>;
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+  [Feature64Bit,
+   FeatureStdExtZifencei,
+   Feat

[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)

[Michael Maitland via cfe-commits]

@@ -4,3 +4,12 @@
 int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
 //expected-error@+1 {{redefinition of 'foo'}}
 int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute 
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+notafeature"))) UnsupportFeature(void) { 
return 0; }
+
+//expected-warning@+1 {{unsupported 'arch=+zba,zbb' in the 'target' attribute 
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+zba,zbb"))) WithoutAddSigned(void) { return 
0; }
+
+//expected-warning@+1 {{unsupported 'arch=zba' in the 'target' attribute 
string; 'target' attribute ignored}}
+int __attribute__((target("arch=zba"))) WithoutAddSigned2(void) { return 0; }

michaelmaitland wrote:

should we add a test for `arch=-notafeature`?

https://github.com/llvm/llvm-project/pull/106495
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[clang] [llvm] [Driver] Default -msmall-data-limit= to 0 and clean up code (PR #83093)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

Adding a data point here: changing the small data limit to 0 is causing 
significant regressions on dhrystone, spec2006, spec2017, and geekbench5 on the 
sifive-x280 and sifive-p470.

Separate from this data point, a default of 8 bytes may be justified because 
most scalar primitives are 8 bytes or smaller on most architectures (boolean, 
char, int, unsigned, long, float, double, half). Data larger than this is 
likely something like arrays or structs.

https://github.com/llvm/llvm-project/pull/83093
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Michael Maitland via cfe-commits]

@@ -762,6 +773,14 @@ def HasStdExtZvkg : 
Predicate<"Subtarget->hasStdExtZvkg()">,
 AssemblerPredicate<(all_of FeatureStdExtZvkg),
 "'Zvkg' (Vector GCM instructions for Cryptography)">;
 
+def FeatureStdExtZvkgs
+: RISCVExperimentalExtension<"zvkgs", 0, 7,
+ "'Zvkgs' (Vector-Scalar GCM instructions for 
Cryptography)",
+ [FeatureStdExtZvkg]>;

michaelmaitland wrote:

>From the Zvkgs speck:

> Zvkgs depends on Zvkg

Does this part of the spec mean that Zvkg must be present too, or does it mean 
that if Zvkgs is present, then Zvkg is implied?

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Michael Maitland via cfe-commits]

@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimental-zvkgs``

michaelmaitland wrote:

Should we mention these extensions are added in the release notes?

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Michael Maitland via cfe-commits]

@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
 defvar SiFiveP400F2I  = SiFiveP400FEXQ0;
 def SiFiveP400FloatDiv: ProcResource<1>;
 
+// Vector pipeline
+def SiFiveP400VEXQ0: ProcResource<1>;

michaelmaitland wrote:

There is an issue queue in front of the vector ALU (purple). Vector loads go 
through the load/store dispatch buffer (green). Vector divisions are non 
blocking to other vector ALU operations.

We think it is okay to model VLD/VST/VDiv/VFloatDiv as standalone resources.

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

@camel-cdr

> Are the vrgather.vv numbers correct?

According to llvm-exegisis, our micro-architecture spec, and llvm-mca reports, 
we believe these numbers are correct.

> Usually LMUL>1 vrgather is implemented by applying a LMUL=1 vrgather LMUL^2 
> times. Since the LMUL=1 vrgather.vv takes a single cycle, I would've expected 
> a 4 cycle LMUL=2 vrgather.vv instead of 12.

We don't think using the approach you present here agrees with what we see in 
llvm-exegisis. We think the approach we take is a good representation.

> Oh, and did you use upstream llvm-exegesis? I didn't managed to get it to 
> work last time I tried.

This is a question for @mshockwave.

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

I want to circle back to a comment made by @asb 
[here](https://github.com/llvm/llvm-project/pull/70294#issuecomment-1782282361):
>  it's obvious that commercial designs with active support should go in

Since this is in BPi-F3, I think that it constitutes as a commercial design. 
Will this core have active support on the LLVM side?

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

Could you explain these numbers? It looks like data in some columns is missing. 

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Michael Maitland via cfe-commits]

@@ -0,0 +1,266 @@
+//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// This model covers SYNTACORE_SCR3_RV32IMC and SYNTACORE_RV64IMAC
+// configurations (syntacore-scr3-rv32/64).
+// Overview: https://syntacore.com/products/scr3
+
+// SCR3 is single-issue in-order processor
+class SyntacoreSCR3Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtD, HasStdExtZbkb, HasStdExtZbkc, 
HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+// Branching
+multiclass SCR3_Branching {
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+}
+
+// Single-cycle integer arithmetic and logic
+multiclass SCR3_IntALU {
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+}
+
+// Integer multiplication
+multiclass SCR3_IntMul {
+  let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Integer division
+multiclass SCR3_IntDiv {
+  let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Load/store instructions on SCR3 have latency 2
+multiclass SCR3_Memory {
+  let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Atomic memory
+multiclass SCR3_AtomicMemory {
+  let Latency = 20 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Others
+multiclass SCR3_Other {
+  def : WriteRes;
+  def : WriteRes;
+
+  def : InstRW<[WriteIALU], (instrs COPY)>;
+}
+
+
+multiclass SCR3_Unsupported {
+  defm : UnsupportedSchedSFB;
+  defm : UnsupportedSchedV;
+  defm : UnsupportedSchedXsfvcp;
+  defm : UnsupportedSchedZabha;
+  defm : UnsupportedSchedZba;
+  defm : UnsupportedSchedZbb;
+  defm : UnsupportedSchedZbc;
+  defm : UnsupportedSchedZbs;
+  defm : UnsupportedSchedZbkb;
+  defm : UnsupportedSchedZbkx;
+  defm : UnsupportedSchedZfa;
+  defm : UnsupportedSchedZfh;
+  defm : UnsupportedSchedZvk;
+
+  let Unsupported = true in {

michaelmaitland wrote:

Should we have an `UnsupportedSchedF` and use it here?

https://github.com/llvm/llvm-project/pull/95427
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[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland requested changes to this pull request.


https://github.com/llvm/llvm-project/pull/95427
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[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Michael Maitland via cfe-commits]

@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : 
RISCVProcessorModel<"syntacore-scr1-max",
   FeatureStdExtC],
  [TuneNoDefaultUnroll]>;
 
+def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
+  SyntacoreSCR3RV32Model,
+  [Feature32Bit,
+   FeatureStdExtI,
+   FeatureStdExtZicsr,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtC],
+  [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
+
+def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",

michaelmaitland wrote:

The PR title is misleading since it does not make clear that it adds a 
processor. Can you please change that?

This PR is missing `clang/test/Driver/riscv-cpus.c` that are required to add 
new processors. Can you also add to release notes that this processor is added?

https://github.com/llvm/llvm-project/pull/95427
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[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/95427
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Michael Maitland via cfe-commits]

@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr3-rv64 
--iterations=2 < %s | FileCheck %s --check-prefixes=CHECK,RV64

michaelmaitland wrote:

Is there a purpose for having 2 iterations instead of just 1?

Is there a better name for this test than using the first letter of every 
instruction in the sequence? Maybe SCR3-alu.s?

https://github.com/llvm/llvm-project/pull/95427
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland created 
https://github.com/llvm/llvm-project/pull/98207

bb83a3d introduced `--print-enabled-extensions` command line option for 
AArch64. This patch introduces RISC-V support for this option.

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH] [RISCV] Add ability to list extensions enabled for a target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensi

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/98207
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[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/2] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/2] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/2] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

@@ -1061,11 +1061,40 @@ For example, clang -march=rv32i_v1p0)";
 
   outs().flush();
   testing::internal::CaptureStdout();
-  riscvExtensionsHelp(DummyMap);
+  RISCVISAInfo::printSupportedExtensions(DummyMap);
   outs().flush();
 
   std::string CapturedOutput = testing::internal::GetCapturedStdout();
   EXPECT_TRUE([](std::string &Captured, std::string &Expected) {
 return Captured.find(Expected) != std::string::npos;
   }(CapturedOutput, ExpectedOutput));
 }
+
+TEST(TargetParserTest, RISCVPrintEnabledExtensions) {
+  // clang-format off
+  std::string ExpectedOutput =
+R"(Extensions enabled for the given RISC-V target
+
+Name Version   Description
+i2.1   'I' (Base Integer Instruction Set)
+
+Experimental extensions
+ztso 0.1   'Ztso' (Memory Model - Total Store Order)

michaelmaitland wrote:

is there an extension you'd like me to use?

https://github.com/llvm/llvm-project/pull/98207
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[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/3] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/3] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

@@ -116,6 +115,44 @@ void llvm::riscvExtensionsHelp(StringMap 
DescMap) {
 "For example, clang -march=rv32i_v1p0\n";
 }
 
+void RISCVISAInfo::printEnabledExtensions(
+bool IsRV64, std::set &EnabledFeatureNames,
+StringMap &DescMap) {
+  outs() << "Extensions enabled for the given RISC-V target\n\n";
+  PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
+
+  RISCVISAUtils::OrderedExtensionMap FullExtMap;
+  RISCVISAUtils::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+if (EnabledFeatureNames.count(E.Name) != 0) {
+  FullExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+}
+  for (const auto &E : ExtMap) {
+std::string Version =
+std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor);
+PrintExtension(E.first, Version, DescMap[E.first]);
+  }

michaelmaitland wrote:

I propose that we print with the current order proposed in this patch 
(canonical). If we decide that we'd like to change printing order, then we 
should have a follow up PR that changes print order for both 
`printSupportedExtensions` and `printEnabledExtensions`.

https://github.com/llvm/llvm-project/pull/98207
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[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

@@ -116,6 +115,44 @@ void llvm::riscvExtensionsHelp(StringMap 
DescMap) {
 "For example, clang -march=rv32i_v1p0\n";
 }
 
+void RISCVISAInfo::printEnabledExtensions(
+bool IsRV64, std::set &EnabledFeatureNames,
+StringMap &DescMap) {
+  outs() << "Extensions enabled for the given RISC-V target\n\n";
+  PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
+
+  RISCVISAUtils::OrderedExtensionMap FullExtMap;
+  RISCVISAUtils::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+if (EnabledFeatureNames.count(E.Name) != 0) {
+  FullExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+}
+  for (const auto &E : ExtMap) {
+std::string Version =
+std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor);
+PrintExtension(E.first, Version, DescMap[E.first]);
+  }
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions) {
+StringRef Name(E.Name);
+if (EnabledFeatureNames.count("experimental-" + Name.str()) != 0) {
+  FullExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+}
+  }
+  for (const auto &E : ExtMap) {
+std::string Version =
+std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor);
+PrintExtension(E.first, Version, DescMap["experimental-" + E.first]);
+  }
+
+  unsigned XLen = IsRV64 ? 64 : 32;
+  outs() << "\nISA String: " << RISCVISAInfo(XLen, FullExtMap).toString();

michaelmaitland wrote:

Updated.

https://github.com/llvm/llvm-project/pull/98207
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[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From 9db0919439f197408e9cb8314bd407beb18d075b Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/4] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index fae865571001c..b128f4a80ef99 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5730,7 +5730,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index 5d3f3e113e96d..e70ef52268feb 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 0229b5a140f91..c48ec23246579 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From 9db0919439f197408e9cb8314bd407beb18d075b Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/4] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index fae865571001c..b128f4a80ef99 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5730,7 +5730,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index 5d3f3e113e96d..e70ef52268feb 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 0229b5a140f91..c48ec23246579 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [llvm] [RISCV] Add ability to list extensions enabled for a target (PR #98207)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/98207

>From 9db0919439f197408e9cb8314bd407beb18d075b Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/5] [RISCV] Add ability to list extensions enabled for a
 target

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
 clang/include/clang/Driver/Options.td |  2 +-
 clang/lib/Driver/Driver.cpp   |  1 +
 clang/tools/driver/cc1_main.cpp   | 12 --
 llvm/include/llvm/TargetParser/RISCVISAInfo.h |  6 ++-
 llvm/lib/TargetParser/RISCVISAInfo.cpp| 42 ++-
 .../TargetParser/RISCVISAInfoTest.cpp | 30 -
 6 files changed, 85 insertions(+), 8 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index fae865571001c..b128f4a80ef99 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5730,7 +5730,7 @@ def print_supported_extensions : Flag<["-", "--"], 
"print-supported-extensions">
 def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"Print the extensions enabled by the given target and -march/-mcpu 
options."
-   " (AArch64 only)">,
+   " (AArch64 and RISC-V only)">,
   MarshallingInfoFlag>;
 def : Flag<["-"], "mcpu=help">, Alias;
 def : Flag<["-"], "mtune=help">, Alias;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList 
&Args,
 return;
   }
   if (Opt == options::OPT_print_enabled_extensions &&
+  !C.getDefaultToolChain().getTriple().isRISCV() &&
   !C.getDefaultToolChain().getTriple().isAArch64()) {
 C.getDriver().Diag(diag::err_opt_not_valid_on_target)
 << "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
 DescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-llvm::riscvExtensionsHelp(DescMap);
+llvm::printSupportedExtensions(DescMap);
   else if (MachineTriple.isAArch64())
 llvm::AArch64::PrintSupportedExtensions();
   else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions& 
TargetOpts) {
   for (const llvm::SubtargetFeatureKV &feature : Features)
 EnabledFeatureNames.insert(feature.Key);
 
-  if (!MachineTriple.isAArch64()) {
+  if (MachineTriple.isAArch64())
+llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+  else if (MachineTriple.isRISCV()) {
+llvm::StringMap DescMap;
+for (const llvm::SubtargetFeatureKV &feature : Features)
+  DescMap.insert({feature.Key, feature.Desc});
+llvm::printEnabledExtensions(MachineTriple.isArch64Bit(), 
EnabledFeatureNames, DescMap);
+  } else {
 // The option was already checked in Driver::HandleImmediateArgs,
 // so we do not expect to get here if we are not a supported architecture.
 assert(0 && "Unhandled triple for --print-enabled-extensions option.");
 return 1;
   }
-  llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
 
   return 0;
 }
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h 
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index 5d3f3e113e96d..e70ef52268feb 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
 #include "llvm/Support/RISCVISAUtils.h"
 
 #include 
+#include 
 #include 
 #include 
 
 namespace llvm {
-void riscvExtensionsHelp(StringMap DescMap);
+void printSupportedExtensions(StringMap &DescMap);
+void printEnabledExtensions(bool IsRV64,
+std::set &EnabledFeatureNames,
+StringMap &DescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 0229b5a140f91..c48ec23246579 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
  << Description << "\n";
 }
 
-void llvm::riscvExtensionsHelp(StringMap DescMap) {
-
+void llvm::printSupportedExtensions(StringMap &DescMap) {
   outs() << "All available -march extensions for RISC-V\n\n";
   PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
 
@@ -116,6 +115,45 @@ void llvm:

[clang] [clang] Distinguish unresolved templates in UnresolvedLookupExpr (PR #89019)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/89019

>From 89a5bbcc89c1e43ac7f2e60f3c234c2c42928c86 Mon Sep 17 00:00:00 2001
From: Younan Zhang 
Date: Wed, 17 Apr 2024 12:24:56 +0800
Subject: [PATCH 1/7] [clang] Distinguish unresolved templates in
 UnresolvedLookupExpr

This patch revolves around the misuse of UnresolvedLookupExpr in
BuildTemplateIdExpr.

Basically, we build up an UnresolvedLookupExpr not only for function
overloads but for "unresolved" templates wherever we need an expression
for template decls. For example, a dependent VarTemplateDecl can be
wrapped with such an expression before template instantiation. (See
https://github.com/llvm/llvm-project/commit/617007240cbfb97c8ccf6d61b0c4ca0bb62d43c9)

Also, one important thing is that UnresolvedLookupExpr uses a "canonical"
QualType to describe the containing unresolved decls: a DependentTy is
for dependent expressions and an OverloadTy otherwise. Therefore, this
modeling for non-dependent templates leaves a problem in that the expression
is marked and perceived as if describing overload functions. The consumer then
expects functions for every such expression, although the fact is the reverse.
Hence, we run into crashes.

As to the patch, I added a new canonical type "UnresolvedTemplateTy" to
model these cases. Given that we have been using this model (intentionally or
accidentally) and it is pretty baked in throughout the code, I think
extending the role of UnresolvedLookupExpr is reasonable. Further, I added
some diagnostics for the direct occurrence of these expressions, which
are supposed to be ill-formed.

As a bonus, this patch also fixes some typos in the diagnostics and creates
RecoveryExprs rather than nothing in the hope of a better error-recovery
for clangd.

Fixes https://github.com/llvm/llvm-project/issues/88832
Fixes https://github.com/llvm/llvm-project/issues/63243
Fixes https://github.com/llvm/llvm-project/issues/48673
---
 clang/docs/ReleaseNotes.rst   |  1 +
 clang/include/clang/AST/ASTContext.h  |  3 +-
 clang/include/clang/AST/BuiltinTypes.def  |  3 +
 .../include/clang/Serialization/ASTBitCodes.h |  5 +-
 clang/lib/AST/ASTContext.cpp  |  3 +
 clang/lib/AST/NSAPI.cpp   |  1 +
 clang/lib/AST/Type.cpp|  3 +
 clang/lib/AST/TypeLoc.cpp |  1 +
 clang/lib/Sema/SemaExpr.cpp   | 19 +
 clang/lib/Sema/SemaTemplate.cpp   | 13 +++-
 clang/lib/Serialization/ASTCommon.cpp |  3 +
 clang/lib/Serialization/ASTReader.cpp |  3 +
 clang/test/SemaCXX/PR62533.cpp|  2 +-
 clang/test/SemaTemplate/template-id-expr.cpp  | 71 +++
 14 files changed, 125 insertions(+), 6 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index efc32212f300cf..8c50988083faa6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -535,6 +535,7 @@ Bug Fixes to C++ Support
 - Fix a crash when deducing ``auto`` from an invalid dereference (#GH88329).
 - Fix a crash in requires expression with templated base class member 
function. Fixes (#GH84020).
 - Placement new initializes typedef array with correct size (#GH41441)
+- Fixed a misuse of ``UnresolvedLookupExpr`` for ill-formed templated 
expressions. Fixes (#GH48673), (#GH63243) and (#GH88832).
 
 Bug Fixes to AST Handling
 ^
diff --git a/clang/include/clang/AST/ASTContext.h 
b/clang/include/clang/AST/ASTContext.h
index 28f8d67811f0a2..e9a22f04cfe764 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -1116,7 +1116,8 @@ class ASTContext : public RefCountedBase {
   CanQualType BFloat16Ty;
   CanQualType Float16Ty; // C11 extension ISO/IEC TS 18661-3
   CanQualType VoidPtrTy, NullPtrTy;
-  CanQualType DependentTy, OverloadTy, BoundMemberTy, UnknownAnyTy;
+  CanQualType DependentTy, OverloadTy, BoundMemberTy, UnresolvedTemplateTy,
+  UnknownAnyTy;
   CanQualType BuiltinFnTy;
   CanQualType PseudoObjectTy, ARCUnbridgedCastTy;
   CanQualType ObjCBuiltinIdTy, ObjCBuiltinClassTy, ObjCBuiltinSelTy;
diff --git a/clang/include/clang/AST/BuiltinTypes.def 
b/clang/include/clang/AST/BuiltinTypes.def
index c04f6f6f127191..fd0cc10be8ebca 100644
--- a/clang/include/clang/AST/BuiltinTypes.def
+++ b/clang/include/clang/AST/BuiltinTypes.def
@@ -285,6 +285,9 @@ PLACEHOLDER_TYPE(Overload, OverloadTy)
 //   x->foo   # if only contains non-static members
 PLACEHOLDER_TYPE(BoundMember, BoundMemberTy)
 
+// The type of an unresolved template. Used in UnresolvedLookupExpr.
+PLACEHOLDER_TYPE(UnresolvedTemplate, UnresolvedTemplateTy)
+
 // The type of an expression which refers to a pseudo-object,
 // such as those introduced by Objective C's @property or
 // VS.NET's __property declarations.  A placeholder type.  The
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h 
b/clang/include/

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland created 
https://github.com/llvm/llvm-project/pull/102022

This is an OOO core that has a vector unit. For more information see 
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate vector 
scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.

>From 987b46c76297486e2c4c5a67f5c67225b2bbd361 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 5 Aug 2024 10:01:08 -0700
Subject: [PATCH] [RISCV] Add sifive-p470 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate vector
scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.
---
 clang/test/Driver/riscv-cpus.c| 10 +
 clang/test/Misc/target-invalid-cpu-note.c |  5 ++-
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  1 -
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 52 ---
 5 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a885cde76d6a..fc87710e0da06 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -304,6 +304,16 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck 
-check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" 
"+za64rs" "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
 // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b87bced18cb2b..249bea2311549 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,5 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/102022

>From 987b46c76297486e2c4c5a67f5c67225b2bbd361 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 5 Aug 2024 10:01:08 -0700
Subject: [PATCH 1/2] [RISCV] Add sifive-p470 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate vector
scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.
---
 clang/test/Driver/riscv-cpus.c| 10 +
 clang/test/Misc/target-invalid-cpu-note.c |  5 ++-
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  1 -
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 52 ---
 5 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a885cde76d6a..fc87710e0da06 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -304,6 +304,16 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck 
-check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" 
"+za64rs" "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
 // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b87bced18cb2b..249bea2311549 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,5 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, 
sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, s

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/102022

>From 987b46c76297486e2c4c5a67f5c67225b2bbd361 Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Mon, 5 Aug 2024 10:01:08 -0700
Subject: [PATCH 1/3] [RISCV] Add sifive-p470 processor

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate vector
scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.
---
 clang/test/Driver/riscv-cpus.c| 10 +
 clang/test/Misc/target-invalid-cpu-note.c |  5 ++-
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  1 -
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 52 ---
 5 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a885cde76d6a..fc87710e0da06 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -304,6 +304,16 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck 
-check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" "-target-feature" "+v" 
"-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" 
"+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" 
"-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" 
"+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 
"-target-feature" "+zihintntl" "-target-feature" "+zihintpause" 
"-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" 
"+za64rs" "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbs"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" "-target-feature" 
"+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" 
"-target-feature" "+zve64x"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" 
"-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" 
"+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" 
"-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" 
"+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck 
-check-prefix=MCPU-SIFIVE-P670 %s
 // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b87bced18cb2b..249bea2311549 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,5 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, 
rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, 
sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, s

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Michael Maitland via cfe-commits]

@@ -266,11 +272,47 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", 
SiFiveP400Model,
FeatureStdExtZfhmin,
FeatureUnalignedScalarMem,
FeatureUnalignedVectorMem],
-  [TuneNoDefaultUnroll,
-   TuneConditionalCompressedMoveFusion,
-   TuneLUIADDIFusion,
-   TuneAUIPCADDIFusion,
-   FeaturePostRAScheduler]>;
+  SiFiveP400TuneFeatures>;
+
+def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,

michaelmaitland wrote:

I've updated it to use a profile list, without the supervisor extensions.

https://github.com/llvm/llvm-project/pull/102022
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[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland closed 
https://github.com/llvm/llvm-project/pull/102022
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[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

There was a prior discussion about what designs should go in. The initial quote 
from @asb was:

> it's obvious that commercial designs with active support should go in, and 
> that some core design I hacked up over a weekend shouldn't but we haven't had 
> the need to discuss anything in-between that

@preames suggested:

> we might want to think about deprecation policy so that we can be fairly 
> liberal in accepting support for new CPUs/microarchs, yet remove them later 
> if they become less relevant

My main concern here is that we'd like to ensure that there is a maintainer for 
this. Could you provide us some more information on what entity would be the 
maintainer? It looks like @Wren6991 is the only maintainer of Hazard3.

I'm also interested in understanding whether there are any customers or users 
of this core.

I think it would be helpful to raise this at the next LLVM RISC-V syncup.

https://github.com/llvm/llvm-project/pull/102452
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[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

Is this PR stacked on b125071eeb35ee4a76e126967b7c29d86a1fae56?

https://github.com/llvm/llvm-project/pull/102452
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[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/102452
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[clang] [llvm] [RISCV] Bump Pointer Masking extension version (PR #96715)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/96715

>From f6a4cf6b13442deac91c9ee49b7ba97617508c9d Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 25 Jun 2024 16:35:25 -0700
Subject: [PATCH 1/3] [RISCV] Bump Pointer Masking extension version

---
 llvm/docs/RISCVUsage.rst  |  2 +-
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td| 10 ++---
 llvm/test/CodeGen/RISCV/attributes.ll | 22 +-
 llvm/test/MC/RISCV/attribute-arch.s   | 40 +--
 .../TargetParser/RISCVISAInfoTest.cpp | 10 ++---
 6 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 152849a01c37f..61ded53c489f8 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -263,7 +263,7 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose one, attending the bi-weekly RISC-V sync-up call is 
strongly advised.
 
 ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, 
``experimental-sspm``, ``experimental-supm``
-  LLVM implements the `v0.8.1 draft specification 
`__.
+  LLVM implements the `v1.0.0-rc2 specification 
`__.
 
 ``experimental-ssqosid``
   LLVM implements assembler support for the `v1.0-rc1 draft specification 
`_.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 76356dd76f1d2..4392cd4b8907b 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -184,6 +184,7 @@ Changes to the RISC-V Backend
 * B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 * Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
 * ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
+* Ssnpm, Smnpm, Smmpm, Sspm, and Supm are bumped to version 1.0.0
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a5e34def81c85..1b1170347d1da 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -961,32 +961,32 @@ def FeatureStdExtSvpbmt
 // privilege mode (U-mode), and for VS- and VU-modes if the H extension is
 // present.
 def FeatureStdExtSsnpm
-: RISCVExperimentalExtension<"ssnpm", 0, 8,
+: RISCVExperimentalExtension<"ssnpm", 1, 0,
  "'Ssnpm' (Supervisor-level Pointer Masking 
for next lower privilege mode)">;
 
 // A machine-level extension that provides pointer masking for the next lower
 // privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
 def FeatureStdExtSmnpm
-: RISCVExperimentalExtension<"smnpm", 0, 8,
+: RISCVExperimentalExtension<"smnpm", 1, 0,
  "'Smnpm' (Machine-level Pointer Masking for 
next lower privilege mode)">;
 
 // A machine-level extension that provides pointer masking for M-mode.
 def FeatureStdExtSmmpm
-: RISCVExperimentalExtension<"smmpm", 0, 8,
+: RISCVExperimentalExtension<"smmpm", 1, 0,
  "'Smmpm' (Machine-level Pointer Masking for 
M-mode)">;
 
 // An extension that indicates that there is pointer-masking support available
 // in supervisor mode, with some facility provided in the supervisor execution
 // environment to control pointer masking.
 def FeatureStdExtSspm
-: RISCVExperimentalExtension<"sspm", 0, 8,
+: RISCVExperimentalExtension<"sspm", 1, 0,
  "'Sspm' (Indicates Supervisor-mode Pointer 
Masking)">;
 
 // An extension that indicates that there is pointer-masking support available
 // in user mode, with some facility provided in the application execution
 // environment to control pointer masking.
 def FeatureStdExtSupm
-: RISCVExperimentalExtension<"supm", 0, 8,
+: RISCVExperimentalExtension<"supm", 1, 0,
  "'Supm' (Indicates User-mode Pointer 
Masking)">;
 
 
//===--===//
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index f20f6f7c6f94e..135baad04bbbd 100644
--- a/llvm/test/CodeGen/R

[clang] [llvm] [RISCV] Bump Pointer Masking extension version (PR #96715)

[Michael Maitland via cfe-commits]

https://github.com/michaelmaitland updated 
https://github.com/llvm/llvm-project/pull/96715

>From f6a4cf6b13442deac91c9ee49b7ba97617508c9d Mon Sep 17 00:00:00 2001
From: Michael Maitland 
Date: Tue, 25 Jun 2024 16:35:25 -0700
Subject: [PATCH 1/4] [RISCV] Bump Pointer Masking extension version

---
 llvm/docs/RISCVUsage.rst  |  2 +-
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td| 10 ++---
 llvm/test/CodeGen/RISCV/attributes.ll | 22 +-
 llvm/test/MC/RISCV/attribute-arch.s   | 40 +--
 .../TargetParser/RISCVISAInfoTest.cpp | 10 ++---
 6 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 152849a01c37f..61ded53c489f8 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -263,7 +263,7 @@ LLVM supports (to various degrees) a number of experimental 
extensions.  All exp
 The primary goal of experimental support is to assist in the process of 
ratification by providing an existence proof of an implementation, and 
simplifying efforts to validate the value of a proposed extension against large 
code bases.  Experimental extensions are expected to either transition to 
ratified status, or be eventually removed.  The decision on whether to accept 
an experimental extension is currently done on an entirely case by case basis; 
if you want to propose one, attending the bi-weekly RISC-V sync-up call is 
strongly advised.
 
 ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, 
``experimental-sspm``, ``experimental-supm``
-  LLVM implements the `v0.8.1 draft specification 
`__.
+  LLVM implements the `v1.0.0-rc2 specification 
`__.
 
 ``experimental-ssqosid``
   LLVM implements assembler support for the `v1.0-rc1 draft specification 
`_.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 76356dd76f1d2..4392cd4b8907b 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -184,6 +184,7 @@ Changes to the RISC-V Backend
 * B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 * Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
 * ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
+* Ssnpm, Smnpm, Smmpm, Sspm, and Supm are bumped to version 1.0.0
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a5e34def81c85..1b1170347d1da 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -961,32 +961,32 @@ def FeatureStdExtSvpbmt
 // privilege mode (U-mode), and for VS- and VU-modes if the H extension is
 // present.
 def FeatureStdExtSsnpm
-: RISCVExperimentalExtension<"ssnpm", 0, 8,
+: RISCVExperimentalExtension<"ssnpm", 1, 0,
  "'Ssnpm' (Supervisor-level Pointer Masking 
for next lower privilege mode)">;
 
 // A machine-level extension that provides pointer masking for the next lower
 // privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
 def FeatureStdExtSmnpm
-: RISCVExperimentalExtension<"smnpm", 0, 8,
+: RISCVExperimentalExtension<"smnpm", 1, 0,
  "'Smnpm' (Machine-level Pointer Masking for 
next lower privilege mode)">;
 
 // A machine-level extension that provides pointer masking for M-mode.
 def FeatureStdExtSmmpm
-: RISCVExperimentalExtension<"smmpm", 0, 8,
+: RISCVExperimentalExtension<"smmpm", 1, 0,
  "'Smmpm' (Machine-level Pointer Masking for 
M-mode)">;
 
 // An extension that indicates that there is pointer-masking support available
 // in supervisor mode, with some facility provided in the supervisor execution
 // environment to control pointer masking.
 def FeatureStdExtSspm
-: RISCVExperimentalExtension<"sspm", 0, 8,
+: RISCVExperimentalExtension<"sspm", 1, 0,
  "'Sspm' (Indicates Supervisor-mode Pointer 
Masking)">;
 
 // An extension that indicates that there is pointer-masking support available
 // in user mode, with some facility provided in the application execution
 // environment to control pointer masking.
 def FeatureStdExtSupm
-: RISCVExperimentalExtension<"supm", 0, 8,
+: RISCVExperimentalExtension<"supm", 1, 0,
  "'Supm' (Indicates User-mode Pointer 
Masking)">;
 
 
//===--===//
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index f20f6f7c6f94e..135baad04bbbd 100644
--- a/llvm/test/CodeGen/R