https://github.com/michaelmaitland updated
https://github.com/llvm/llvm-project/pull/98207
>From a43b26a423e45b96fa105a9bbca7fbc3495e8ef8 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitl...@gmail.com>
Date: Tue, 9 Jul 2024 10:44:05 -0700
Subject: [PATCH 1/2] [RISCV] Add ability to list extensions enabled for a
target
bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option.
---
clang/include/clang/Driver/Options.td | 2 +-
clang/lib/Driver/Driver.cpp | 1 +
clang/tools/driver/cc1_main.cpp | 12 ++++--
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 6 ++-
llvm/lib/TargetParser/RISCVISAInfo.cpp | 42 ++++++++++++++++++-
.../TargetParser/RISCVISAInfoTest.cpp | 30 ++++++++++++-
6 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index be7c3b60c20f1..90c5e12813884 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5724,7 +5724,7 @@ def print_supported_extensions : Flag<["-", "--"],
"print-supported-extensions">
def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
Visibility<[ClangOption, CC1Option, CLOption]>,
HelpText<"Print the extensions enabled by the given target and -march/-mcpu
options."
- " (AArch64 only)">,
+ " (AArch64 and RISC-V only)">,
MarshallingInfoFlag<FrontendOpts<"PrintEnabledExtensions">>;
def : Flag<["-"], "mcpu=help">, Alias<print_supported_cpus>;
def : Flag<["-"], "mtune=help">, Alias<print_supported_cpus>;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 021c5b8a33dba..28c3b52483e51 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -4367,6 +4367,7 @@ void Driver::BuildActions(Compilation &C, DerivedArgList
&Args,
return;
}
if (Opt == options::OPT_print_enabled_extensions &&
+ !C.getDefaultToolChain().getTriple().isRISCV() &&
!C.getDefaultToolChain().getTriple().isAArch64()) {
C.getDriver().Diag(diag::err_opt_not_valid_on_target)
<< "--print-enabled-extensions";
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c0599c2e5149..441093dbf9f39 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
DescMap.insert({feature.Key, feature.Desc});
if (MachineTriple.isRISCV())
- llvm::riscvExtensionsHelp(DescMap);
+ llvm::printSupportedExtensions(DescMap);
else if (MachineTriple.isAArch64())
llvm::AArch64::PrintSupportedExtensions();
else if (MachineTriple.isARM())
@@ -190,13 +190,19 @@ static int PrintEnabledExtensions(const TargetOptions&
TargetOpts) {
for (const llvm::SubtargetFeatureKV &feature : Features)
EnabledFeatureNames.insert(feature.Key);
- if (!MachineTriple.isAArch64()) {
+ if (MachineTriple.isAArch64())
+ llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+ else if (MachineTriple.isRISCV()) {
+ llvm::StringMap<llvm::StringRef> DescMap;
+ for (const llvm::SubtargetFeatureKV &feature : Features)
+ DescMap.insert({feature.Key, feature.Desc});
+ llvm::printEnabledExtensions(MachineTriple.isArch64Bit(),
EnabledFeatureNames, DescMap);
+ } else {
// The option was already checked in Driver::HandleImmediateArgs,
// so we do not expect to get here if we are not a supported architecture.
assert(0 && "Unhandled triple for --print-enabled-extensions option.");
return 1;
}
- llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
return 0;
}
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index ba2965600decd..418c9337c144f 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -15,11 +15,15 @@
#include "llvm/Support/RISCVISAUtils.h"
#include <map>
+#include <set>
#include <string>
#include <vector>
namespace llvm {
-void riscvExtensionsHelp(StringMap<StringRef> DescMap);
+void printSupportedExtensions(StringMap<StringRef> &DescMap);
+void printEnabledExtensions(bool IsRV64,
+ std::set<StringRef> &EnabledFeatureNames,
+ StringMap<StringRef> &DescMap);
class RISCVISAInfo {
public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1d077326e4cf2..4ed0df0104e3c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,8 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
<< Description << "\n";
}
-void llvm::riscvExtensionsHelp(StringMap<StringRef> DescMap) {
-
+void llvm::printSupportedExtensions(StringMap<StringRef> &DescMap) {
outs() << "All available -march extensions for RISC-V\n\n";
PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
@@ -116,6 +115,45 @@ void llvm::riscvExtensionsHelp(StringMap<StringRef>
DescMap) {
"For example, clang -march=rv32i_v1p0\n";
}
+void llvm::printEnabledExtensions(bool IsRV64,
+ std::set<StringRef> &EnabledFeatureNames,
+ StringMap<StringRef> &DescMap) {
+ outs() << "Extensions enabled for the given RISC-V target\n\n";
+ PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
+
+ RISCVISAUtils::OrderedExtensionMap FullExtMap;
+ RISCVISAUtils::OrderedExtensionMap ExtMap;
+ for (const auto &E : SupportedExtensions)
+ if (EnabledFeatureNames.find(E.Name) != EnabledFeatureNames.end()) {
+ FullExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+ ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+ }
+ for (const auto &E : ExtMap) {
+ std::string Version =
+ std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor);
+ PrintExtension(E.first, Version, DescMap[E.first]);
+ }
+
+ outs() << "\nExperimental extensions\n";
+ ExtMap.clear();
+ for (const auto &E : SupportedExperimentalExtensions) {
+ StringRef Name(E.Name);
+ if (EnabledFeatureNames.find("experimental-" + Name.str()) !=
+ EnabledFeatureNames.end()) {
+ FullExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+ ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+ }
+ }
+ for (const auto &E : ExtMap) {
+ std::string Version =
+ std::to_string(E.second.Major) + "." + std::to_string(E.second.Minor);
+ PrintExtension(E.first, Version, DescMap["experimental-" + E.first]);
+ }
+
+ unsigned XLen = IsRV64 ? 64 : 32;
+ outs() << "\nISA String: " << RISCVISAInfo(XLen, FullExtMap).toString();
+}
+
static bool stripExperimentalPrefix(StringRef &Ext) {
return Ext.consume_front("experimental-");
}
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 7b45d0715a52a..98149002e7cab 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1061,7 +1061,7 @@ For example, clang -march=rv32i_v1p0)";
outs().flush();
testing::internal::CaptureStdout();
- riscvExtensionsHelp(DummyMap);
+ printSupportedExtensions(DummyMap);
outs().flush();
std::string CapturedOutput = testing::internal::GetCapturedStdout();
@@ -1069,3 +1069,31 @@ For example, clang -march=rv32i_v1p0)";
return Captured.find(Expected) != std::string::npos;
}(CapturedOutput, ExpectedOutput));
}
+
+TEST(TargetParserTest, RISCVPrintEnabledExtensions) {
+ // clang-format off
+ std::string ExpectedOutput =
+R"(Extensions enabled for the given RISC-V target
+
+ Name Version Description
+ i 2.1 'I' (Base Integer Instruction Set)
+
+Experimental extensions
+ ztso 0.1 'Ztso' (Memory Model - Total Store Order)
+
+ISA String: rv64i2p1_ztso0p1)";
+ // clang-format on
+
+ StringMap<StringRef> DescMap;
+ DescMap["i"] = "'I' (Base Integer Instruction Set)";
+ DescMap["experimental-ztso"] = "'Ztso' (Memory Model - Total Store Order)";
+ std::set<StringRef> EnabledExtensions = {"i", "experimental-ztso"};
+
+ outs().flush();
+ testing::internal::CaptureStdout();
+ llvm::printEnabledExtensions(/*IsRV64=*/true, EnabledExtensions, DescMap);
+ outs().flush();
+ std::string CapturedOutput = testing::internal::GetCapturedStdout();
+
+ EXPECT_EQ(CapturedOutput, ExpectedOutput);
+}
>From ea5501ba4cb54e167e3b994e49ff68f46333d84f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitl...@gmail.com>
Date: Tue, 9 Jul 2024 12:53:43 -0700
Subject: [PATCH 2/2] fixup! format and use RISCV namespace
---
clang/tools/driver/cc1_main.cpp | 5 +++--
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 2 ++
llvm/lib/TargetParser/RISCVISAInfo.cpp | 4 ++--
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 441093dbf9f39..819f20d2d6fa2 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -147,7 +147,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
DescMap.insert({feature.Key, feature.Desc});
if (MachineTriple.isRISCV())
- llvm::printSupportedExtensions(DescMap);
+ llvm::RISCV::printSupportedExtensions(DescMap);
else if (MachineTriple.isAArch64())
llvm::AArch64::PrintSupportedExtensions();
else if (MachineTriple.isARM())
@@ -196,7 +196,8 @@ static int PrintEnabledExtensions(const TargetOptions&
TargetOpts) {
llvm::StringMap<llvm::StringRef> DescMap;
for (const llvm::SubtargetFeatureKV &feature : Features)
DescMap.insert({feature.Key, feature.Desc});
- llvm::printEnabledExtensions(MachineTriple.isArch64Bit(),
EnabledFeatureNames, DescMap);
+ llvm::RISCV::printEnabledExtensions(MachineTriple.isArch64Bit(),
+ EnabledFeatureNames, DescMap);
} else {
// The option was already checked in Driver::HandleImmediateArgs,
// so we do not expect to get here if we are not a supported architecture.
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
index 418c9337c144f..7e10eef24bd30 100644
--- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h
+++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h
@@ -20,10 +20,12 @@
#include <vector>
namespace llvm {
+namespace RISCV {
void printSupportedExtensions(StringMap<StringRef> &DescMap);
void printEnabledExtensions(bool IsRV64,
std::set<StringRef> &EnabledFeatureNames,
StringMap<StringRef> &DescMap);
+} // end namespace RISCV
class RISCVISAInfo {
public:
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 4ed0df0104e3c..633cb04bf6c9e 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -80,7 +80,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
<< Description << "\n";
}
-void llvm::printSupportedExtensions(StringMap<StringRef> &DescMap) {
+void llvm::RISCV::printSupportedExtensions(StringMap<StringRef> &DescMap) {
outs() << "All available -march extensions for RISC-V\n\n";
PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description"));
@@ -115,7 +115,7 @@ void llvm::printSupportedExtensions(StringMap<StringRef>
&DescMap) {
"For example, clang -march=rv32i_v1p0\n";
}
-void llvm::printEnabledExtensions(bool IsRV64,
+void llvm::RISCV::printEnabledExtensions(bool IsRV64,
std::set<StringRef> &EnabledFeatureNames,
StringMap<StringRef> &DescMap) {
outs() << "Extensions enabled for the given RISC-V target\n\n";
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