Author: Michael Maitland Date: 2023-05-05T09:03:06-07:00 New Revision: 6e7ca6839def260e57334040a586934011f0098d
URL: https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d DIFF: https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d.diff LOG: Revert "[RISCV] Add sifive-x280 processor with all of its extensions" Test still not working... This reverts commit a11dfd0fe6b1c38495f7de9858a2d1839d2902b9. Added: Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note.c llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index a484b07ce330a..76325311668d8 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -167,20 +167,6 @@ // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" -// mcpu with default march include experimental extensions -// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s -// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" -// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" -// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" - // Check failed cases // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index ba43ba50accd9..1f205163a966e 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}, sifive-x280 +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 845cee9e75455..c764a50f88b22 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -175,7 +175,6 @@ Changes to the RISC-V Backend ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and ``checkTuneCPUKind``. -* Add sifive-x280 processor. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 69edacc4058c1..67b0364aa2fd7 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -166,22 +166,6 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", FeatureStdExtC], [TuneSiFive7]>; -def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, - [Feature64Bit, - FeatureStdExtZifencei, - FeatureStdExtM, - FeatureStdExtA, - FeatureStdExtF, - FeatureStdExtD, - FeatureStdExtC, - FeatureStdExtV, - FeatureStdExtZvl512b, - FeatureStdExtZfh, - FeatureStdExtZvfh, - FeatureStdExtZba, - FeatureStdExtZbb], - [TuneSiFive7]>; - def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, [Feature32Bit, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
