================ @@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0; defvar SiFiveP400F2I = SiFiveP400FEXQ0; def SiFiveP400FloatDiv : ProcResource<1>; +// Vector pipeline +def SiFiveP400VEXQ0 : ProcResource<1>; ---------------- michaelmaitland wrote:
There is an issue queue in front of the vector ALU (purple). Vector loads go through the load/store dispatch buffer (green). Vector divisions are non blocking to other vector ALU operations. We think it is okay to model VLD/VST/VDiv/VFloatDiv as standalone resources. https://github.com/llvm/llvm-project/pull/102155 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
