https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/102022
>From 987b46c76297486e2c4c5a67f5c67225b2bbd361 Mon Sep 17 00:00:00 2001 From: Michael Maitland <michaeltmaitl...@gmail.com> Date: Mon, 5 Aug 2024 10:01:08 -0700 Subject: [PATCH 1/2] [RISCV] Add sifive-p470 processor This is an OOO core that has a vector unit. For more information see https://www.sifive.com/cores/performance-p450-470. Use the existing P400 scheduler model. This model is missing accurate vector scheduling support, but it will be added in a follow up patch. Other tunings can come in future patches too. --- clang/test/Driver/riscv-cpus.c | 10 +++++ clang/test/Misc/target-invalid-cpu-note.c | 5 ++- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 1 - llvm/lib/Target/RISCV/RISCVProcessors.td | 52 ++++++++++++++++++++--- 5 files changed, 61 insertions(+), 8 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 7a885cde76d6a..fc87710e0da06 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -304,6 +304,16 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s +// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" "+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" "+za64rs" "-target-feature" "+zfhmin" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" "-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" "+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" "-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" "+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt" +// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d" + // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670" // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index b87bced18cb2b..249bea2311549 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' @@ -93,4 +93,5 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}} + diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index a95cb53694e2b..1ed860de6b9dc 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -107,6 +107,7 @@ Changes to the RISC-V Backend the required alignment space with a sequence of `0x0` bytes (the requested fill value) rather than NOPs. * Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64`` +* ``-mcpu=sifive-p470`` was added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e278fa3fe3176..5c5e03e7782a5 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1371,7 +1371,6 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion() def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; - def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", "Ventana Veyron-Series processors">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 83d27b35cf0da..a118e1fe5e502 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -239,6 +239,12 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, FeatureStdExtZbb], SiFiveX280TuneFeatures>; +defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + FeaturePostRAScheduler]; + def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, [Feature64Bit, FeatureStdExtI, @@ -266,11 +272,47 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, FeatureStdExtZfhmin, FeatureUnalignedScalarMem, FeatureUnalignedVectorMem], - [TuneNoDefaultUnroll, - TuneConditionalCompressedMoveFusion, - TuneLUIADDIFusion, - TuneAUIPCADDIFusion, - FeaturePostRAScheduler]>; + SiFiveP400TuneFeatures>; + +def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureVendorXSiFivecdiscarddlone, + FeatureVendorXSiFivecflushdlone, + FeatureStdExtZa64rs, + FeatureStdExtZic64b, + FeatureStdExtZicbop, + FeatureStdExtZicbom, + FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZicclsm, + FeatureStdExtZiccrse, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZfhmin, + FeatureStdExtV, + FeatureStdExtZvl128b, + FeatureStdExtZvbb, + FeatureStdExtZvknc, + FeatureStdExtZvkng, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem], + !listconcat(SiFiveP400TuneFeatures, + [TuneNoSinkSplatOperands])>; + def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, [Feature64Bit, >From 64ac7df8c1eb0f45edb60ce3c7c9d29befc27fb7 Mon Sep 17 00:00:00 2001 From: Michael Maitland <michaeltmaitl...@gmail.com> Date: Tue, 6 Aug 2024 07:10:10 -0700 Subject: [PATCH 2/2] fixup! respond to comments --- clang/test/Driver/riscv-cpus.c | 50 ++++++++++++++++++++++---- llvm/lib/Target/RISCV/RISCVFeatures.td | 1 + 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index fc87710e0da06..750fb637edeb1 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -306,12 +306,50 @@ // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s // MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zic64b" "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz" "-target-feature" "+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm" "-target-feature" "+ziccrse" "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintntl" "-target-feature" "+zihintpause" "-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" "+za64rs" "-target-feature" "+zfhmin" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbs" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" "-target-feature" "+zvbc" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x" -// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" "-target-feature" "+zvkn" "-target-feature" "+zvknc" "-target-feature" "+zvkned" "-target-feature" "+zvkng" "-target-feature" "+zvknhb" "-target-feature" "+zvks" "-target-feature" "+zvksc" "-target-feature" "+zvksed" "-target-feature" "+zvksg" "-target-feature" "+zvksh" "-target-feature" "+zvkt" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+a" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+f" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+d" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+v" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh" +// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d" // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 5c5e03e7782a5..e278fa3fe3176 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1371,6 +1371,7 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion() def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; + def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", "Ventana Veyron-Series processors">; _______________________________________________ cfe-commits mailing list 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