Hi Pavel, On 8/29/2024 6:24 AM, Pavel Pisa wrote: > Generally, I agree that index should wrap up for cyclic FIFO > implementation and change looks logical to me but I do not > see and studied all consequences related to emulated HW. > > If that is confirmed or corrected by somebody from AMD/XilinX, > it would be better. I can find more time to do deeper analysis > if no other looks into the whole code.
Thank you for your reviews! I agree. I don't know how the hardware is actually implemented internally so it would be great if someone from AMD could confirm that this change 100% matches the hardware. Unfortunately Versal dev boards are very expensive so I can't test hardware myself. What I can say is that before I implemented the index calculation fixes in this patch, the Linux driver in the Xilinx kernel was seeing incorrect messages. Now it works fine even with heavy bus load. Doug
