On Tue, 27 Aug 2024 at 04:51, Doug Brown <d...@schmorgal.com> wrote: > > This series fixes several problems I ran into while trying to simulate > the AMD/Xilinx Versal CANFD controller in the xlnx-versal-virt machine > using Xilinx's v6.6_LTS_2024.1 kernel. With all of these patches > applied, everything works correctly alongside actual CAN devices. > > - IRQs were accidentally not being delivered due to having a level other > than 1. The IRQ count in /proc/interrupts in Linux was stuck at 0. > - Incoming CAN FD frames were being treated as non-FD. > - The CAN IDs were garbled in both RX and TX directions. > - The ESI and BRS flags were not being handled. > - The byte ordering was wrong in the data in both directions. > - Incoming CAN FD frames with DLC = 1-7 weren't handled correctly. > - The FIFO read_index and store_index wrapping logic was incorrect. > > I don't have any actual Versal hardware to compare behavior against, but > with these changes, it plays nicely with SocketCAN on the host system. > > Changes in v2: > - Added handling of ESI and BRS flags, ensured frame->flags is initialized > - Switched to use common can_dlc2len() and can_len2dlc() functions > - Added fix for FIFO wrapping problems I observed during stress testing
I've applied this series to target-arm.next; thanks! -- PMM
