The interrupt level should be 0 or 1. The existing code was using the
interrupt flags to determine the level. In the only machine currently
supported (xlnx-versal-virt), the GICv3 was masking off all bits except
bit 0 when applying it, resulting in the IRQ never being delivered.
Signed-off-by: Doug Brown <d...@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
---
hw/net/can/xlnx-versal-canfd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
index 5f083c21e9..ad0c4da3c8 100644
--- a/hw/net/can/xlnx-versal-canfd.c
+++ b/hw/net/can/xlnx-versal-canfd.c
@@ -682,8 +682,8 @@ static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32,
48, 64};
static void canfd_update_irq(XlnxVersalCANFDState *s)
{
- unsigned int irq = s->regs[R_INTERRUPT_STATUS_REGISTER] &
- s->regs[R_INTERRUPT_ENABLE_REGISTER];
+ const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] &
+ s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0;
g_autofree char *path = object_get_canonical_path(OBJECT(s));
/* RX watermark interrupts. */
--
2.34.1
