On Mon, Apr 30, 2012 at 5:19 AM, Olivier Galibert <galib...@pobox.com> wrote:
> TGSI doesn't need an opcode, since registers are untyped (but beware
> once doubles come into the scene). Mesa needs two because registers
> are typed float. They're not going to work anyway, given that a float
> does not have enough mantissa bits to store a full 32bits integer.
>
> Of course, in the end, it was only tested with softpipe, since the
> other two software renderers don't support glsl 1.3 yet.
>
> Signed-off-by: Olivier Galibert <galib...@pobox.com>
> ---
> src/mesa/program/ir_to_mesa.cpp | 8 ++++++++
> src/mesa/program/prog_execute.c | 18 ++++++++++++++++++
> src/mesa/program/prog_instruction.c | 2 ++
> src/mesa/program/prog_instruction.h | 2 ++
> src/mesa/program/prog_optimize.c | 4 ++++
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 ++++++
> 6 files changed, 40 insertions(+)
>
> diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
> index 840648e..14ece29 100644
> --- a/src/mesa/program/ir_to_mesa.cpp
> +++ b/src/mesa/program/ir_to_mesa.cpp
> @@ -1407,6 +1407,14 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
> emit(ir, OPCODE_SNE, result_dst,
> op[0], src_reg_for_float(0.0));
> break;
> + case ir_unop_bf2i:
> + case ir_unop_bf2u:
> + emit(ir, OPCODE_BF2U, result_dst, op[0]);
> + break;
> + case ir_unop_bi2f:
> + case ir_unop_bu2f:
> + emit(ir, OPCODE_BU2F, result_dst, op[0]);
> + break;
> case ir_unop_trunc:
> emit(ir, OPCODE_TRUNC, result_dst, op[0]);
> break;
> diff --git a/src/mesa/program/prog_execute.c b/src/mesa/program/prog_execute.c
> index 848c2fe..a58f58f 100644
> --- a/src/mesa/program/prog_execute.c
> +++ b/src/mesa/program/prog_execute.c
> @@ -713,6 +713,24 @@ _mesa_execute_program(struct gl_context * ctx,
> }
> }
> break;
> + case OPCODE_BF2U:
> + {
> + GLfloat a[4];
> + GLuint result[4];
> + fetch_vector4(&inst->SrcReg[0], machine, a);
> + memcpy(result, a, 4*4);
Maybe 4*sizeof(GLfloat) or sizeof(GLuint) just to be clear (same below).
> + store_vector4ui(inst, machine, result);
> + }
> + break;
> + case OPCODE_BU2F:
> + {
> + GLuint a[4];
> + GLfloat result[4];
> + fetch_vector4ui(&inst->SrcReg[0], machine, a);
> + memcpy(result, a, 4*4);
> + store_vector4(inst, machine, result);
> + }
> + break;
> case OPCODE_BGNLOOP:
> /* no-op */
> ASSERT(program->Instructions[inst->BranchTarget].Opcode
> diff --git a/src/mesa/program/prog_instruction.c
> b/src/mesa/program/prog_instruction.c
> index 5d6cb47..91bcf3f 100644
> --- a/src/mesa/program/prog_instruction.c
> +++ b/src/mesa/program/prog_instruction.c
> @@ -160,6 +160,8 @@ static const struct instruction_info InstInfo[MAX_OPCODE]
> = {
> { OPCODE_ARL, "ARL", 1, 1 },
> { OPCODE_ARL_NV, "ARL_NV", 1, 1 },
> { OPCODE_ARR, "ARL", 1, 1 },
> + { OPCODE_BF2U, "BF2U", 1, 1 },
> + { OPCODE_BU2F, "BU2F", 1, 1 },
> { OPCODE_BGNLOOP,"BGNLOOP", 0, 0 },
> { OPCODE_BGNSUB, "BGNSUB", 0, 0 },
> { OPCODE_BRA, "BRA", 0, 0 },
> diff --git a/src/mesa/program/prog_instruction.h
> b/src/mesa/program/prog_instruction.h
> index 09659ce..17ac18a 100644
> --- a/src/mesa/program/prog_instruction.h
> +++ b/src/mesa/program/prog_instruction.h
> @@ -152,6 +152,8 @@ typedef enum prog_opcode {
> OPCODE_ARL, /* X X X */
> OPCODE_ARL_NV, /* 2 */
> OPCODE_ARR, /* 2 */
> + OPCODE_BF2U, /* X */
> + OPCODE_BU2F, /* X */
> OPCODE_BGNLOOP, /* opt */
> OPCODE_BGNSUB, /* opt */
> OPCODE_BRA, /* 2 */
> diff --git a/src/mesa/program/prog_optimize.c
> b/src/mesa/program/prog_optimize.c
> index 25d9684..bdb9b14 100644
> --- a/src/mesa/program/prog_optimize.c
> +++ b/src/mesa/program/prog_optimize.c
> @@ -71,6 +71,8 @@ get_src_arg_mask(const struct prog_instruction *inst,
> case OPCODE_MAX:
> case OPCODE_ABS:
> case OPCODE_ADD:
> + case OPCODE_BF2U:
> + case OPCODE_BU2F:
> case OPCODE_MAD:
> case OPCODE_MUL:
> case OPCODE_SUB:
> @@ -671,6 +673,8 @@ _mesa_merge_mov_into_inst(struct prog_instruction *inst,
> case OPCODE_MAX:
> case OPCODE_ABS:
> case OPCODE_ADD:
> + case OPCODE_BF2U:
> + case OPCODE_BU2F:
> case OPCODE_MAD:
> case OPCODE_MUL:
> case OPCODE_SUB:
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 9e68deb..be0cecf 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -1762,6 +1762,12 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
> else
> emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
> break;
> + case ir_unop_bf2i:
> + case ir_unop_bf2u:
> + case ir_unop_bi2f:
> + case ir_unop_bu2f:
> + result_src = op[0];
> + break;
> case ir_unop_f2b:
> emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
> break;
Reviewed-by: Brian Paul <bri...@vmware.com>
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