From: Nicolai Hähnle <nicolai.haeh...@amd.com>
This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.
It doesn't use the ac_surface computation functions yet.
---
src/amd/common/ac_surface.h | 1 +
src/amd/vulkan/radv_device.c | 22 +++---
src/amd/vulkan/radv_image.c | 54 +++++++-------
src/amd/vulkan/radv_meta_clear.c | 2 +-
src/amd/vulkan/radv_private.h | 3 +-
src/amd/vulkan/radv_radeon_winsys.h | 87 +---------------------
src/amd/vulkan/radv_wsi.c | 2 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 63 ++++++++--------
8 files changed, 81 insertions(+), 153 deletions(-)
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index db01e74..582a671 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -55,20 +55,21 @@ enum radeon_micro_mode {
RADEON_MICRO_MODE_DEPTH = 2,
RADEON_MICRO_MODE_ROTATED = 3,
};
/* the first 16 bits are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_SCANOUT (1 << 16)
#define RADEON_SURF_ZBUFFER (1 << 17)
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER |
RADEON_SURF_SBUFFER)
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
+#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
struct legacy_surf_level {
uint64_t offset;
uint64_t slice_size;
uint64_t dcc_offset;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 2c7a680..62052f7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2599,42 +2599,42 @@ void radv_DestroyBuffer(
if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
device->ws->buffer_destroy(buffer->bo);
vk_free2(&device->alloc, pAllocator, buffer);
}
static inline unsigned
si_tile_mode_index(const struct radv_image *image, unsigned level, bool
stencil)
{
if (stencil)
- return image->surface.stencil_tiling_index[level];
+ return image->surface.u.legacy.stencil_tiling_index[level];
else
- return image->surface.tiling_index[level];
+ return image->surface.u.legacy.tiling_index[level];
}
static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
{
return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth :
iview->layer_count;
}
static void
radv_initialise_color_surface(struct radv_device *device,
struct radv_color_buffer_info *cb,
struct radv_image_view *iview)
{
const struct vk_format_description *desc;
unsigned ntype, format, swap, endian;
unsigned blend_clamp = 0, blend_bypass = 0;
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
uint64_t va;
const struct radeon_surf *surf = &iview->image->surface;
- const struct radeon_surf_level *level_info =
&surf->level[iview->base_mip];
+ const struct legacy_surf_level *level_info =
&surf->u.legacy.level[iview->base_mip];
desc = vk_format_description(iview->vk_format);
memset(cb, 0, sizeof(*cb));
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += level_info->offset;
cb->cb_color_base = va >> 8;
/* CMASK variables */
@@ -2748,34 +2748,34 @@ radv_initialise_color_surface(struct radv_device
*device,
max_uncompressed_block_size = 1;
}
cb->cb_dcc_control =
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(1);
}
/* This must be set for fast clear to work without FMASK. */
if (!iview->image->fmask.size &&
device->physical_device->rad_info.chip_class == SI) {
- unsigned bankh = util_logbase2(iview->image->surface.bankh);
+ unsigned bankh =
util_logbase2(iview->image->surface.u.legacy.bankh);
cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
}
}
static void
radv_initialise_ds_surface(struct radv_device *device,
struct radv_ds_buffer_info *ds,
struct radv_image_view *iview)
{
unsigned level = iview->base_mip;
unsigned format;
uint64_t va, s_offs, z_offs;
- const struct radeon_surf_level *level_info =
&iview->image->surface.level[level];
+ const struct legacy_surf_level *level_info =
&iview->image->surface.u.legacy.level[level];
bool stencil_only = false;
memset(ds, 0, sizeof(*ds));
switch (iview->vk_format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
case VK_FORMAT_X8_D24_UNORM_PACK32:
ds->pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
ds->offset_scale = 2.0f;
break;
case VK_FORMAT_D16_UNORM:
case VK_FORMAT_D16_UNORM_S8_UINT:
@@ -2783,52 +2783,52 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->offset_scale = 4.0f;
break;
case VK_FORMAT_D32_SFLOAT:
case VK_FORMAT_D32_SFLOAT_S8_UINT:
ds->pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
ds->offset_scale = 1.0f;
break;
case VK_FORMAT_S8_UINT:
stencil_only = true;
- level_info = &iview->image->surface.stencil_level[level];
+ level_info =
&iview->image->surface.u.legacy.stencil_level[level];
break;
default:
break;
}
format = radv_translate_dbformat(iview->vk_format);
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
s_offs = z_offs = va;
- z_offs += iview->image->surface.level[level].offset;
- s_offs += iview->image->surface.stencil_level[level].offset;
+ z_offs += iview->image->surface.u.legacy.level[level].offset;
+ s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
uint32_t max_slice = radv_surface_layer_count(iview);
ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
if (iview->image->info.samples > 1)
ds->db_z_info |=
S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
else
ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
if (device->physical_device->rad_info.chip_class >= CIK) {
struct radeon_info *info = &device->physical_device->rad_info;
- unsigned tiling_index =
iview->image->surface.tiling_index[level];
- unsigned stencil_index =
iview->image->surface.stencil_tiling_index[level];
- unsigned macro_index = iview->image->surface.macro_tile_index;
+ unsigned tiling_index =
iview->image->surface.u.legacy.tiling_index[level];
+ unsigned stencil_index =
iview->image->surface.u.legacy.stencil_tiling_index[level];
+ unsigned macro_index =
iview->image->surface.u.legacy.macro_tile_index;
unsigned tile_mode = info->si_tile_mode_array[tiling_index];
unsigned stencil_tile_mode =
info->si_tile_mode_array[stencil_index];
unsigned macro_mode =
info->cik_macrotile_mode_array[macro_index];
if (stencil_only)
tile_mode = stencil_tile_mode;
ds->db_depth_info |=
S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 04ae293..c254228 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -122,23 +122,23 @@ radv_init_surface(struct radv_device *device,
#define ATI_VENDOR_ID 0x1002
static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
{
return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
}
static inline unsigned
si_tile_mode_index(const struct radv_image *image, unsigned level, bool
stencil)
{
if (stencil)
- return image->surface.stencil_tiling_index[level];
+ return image->surface.u.legacy.stencil_tiling_index[level];
else
- return image->surface.tiling_index[level];
+ return image->surface.u.legacy.tiling_index[level];
}
static unsigned radv_map_swizzle(unsigned swizzle)
{
switch (swizzle) {
case VK_SWIZZLE_Y:
return V_008F0C_SQ_SEL_Y;
case VK_SWIZZLE_Z:
return V_008F0C_SQ_SEL_Z;
case VK_SWIZZLE_W:
@@ -182,21 +182,21 @@ radv_make_buffer_descriptor(struct radv_device *device,
S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
S_008F0C_NUM_FORMAT(num_format) |
S_008F0C_DATA_FORMAT(data_format);
}
static void
si_set_mutable_tex_desc_fields(struct radv_device *device,
struct radv_image *image,
- const struct radeon_surf_level *base_level_info,
+ const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state)
{
uint64_t gpu_address = device->ws->buffer_get_va(image->bo) +
image->offset;
uint64_t va = gpu_address + base_level_info->offset;
unsigned pitch = base_level_info->nblk_x * block_width;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[3] &= C_008F1C_TILING_INDEX;
@@ -402,72 +402,72 @@ radv_query_opaque_metadata(struct radv_device *device,
si_make_texture_descriptor(device, image, true,
(VkImageViewType)image->type,
image->vk_format,
&fixedmapping, 0, image->info.levels - 1, 0,
image->info.array_size,
image->info.width, image->info.height,
image->info.depth,
desc, NULL);
- si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0],
0, 0,
+ si_set_mutable_tex_desc_fields(device, image,
&image->surface.u.legacy.level[0], 0, 0,
image->surface.blk_w, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
desc[1] &= C_008F14_BASE_ADDRESS_HI;
desc[7] = image->dcc_offset >> 8;
/* Dwords [2:9] contain the image descriptor. */
memcpy(&md->metadata[2], desc, sizeof(desc));
/* Dwords [10:..] contain the mipmap level offsets. */
for (i = 0; i <= image->info.levels - 1; i++)
- md->metadata[10+i] = image->surface.level[i].offset >> 8;
+ md->metadata[10+i] = image->surface.u.legacy.level[i].offset >>
8;
md->size_metadata = (11 + image->info.levels - 1) * 4;
}
void
radv_init_metadata(struct radv_device *device,
struct radv_image *image,
struct radeon_bo_metadata *metadata)
{
struct radeon_surf *surface = &image->surface;
memset(metadata, 0, sizeof(*metadata));
- metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+ metadata->microtile = surface->u.legacy.level[0].mode >=
RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+ metadata->macrotile = surface->u.legacy.level[0].mode >=
RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->pipe_config = surface->pipe_config;
- metadata->bankw = surface->bankw;
- metadata->bankh = surface->bankh;
- metadata->tile_split = surface->tile_split;
- metadata->mtilea = surface->mtilea;
- metadata->num_banks = surface->num_banks;
- metadata->stride = surface->level[0].nblk_x * surface->bpe;
+ metadata->pipe_config = surface->u.legacy.pipe_config;
+ metadata->bankw = surface->u.legacy.bankw;
+ metadata->bankh = surface->u.legacy.bankh;
+ metadata->tile_split = surface->u.legacy.tile_split;
+ metadata->mtilea = surface->u.legacy.mtilea;
+ metadata->num_banks = surface->u.legacy.num_banks;
+ metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
radv_query_opaque_metadata(device, image, metadata);
}
/* The number of samples can be specified independently of the texture. */
static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_image *image,
unsigned nr_samples,
struct radv_fmask_info *out)
{
/* FMASK is allocated like an ordinary texture. */
struct radeon_surf fmask = image->surface;
- struct radeon_surf_info info = image->info;
+ struct ac_surf_info info = image->info;
memset(out, 0, sizeof(*out));
fmask.surf_alignment = 0;
fmask.surf_size = 0;
fmask.flags |= RADEON_SURF_FMASK;
info.samples = 1;
/* Force 2D tiling if it wasn't set. This may occur when creating
* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
* destination buffer must have an FMASK too. */
fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
@@ -481,29 +481,29 @@ radv_image_get_fmask_info(struct radv_device *device,
fmask.bpe = 1;
break;
case 8:
fmask.bpe = 4;
break;
default:
return;
}
device->ws->surface_init(device->ws, &info, &fmask);
- assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+ assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
- out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) /
64;
+ out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x *
fmask.u.legacy.level[0].nblk_y) / 64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
- out->tile_mode_index = fmask.tiling_index[0];
- out->pitch_in_pixels = fmask.level[0].nblk_x;
- out->bank_height = fmask.bankh;
+ out->tile_mode_index = fmask.u.legacy.tiling_index[0];
+ out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
+ out->bank_height = fmask.u.legacy.bankh;
out->alignment = MAX2(256, fmask.surf_alignment);
out->size = fmask.surf_size;
}
static void
radv_image_alloc_fmask(struct radv_device *device,
struct radv_image *image)
{
radv_image_get_fmask_info(device, image, image->info.samples,
&image->fmask);
@@ -750,21 +750,23 @@ radv_image_view_init(struct radv_image_view *iview,
&pCreateInfo->components,
0, radv_get_levelCount(image, range) - 1,
range->baseArrayLayer,
range->baseArrayLayer +
radv_get_layerCount(image, range) - 1,
iview->extent.width,
iview->extent.height,
iview->extent.depth,
iview->descriptor,
iview->fmask_descriptor);
si_set_mutable_tex_desc_fields(device, image,
- is_stencil ?
&image->surface.stencil_level[range->baseMipLevel] :
&image->surface.level[range->baseMipLevel], range->baseMipLevel,
+ is_stencil ?
&image->surface.u.legacy.stencil_level[range->baseMipLevel]
+ :
&image->surface.u.legacy.level[range->baseMipLevel],
+ range->baseMipLevel,
range->baseMipLevel,
blk_w, is_stencil, iview->descriptor);
}
bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout)
{
return (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
}
@@ -835,25 +837,25 @@ void radv_GetImageSubresourceLayout(
VkDevice device,
VkImage _image,
const VkImageSubresource* pSubresource,
VkSubresourceLayout* pLayout)
{
RADV_FROM_HANDLE(radv_image, image, _image);
int level = pSubresource->mipLevel;
int layer = pSubresource->arrayLayer;
struct radeon_surf *surface = &image->surface;
- pLayout->offset = surface->level[level].offset +
surface->level[level].slice_size * layer;
- pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
- pLayout->arrayPitch = surface->level[level].slice_size;
- pLayout->depthPitch = surface->level[level].slice_size;
- pLayout->size = surface->level[level].slice_size;
+ pLayout->offset = surface->u.legacy.level[level].offset +
surface->u.legacy.level[level].slice_size * layer;
+ pLayout->rowPitch = surface->u.legacy.level[level].nblk_x *
surface->bpe;
+ pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
+ pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
+ pLayout->size = surface->u.legacy.level[level].slice_size;
if (image->type == VK_IMAGE_TYPE_3D)
pLayout->size *= u_minify(image->info.depth, level);
}
VkResult
radv_CreateImageView(VkDevice _device,
const VkImageViewCreateInfo *pCreateInfo,
const VkAllocationCallbacks *pAllocator,
VkImageView *pView)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 57b812d..ed4325b 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -797,21 +797,21 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
/* all layers are bound */
if (iview->base_layer > 0)
goto fail;
if (iview->image->info.array_size != iview->layer_count)
goto fail;
if (iview->image->info.levels > 1)
goto fail;
- if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
+ if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
goto fail;
if (!radv_image_extent_compare(iview->image, &iview->extent))
goto fail;
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
clear_rect->rect.extent.width != iview->image->info.width ||
clear_rect->rect.extent.height != iview->image->info.height)
goto fail;
if (clear_rect->baseArrayLayer != 0)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index eda2ea4..518ed6c 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -46,20 +46,21 @@
#include <amdgpu.h>
#include "compiler/shader_enums.h"
#include "util/macros.h"
#include "util/list.h"
#include "util/vk_alloc.h"
#include "main/macros.h"
#include "radv_radeon_winsys.h"
#include "ac_binary.h"
#include "ac_nir_to_llvm.h"
+#include "ac_surface.h"
#include "radv_debug.h"
#include "radv_descriptor_set.h"
#include <llvm-c/TargetMachine.h>
/* Pre-declarations needed for WSI entrypoints */
struct wl_surface;
struct wl_display;
typedef struct xcb_connection_t xcb_connection_t;
typedef uint32_t xcb_visualid_t;
@@ -1156,21 +1157,21 @@ struct r600_htile_info {
unsigned yalign;
};
struct radv_image {
VkImageType type;
/* The original VkFormat provided by the client. This may not match any
* of the actual surface formats.
*/
VkFormat vk_format;
VkImageAspectFlags aspects;
- struct radeon_surf_info info;
+ struct ac_surf_info info;
VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
VkImageTiling tiling; /** VkImageCreateInfo::tiling */
VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
VkDeviceSize size;
uint32_t alignment;
bool exclusive;
unsigned queue_family_mask;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h
b/src/amd/vulkan/radv_radeon_winsys.h
index 1d68629..8173714 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -28,20 +28,23 @@
#ifndef RADV_RADEON_WINSYS_H
#define RADV_RADEON_WINSYS_H
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include "main/macros.h"
#include "amd_family.h"
+struct ac_surf_info;
+struct radeon_surf;
+
#define FREE(x) free(x)
enum radeon_bo_domain { /* bitfield */
RADEON_DOMAIN_GTT = 2,
RADEON_DOMAIN_VRAM = 4,
RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
};
enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_GTT_WC = (1 << 0),
@@ -119,117 +122,35 @@ struct radeon_info {
uint32_t num_render_backends;
uint32_t num_tile_pipes; /* pipe count from
PIPE_CONFIG */
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
/* Tile modes. */
uint32_t si_tile_mode_array[32];
uint32_t cik_macrotile_mode_array[16];
};
-#define RADEON_SURF_MAX_LEVEL 32
-
#define RADEON_SURF_TYPE_MASK 0xFF
#define RADEON_SURF_TYPE_SHIFT 0
#define RADEON_SURF_TYPE_1D 0
#define RADEON_SURF_TYPE_2D 1
#define RADEON_SURF_TYPE_3D 2
#define RADEON_SURF_TYPE_CUBEMAP 3
#define RADEON_SURF_TYPE_1D_ARRAY 4
#define RADEON_SURF_TYPE_2D_ARRAY 5
#define RADEON_SURF_MODE_MASK 0xFF
#define RADEON_SURF_MODE_SHIFT 8
-#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
-#define RADEON_SURF_MODE_1D 2
-#define RADEON_SURF_MODE_2D 3
-#define RADEON_SURF_SCANOUT (1 << 16)
-#define RADEON_SURF_ZBUFFER (1 << 17)
-#define RADEON_SURF_SBUFFER (1 << 18)
-#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER |
RADEON_SURF_SBUFFER)
-#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
-#define RADEON_SURF_FMASK (1 << 21)
-#define RADEON_SURF_DISABLE_DCC (1 << 22)
-#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT)
& RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) <<
RADEON_SURF_ ## field ## _SHIFT)
#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK <<
RADEON_SURF_ ## field ## _SHIFT))
-struct radeon_surf_info {
- uint32_t width;
- uint32_t height;
- uint32_t depth;
- uint8_t samples;
- uint8_t levels;
- uint16_t array_size;
-};
-
-struct radeon_surf_level {
- uint64_t offset;
- uint64_t slice_size;
- uint32_t nblk_x;
- uint32_t nblk_y;
- uint32_t mode;
- uint64_t dcc_offset;
- uint64_t dcc_fast_clear_size;
-};
-
-
-/* surface defintions from the winsys */
-struct radeon_surf {
- /* These are inputs to the calculator. */
- uint32_t blk_w;
- uint32_t blk_h;
- uint32_t bpe;
- uint32_t flags;
-
- unsigned num_dcc_levels:4;
-
- /* These are return values. Some of them can be set by the caller, but
- * they will be treated as hints (e.g. bankw, bankh) and might be
- * changed by the calculator.
- */
- /* This applies to EG and later. */
- uint32_t bankw;
- uint32_t bankh;
- uint32_t mtilea;
- uint32_t tile_split;
- uint32_t stencil_tile_split;
- uint64_t stencil_offset;
- struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
- struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
- uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
- uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
- uint32_t pipe_config;
- uint32_t num_banks;
- uint32_t macro_tile_index;
- uint32_t micro_tile_mode; /* displayable, thin,
depth, rotated */
-
- /* Whether the depth miptree or stencil miptree as used by the DB are
- * adjusted from their TC compatible form to ensure depth/stencil
- * compatibility. If either is true, the corresponding plane cannot be
- * sampled from.
- */
- bool depth_adjusted;
- bool stencil_adjusted;
-
- uint64_t surf_size;
- uint64_t surf_alignment;
-
- uint64_t dcc_size;
- uint64_t dcc_alignment;
-
- uint64_t htile_size;
- uint64_t htile_slice_size;
- uint64_t htile_alignment;
-};
-
enum radeon_bo_layout {
RADEON_LAYOUT_LINEAR = 0,
RADEON_LAYOUT_TILED,
RADEON_LAYOUT_SQUARETILED,
RADEON_LAYOUT_UNKNOWN
};
/* Tiling info for display code, DRI sharing, and other data. */
struct radeon_bo_metadata {
@@ -325,21 +246,21 @@ struct radeon_winsys {
void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
struct radeon_winsys_bo *bo,
uint8_t priority);
void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
struct radeon_winsys_cs *child);
void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t
trace_id);
int (*surface_init)(struct radeon_winsys *ws,
- const struct radeon_surf_info *surf_info,
+ const struct ac_surf_info *surf_info,
struct radeon_surf *surf);
int (*surface_best)(struct radeon_winsys *ws,
struct radeon_surf *surf);
struct radeon_winsys_fence *(*create_fence)();
void (*destroy_fence)(struct radeon_winsys_fence *fence);
bool (*fence_wait)(struct radeon_winsys *ws,
struct radeon_winsys_fence *fence,
bool absolute,
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index e97e0a5..93a53e7 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -217,21 +217,21 @@ radv_wsi_image_create(VkDevice device_h,
goto fail_alloc_memory;
*fd_p = fd;
}
surface = &image->surface;
*image_p = image_h;
*memory_p = memory_h;
*size = image->size;
*offset = image->offset;
- *row_pitch = surface->level[0].nblk_x * surface->bpe;
+ *row_pitch = surface->u.legacy.level[0].nblk_x * surface->bpe;
return VK_SUCCESS;
fail_alloc_memory:
radv_FreeMemory(device_h, memory_h, pAllocator);
fail_create_image:
radv_DestroyImage(device_h, image_h, pAllocator);
return result;
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index eb9c11c..3a682c6 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -28,33 +28,35 @@
#include <errno.h>
#include "radv_private.h"
#include "addrlib/addrinterface.h"
#include "util/bitset.h"
#include "radv_amdgpu_winsys.h"
#include "radv_amdgpu_surface.h"
#include "sid.h"
+#include "ac_surface.h"
+
#ifndef NO_ENTRIES
#define NO_ENTRIES 32
#endif
#ifndef NO_MACRO_ENTRIES
#define NO_MACRO_ENTRIES 16
#endif
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
-static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
+static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
const struct radeon_surf *surf)
{
unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
return -EINVAL;
/* all dimension must be at least 1 ! */
if (!surf_info->width || !surf_info->height || !surf_info->depth ||
!surf_info->array_size)
@@ -152,85 +154,85 @@ ADDR_HANDLE radv_amdgpu_addr_create(struct
amdgpu_gpu_info *amdinfo, int family,
addrCreateInput.regValue = regValue;
addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
if (addrRet != ADDR_OK)
return NULL;
return addrCreateOutput.hLib;
}
static int radv_compute_level(ADDR_HANDLE addrlib,
- const struct radeon_surf_info *surf_info,
+ const struct ac_surf_info *surf_info,
struct radeon_surf *surf, bool is_stencil,
unsigned level, unsigned type, bool compressed,
ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut,
ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
{
- struct radeon_surf_level *surf_level;
+ struct legacy_surf_level *surf_level;
ADDR_E_RETURNCODE ret;
AddrSurfInfoIn->mipLevel = level;
AddrSurfInfoIn->width = u_minify(surf_info->width, level);
AddrSurfInfoIn->height = u_minify(surf_info->height, level);
if (type == RADEON_SURF_TYPE_3D)
AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
else if (type == RADEON_SURF_TYPE_CUBEMAP)
AddrSurfInfoIn->numSlices = 6;
else
AddrSurfInfoIn->numSlices = surf_info->array_size;
if (level > 0) {
/* Set the base level pitch. This is needed for calculation
* of non-zero levels. */
if (is_stencil)
- AddrSurfInfoIn->basePitch =
surf->stencil_level[0].nblk_x;
+ AddrSurfInfoIn->basePitch =
surf->u.legacy.stencil_level[0].nblk_x;
else
- AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
+ AddrSurfInfoIn->basePitch =
surf->u.legacy.level[0].nblk_x;
/* Convert blocks to pixels for compressed formats. */
if (compressed)
AddrSurfInfoIn->basePitch *= surf->blk_w;
}
ret = AddrComputeSurfaceInfo(addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK)
return ret;
- surf_level = is_stencil ? &surf->stencil_level[level] :
&surf->level[level];
+ surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] :
&surf->u.legacy.level[level];
surf_level->offset = align64(surf->surf_size,
AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
break;
case ADDR_TM_1D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_1D;
break;
case ADDR_TM_2D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_2D;
break;
default:
assert(0);
}
if (is_stencil)
- surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
+ surf->u.legacy.stencil_tiling_index[level] =
AddrSurfInfoOut->tileIndex;
else
- surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
+ surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
surf_level->dcc_offset = 0;
/* The previous level's flag tells us if we can use DCC for this level.
*/
if (AddrSurfInfoIn->flags.dccCompatible &&
(level == 0 || AddrDccOut->subLvlCompressible)) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
@@ -275,44 +277,44 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
surf->htile_slice_size = AddrHtileOut.sliceSize;
surf->htile_alignment = AddrHtileOut.baseAlign;
}
}
return 0;
}
static void radv_set_micro_tile_mode(struct radeon_surf *surf,
struct radeon_info *info)
{
- uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
+ uint32_t tile_mode =
info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
{
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
- tileb = MIN2(surf->tile_split, tileb);
+ tileb = MIN2(surf->u.legacy.tile_split, tileb);
for (index = 0; tileb > 64; index++)
tileb >>= 1;
assert(index < 16);
return index;
}
static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
- const struct radeon_surf_info
*surf_info,
+ const struct ac_surf_info *surf_info,
struct radeon_surf *surf)
{
struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
unsigned level, mode, type;
bool compressed;
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
ADDR_TILEINFO AddrTileInfoIn = {0};
@@ -415,29 +417,30 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
*
* TODO: update addrlib to a newer version, remove this, and
* use flags.matchStencilTileCfg = 1 as an alternative fix.
*/
if (last_level > 0)
AddrSurfInfoIn.flags.noStencil = 1;
/* Set preferred macrotile parameters. This is usually required
* for shared resources. This is for 2D tiling only. */
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
- surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
+ surf->u.legacy.bankw && surf->u.legacy.bankh &&
surf->u.legacy.mtilea &&
+ surf->u.legacy.tile_split) {
/* If any of these parameters are incorrect, the calculation
* will fail. */
- AddrTileInfoIn.banks = surf->num_banks;
- AddrTileInfoIn.bankWidth = surf->bankw;
- AddrTileInfoIn.bankHeight = surf->bankh;
- AddrTileInfoIn.macroAspectRatio = surf->mtilea;
- AddrTileInfoIn.tileSplitBytes = surf->tile_split;
- AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1
compared to GB_TILE_MODE */
+ AddrTileInfoIn.banks = surf->u.legacy.num_banks;
+ AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
+ AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
+ AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
+ AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
+ AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /*
+1 compared to GB_TILE_MODE */
AddrSurfInfoIn.flags.opt4Space = 0;
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
/* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
* the tile index, because we are expected to know it if
* we know the other parameters.
*
* This is something that can easily be fixed in Addrlib.
* For now, just figure it out here.
* Note that only 2D_TILE_THIN1 is handled here.
@@ -479,59 +482,59 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
/* Calculate texture layout information. */
for (level = 0; level <= last_level; level++) {
r = radv_compute_level(ws->addrlib, surf_info, surf, false,
level, type, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut);
if (r)
break;
if (level == 0) {
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
- surf->pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
+ surf->u.legacy.pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
radv_set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1)
{
- surf->bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
- surf->bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
- surf->mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
- surf->tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
- surf->num_banks =
AddrSurfInfoOut.pTileInfo->banks;
- surf->macro_tile_index =
AddrSurfInfoOut.macroModeIndex;
+ surf->u.legacy.bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
+ surf->u.legacy.bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
+ surf->u.legacy.mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
+ surf->u.legacy.tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
+ surf->u.legacy.num_banks =
AddrSurfInfoOut.pTileInfo->banks;
+ surf->u.legacy.macro_tile_index =
AddrSurfInfoOut.macroModeIndex;
} else {
- surf->macro_tile_index = 0;
+ surf->u.legacy.macro_tile_index = 0;
}
}
}
/* Calculate texture layout information for stencil. */
if (surf->flags & RADEON_SURF_SBUFFER) {
AddrSurfInfoIn.bpp = 8;
AddrSurfInfoIn.flags.depth = 0;
AddrSurfInfoIn.flags.stencil = 1;
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
- AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
+ AddrTileInfoIn.tileSplitBytes =
surf->u.legacy.stencil_tile_split;
for (level = 0; level <= last_level; level++) {
r = radv_compute_level(ws->addrlib, surf_info, surf,
true, level, type, compressed,
&AddrSurfInfoIn,
&AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
if (r)
return r;
/* DB uses the depth pitch for both stencil and depth.
*/
- if (surf->stencil_level[level].nblk_x !=
surf->level[level].nblk_x)
- surf->stencil_adjusted = true;
+ if (surf->u.legacy.stencil_level[level].nblk_x !=
surf->u.legacy.level[level].nblk_x)
+ surf->u.legacy.stencil_adjusted = true;
if (level == 0) {
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >=
ADDR_TM_2D_TILED_THIN1) {
- surf->stencil_tile_split =
+ surf->u.legacy.stencil_tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
}
}
}
}
/* Recalculate the whole DCC miptree size including disabled levels.
* This is what addrlib does, but calling addrlib would be a lot more
* complicated.
*/
--
2.9.3
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
