From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/amd/common/ac_surface.c | 33 ++++++++++++++++++++++++++
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 16 -------------
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index f0138b5..3d04200 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -23,20 +23,21 @@
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#include "ac_surface.h"
#include "amdgpu_id.h"
#include "util/macros.h"
#include "util/u_math.h"
+#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <amdgpu.h>
#include <amdgpu_drm.h>
#include "addrlib/addrinterface.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
@@ -191,20 +192,46 @@ ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
addrCreateInput.createFlags = createFlags;
addrCreateInput.regValue = regValue;
addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
if (addrRet != ADDR_OK)
return NULL;
return addrCreateOutput.hLib;
}
+static int surf_config_sanity(const struct ac_surf_config *config)
+{
+ /* all dimension must be at least 1 ! */
+ if (!config->info.width || !config->info.height || !config->info.depth
||
+ !config->info.array_size || !config->info.levels)
+ return -EINVAL;
+
+ switch (config->info.samples) {
+ case 0:
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (config->is_3d && config->info.array_size > 1)
+ return -EINVAL;
+ if (config->is_cube && config->info.depth > 1)
+ return -EINVAL;
+
+ return 0;
+}
+
static int gfx6_compute_level(ADDR_HANDLE addrlib,
const struct ac_surf_config *config,
struct radeon_surf *surf, bool is_stencil,
unsigned level, bool compressed,
ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
@@ -1005,15 +1032,21 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
}
return 0;
}
int ac_compute_surface(ADDR_HANDLE addrlib,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
+ int r;
+
+ r = surf_config_sanity(config);
+ if (r)
+ return r;
+
if (config->chip_class >= GFX9)
return gfx9_compute_surface(addrlib, config, mode, surf);
else
return gfx6_compute_surface(addrlib, config, mode, surf);
}
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index ca391e0..cd403f5 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -27,36 +27,20 @@
/* Contact:
* Marek Olšák <mar...@gmail.com>
*/
#include "amdgpu_winsys.h"
#include "util/u_format.h"
static int amdgpu_surface_sanity(const struct pipe_resource *tex)
{
- /* all dimension must be at least 1 ! */
- if (!tex->width0 || !tex->height0 || !tex->depth0 ||
- !tex->array_size)
- return -EINVAL;
-
- switch (tex->nr_samples) {
- case 0:
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default:
- return -EINVAL;
- }
-
switch (tex->target) {
case PIPE_TEXTURE_1D:
if (tex->height0 > 1)
return -EINVAL;
/* fall through */
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
if (tex->depth0 > 1 || tex->array_size > 1)
return -EINVAL;
break;
--
2.9.3
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