From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Vulkan needs it.
---
src/amd/common/ac_surface.c | 4 ++++
src/amd/common/ac_surface.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 486d3f8..376eb47 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -339,20 +339,21 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
ret = AddrComputeHtileInfo(addrlib,
AddrHtileIn,
AddrHtileOut);
if (ret == ADDR_OK) {
surf->htile_size = AddrHtileOut->htileBytes;
+ surf->htile_slice_size = AddrHtileOut->sliceSize;
surf->htile_alignment = AddrHtileOut->baseAlign;
}
}
return 0;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
@@ -569,20 +570,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
/* Addrlib doesn't set this if tileIndex is forced like
above. */
AddrSurfInfoOut.macroModeIndex =
cik_get_macro_tile_index(surf);
}
}
surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = 0;
+ surf->htile_slice_size = 0;
surf->htile_alignment = 1;
/* Calculate texture layout information. */
for (level = 0; level < config->info.levels; level++) {
r = gfx6_compute_level(addrlib, config, surf, false, level,
compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut, &AddrHtileIn,
&AddrHtileOut);
if (r)
return r;
@@ -764,20 +766,21 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
hin.numSlices = in->numSlices;
hin.numMipLevels = in->numMipLevels;
ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
surf->htile_size = hout.htileBytes;
+ surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
} else {
/* DCC */
if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!compressed &&
in->swizzleMode != ADDR_SW_LINEAR &&
/* TODO: We could support DCC with MSAA. */
in->numSamples == 1) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
@@ -950,20 +953,21 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
default:
assert(0);
}
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->htile_size = 0;
+ surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
surf->u.gfx9.stencil_offset = 0;
surf->u.gfx9.fmask_size = 0;
surf->u.gfx9.cmask_size = 0;
/* Calculate texture layout information. */
r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
if (r)
return r;
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 9905be9..bfd2a95 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -159,20 +159,22 @@ struct radeon_surf {
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
uint64_t surf_size;
uint64_t dcc_size;
uint64_t htile_size;
+ uint32_t htile_slice_size;
+
uint32_t surf_alignment;
uint32_t dcc_alignment;
uint32_t htile_alignment;
union {
/* R600-VI return values.
*
* Some of them can be set by the caller if certain parameters are
* desirable. The allocator will try to obey them.
*/
--
2.9.3
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
