From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.
---
src/amd/vulkan/radv_image.c | 11 ++---------
src/amd/vulkan/radv_private.h | 1 -
src/amd/vulkan/radv_radeon_winsys.h | 1 -
src/amd/vulkan/radv_wsi.c | 2 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 1 -
5 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c0fc896..cd1db12 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -439,21 +439,21 @@ radv_init_metadata(struct radv_device *device,
metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->pipe_config = surface->pipe_config;
metadata->bankw = surface->bankw;
metadata->bankh = surface->bankh;
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
- metadata->stride = surface->level[0].pitch_bytes;
+ metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
radv_query_opaque_metadata(device, image, metadata);
}
/* The number of samples can be specified independently of the texture. */
static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_image *image,
unsigned nr_samples,
@@ -667,27 +667,20 @@ radv_image_create(VkDevice _device,
pCreateInfo->mipLevels == 1 &&
!image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
radv_image_alloc_cmask(device, image);
if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format))
{
radv_image_alloc_fmask(device, image);
} else if (vk_format_is_depth(pCreateInfo->format)) {
radv_image_alloc_htile(device, image);
}
-
- if (create_info->stride && create_info->stride !=
image->surface.level[0].pitch_bytes) {
- image->surface.level[0].nblk_x = create_info->stride /
image->surface.bpe;
- image->surface.level[0].pitch_bytes = create_info->stride;
- image->surface.level[0].slice_size = create_info->stride *
image->surface.level[0].nblk_y;
- }
-
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
image->alignment = MAX2(image->alignment, 4096);
image->size = align64(image->size, image->alignment);
image->offset = 0;
image->bo = device->ws->buffer_create(device->ws, image->size,
image->alignment,
0, RADEON_FLAG_VIRTUAL);
if (!image->bo) {
vk_free2(&device->alloc, alloc, image);
return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
@@ -844,21 +837,21 @@ void radv_GetImageSubresourceLayout(
VkImage _image,
const VkImageSubresource* pSubresource,
VkSubresourceLayout* pLayout)
{
RADV_FROM_HANDLE(radv_image, image, _image);
int level = pSubresource->mipLevel;
int layer = pSubresource->arrayLayer;
struct radeon_surf *surface = &image->surface;
pLayout->offset = surface->level[level].offset +
surface->level[level].slice_size * layer;
- pLayout->rowPitch = surface->level[level].pitch_bytes;
+ pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
pLayout->arrayPitch = surface->level[level].slice_size;
pLayout->depthPitch = surface->level[level].slice_size;
pLayout->size = surface->level[level].slice_size;
if (image->type == VK_IMAGE_TYPE_3D)
pLayout->size *= surface->level[level].nblk_z;
}
VkResult
radv_CreateImageView(VkDevice _device,
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b78d221..eda2ea4 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1232,21 +1232,20 @@ struct radv_image_view {
uint32_t layer_count;
uint32_t base_mip;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel.
*/
uint32_t descriptor[8];
uint32_t fmask_descriptor[8];
};
struct radv_image_create_info {
const VkImageCreateInfo *vk_info;
- uint32_t stride;
bool scanout;
};
VkResult radv_image_create(VkDevice _device,
const struct radv_image_create_info *info,
const VkAllocationCallbacks* alloc,
VkImage *pImage);
void radv_image_view_init(struct radv_image_view *view,
struct radv_device *device,
diff --git a/src/amd/vulkan/radv_radeon_winsys.h
b/src/amd/vulkan/radv_radeon_winsys.h
index 84b1d73..df582d8 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -163,21 +163,20 @@ struct radeon_surf_info {
uint8_t levels;
uint16_t array_size;
};
struct radeon_surf_level {
uint64_t offset;
uint64_t slice_size;
uint32_t nblk_x;
uint32_t nblk_y;
uint32_t nblk_z;
- uint32_t pitch_bytes;
uint32_t mode;
bool dcc_enabled;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
};
/* surface defintions from the winsys */
struct radeon_surf {
/* These are inputs to the calculator. */
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 3a8617f..e97e0a5 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -217,21 +217,21 @@ radv_wsi_image_create(VkDevice device_h,
goto fail_alloc_memory;
*fd_p = fd;
}
surface = &image->surface;
*image_p = image_h;
*memory_p = memory_h;
*size = image->size;
*offset = image->offset;
- *row_pitch = surface->level[0].pitch_bytes;
+ *row_pitch = surface->level[0].nblk_x * surface->bpe;
return VK_SUCCESS;
fail_alloc_memory:
radv_FreeMemory(device_h, memory_h, pAllocator);
fail_create_image:
radv_DestroyImage(device_h, image_h, pAllocator);
return result;
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index c972ef1..f8e22da 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -196,21 +196,20 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
ret = AddrComputeSurfaceInfo(addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK)
return ret;
surf_level = is_stencil ? &surf->stencil_level[level] :
&surf->level[level];
surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
- surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 :
surf->bpe);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
if (type == RADEON_SURF_TYPE_3D)
surf_level->nblk_z = AddrSurfInfoOut->depth;
else
surf_level->nblk_z = 1;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
--
2.9.3
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