From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/amd/common/ac_surface.c | 47 ++++++++++++++------------
src/amd/common/ac_surface.h | 11 +++---
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 6 +---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 2 +-
4 files changed, 31 insertions(+), 35 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 3d04200..486d3f8 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -19,21 +19,23 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#include "ac_surface.h"
+#include "amd_family.h"
#include "amdgpu_id.h"
+#include "ac_gpu_info.h"
#include "util/macros.h"
#include "util/u_math.h"
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <amdgpu.h>
#include <amdgpu_drm.h>
#include "addrlib/addrinterface.h"
@@ -136,55 +138,55 @@ static void *ADDR_API allocSysMem(const
ADDR_ALLOCSYSMEM_INPUT * pInput)
{
return malloc(pInput->sizeInBytes);
}
static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *
pInput)
{
free(pInput->pVirtAddr);
return ADDR_OK;
}
-ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
- const struct amdgpu_gpu_info *info)
+ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
+ const struct amdgpu_gpu_info *amdinfo)
{
ADDR_CREATE_INPUT addrCreateInput = {0};
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
- regValue.gbAddrConfig = info->gb_addr_cfg;
+ regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
createFlags.value = 0;
- addrlib_family_rev_id(family, &addrCreateInput.chipFamily,
&addrCreateInput.chipRevision);
+ addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily,
&addrCreateInput.chipRevision);
if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
return NULL;
if (addrCreateInput.chipFamily >= FAMILY_AI) {
addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
regValue.blockVarSizeLog2 = 0;
} else {
- regValue.noOfBanks = info->mc_arb_ramcfg & 0x3;
- regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2;
+ regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
+ regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
- regValue.backendDisables = info->enabled_rb_pipes_mask;
- regValue.pTileConfig = info->gb_tile_mode;
- regValue.noOfEntries = ARRAY_SIZE(info->gb_tile_mode);
+ regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
+ regValue.pTileConfig = amdinfo->gb_tile_mode;
+ regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
if (addrCreateInput.chipFamily == FAMILY_SI) {
regValue.pMacroTileConfig = NULL;
regValue.noOfMacroEntries = 0;
} else {
- regValue.pMacroTileConfig = info->gb_macro_tile_mode;
- regValue.noOfMacroEntries =
ARRAY_SIZE(info->gb_macro_tile_mode);
+ regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
+ regValue.noOfMacroEntries =
ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
}
createFlags.useTileIndex = 1;
createFlags.useHtileSliceAlign = 1;
addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
}
addrCreateInput.callbacks.allocSysMem = allocSysMem;
addrCreateInput.callbacks.freeSysMem = freeSysMem;
@@ -348,25 +350,25 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
}
}
return 0;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
- const struct amdgpu_gpu_info *amdinfo)
+ const struct radeon_info *info)
{
- uint32_t tile_mode =
amdinfo->gb_tile_mode[surf->u.legacy.tiling_index[0]];
+ uint32_t tile_mode =
info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
- if (amdinfo->family_id >= AMDGPU_FAMILY_CI)
+ if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
{
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
@@ -379,20 +381,21 @@ static unsigned cik_get_macro_tile_index(struct
radeon_surf *surf)
return index;
}
/**
* Fill in the tiling information in \p surf based on the given surface config.
*
* The following fields of \p surf must be initialized by the caller:
* blk_w, blk_h, bpe, flags.
*/
static int gfx6_compute_surface(ADDR_HANDLE addrlib,
+ const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
unsigned level;
bool compressed;
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
@@ -484,21 +487,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
config->info.samples <= 1 &&
(surf->flags &
RADEON_SURF_OPTIMIZE_FOR_SPACE);
/* DCC notes:
* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
* with samples >= 4.
* - Mipmapped array textures have low performance (discovered by a
closed
* driver team).
*/
AddrSurfInfoIn.flags.dccCompatible =
- config->chip_class >= VI &&
+ info->chip_class >= VI &&
!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!compressed && AddrDccIn.numSamples <= 1 &&
((config->info.array_size == 1 && config->info.depth == 1) ||
config->info.levels == 1);
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) ==
0;
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
/* noStencil = 0 can result in a depth part that is incompatible with
@@ -533,21 +536,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
* the tile index, because we are expected to know it if
* we know the other parameters.
*
* This is something that can easily be fixed in Addrlib.
* For now, just figure it out here.
* Note that only 2D_TILE_THIN1 is handled here.
*/
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
- if (config->chip_class == SI) {
+ if (info->chip_class == SI) {
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
if (surf->bpe == 2)
AddrSurfInfoIn.tileIndex = 11; /* 16bpp
*/
else
AddrSurfInfoIn.tileIndex = 12; /* 32bpp
*/
} else {
if (surf->bpe == 1)
AddrSurfInfoIn.tileIndex = 14; /* 8bpp
*/
else if (surf->bpe == 2)
AddrSurfInfoIn.tileIndex = 15; /* 16bpp
*/
@@ -579,21 +582,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
for (level = 0; level < config->info.levels; level++) {
r = gfx6_compute_level(addrlib, config, surf, false, level,
compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut, &AddrHtileIn,
&AddrHtileOut);
if (r)
return r;
if (level == 0) {
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
surf->u.legacy.pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
- gfx6_set_micro_tile_mode(surf, config->amdinfo);
+ gfx6_set_micro_tile_mode(surf, info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1)
{
surf->u.legacy.bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
surf->u.legacy.bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
surf->u.legacy.mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->u.legacy.tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->u.legacy.num_banks =
AddrSurfInfoOut.pTileInfo->banks;
surf->u.legacy.macro_tile_index =
AddrSurfInfoOut.macroModeIndex;
} else {
@@ -633,22 +636,22 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
}
}
}
/* Recalculate the whole DCC miptree size including disabled levels.
* This is what addrlib does, but calling addrlib would be a lot more
* complicated.
*/
if (surf->dcc_size && config->info.levels > 1) {
surf->dcc_size = align64(surf->surf_size >> 8,
- config->pipe_interleave_bytes *
- config->num_tile_pipes);
+ info->pipe_interleave_bytes *
+ info->num_tile_pipes);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
* TC-compatible HTILE even for levels where it's disabled by DB.
*/
if (surf->htile_size && config->info.levels > 1)
surf->htile_size *= 2;
surf->is_linear = surf->u.legacy.level[0].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED;
return 0;
@@ -1027,26 +1030,26 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
break;
default:
assert(0);
}
return 0;
}
-int ac_compute_surface(ADDR_HANDLE addrlib,
+int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
int r;
r = surf_config_sanity(config);
if (r)
return r;
- if (config->chip_class >= GFX9)
+ if (info->chip_class >= GFX9)
return gfx9_compute_surface(addrlib, config, mode, surf);
else
- return gfx6_compute_surface(addrlib, config, mode, surf);
+ return gfx6_compute_surface(addrlib, info, config, mode, surf);
}
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 73649c7..9905be9 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -27,20 +27,21 @@
#define AC_SURFACE_H
#include <stdint.h>
#include "amd_family.h"
/* Forward declarations. */
typedef void* ADDR_HANDLE;
struct amdgpu_gpu_info;
+struct radeon_info;
#define RADEON_SURF_MAX_LEVELS 15
enum radeon_surf_mode {
RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
RADEON_SURF_MODE_1D = 2,
RADEON_SURF_MODE_2D = 3,
};
/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
@@ -188,25 +189,21 @@ struct ac_surf_info {
uint32_t depth;
uint8_t samples;
uint8_t levels;
uint16_t array_size;
};
struct ac_surf_config {
struct ac_surf_info info;
unsigned is_3d : 1;
unsigned is_cube : 1;
- enum chip_class chip_class : 4;
- unsigned num_tile_pipes;
- unsigned pipe_interleave_bytes;
- const struct amdgpu_gpu_info *amdinfo;
};
-ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
- const struct amdgpu_gpu_info *info);
+ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
+ const struct amdgpu_gpu_info *amdinfo);
-int ac_compute_surface(ADDR_HANDLE addrlib,
+int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config * config,
enum radeon_surf_mode mode,
struct radeon_surf *surf);
#endif /* AC_SURFACE_H */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index cd403f5..1a2b7c4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -85,22 +85,18 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
struct ac_surf_config config;
config.info.width = tex->width0;
config.info.height = tex->height0;
config.info.depth = tex->depth0;
config.info.array_size = tex->array_size;
config.info.samples = tex->nr_samples;
config.info.levels = tex->last_level + 1;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
- config.chip_class = ws->info.chip_class;
- config.num_tile_pipes = ws->info.num_tile_pipes;
- config.pipe_interleave_bytes = ws->info.pipe_interleave_bytes;
- config.amdinfo = &ws->amdinfo;
- return ac_compute_surface(ws->addrlib, &config, mode, surf);
+ return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
}
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
{
ws->base.surface_init = amdgpu_surface_init;
}
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 4398bbc..0430c7e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -52,21 +52,21 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
goto fail;
/* LLVM 5.0 is required for GFX9. */
if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
HAVE_LLVM >> 8, HAVE_LLVM & 255);
goto fail;
}
- ws->addrlib = amdgpu_addr_create(ws->info.family, &ws->amdinfo);
+ ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
goto fail;
}
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
NULL;
return true;
fail:
--
2.9.3
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