From: Nicolai Hähnle <nicolai.haeh...@amd.com>
To match radeonsi / ac_surface.
---
src/amd/vulkan/radv_image.c | 12 ++++++------
src/amd/vulkan/radv_radeon_winsys.h | 5 +++--
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 8 ++++----
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 6225240..04ae293 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -456,22 +456,22 @@ static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_image *image,
unsigned nr_samples,
struct radv_fmask_info *out)
{
/* FMASK is allocated like an ordinary texture. */
struct radeon_surf fmask = image->surface;
struct radeon_surf_info info = image->info;
memset(out, 0, sizeof(*out));
- fmask.bo_alignment = 0;
- fmask.bo_size = 0;
+ fmask.surf_alignment = 0;
+ fmask.surf_size = 0;
fmask.flags |= RADEON_SURF_FMASK;
info.samples = 1;
/* Force 2D tiling if it wasn't set. This may occur when creating
* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
* destination buffer must have an FMASK too. */
fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
@@ -490,22 +490,22 @@ radv_image_get_fmask_info(struct radv_device *device,
device->ws->surface_init(device->ws, &info, &fmask);
assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) /
64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
- out->alignment = MAX2(256, fmask.bo_alignment);
- out->size = fmask.bo_size;
+ out->alignment = MAX2(256, fmask.surf_alignment);
+ out->size = fmask.surf_size;
}
static void
radv_image_alloc_fmask(struct radv_device *device,
struct radv_image *image)
{
radv_image_get_fmask_info(device, image, image->info.samples,
&image->fmask);
image->fmask.offset = align64(image->size, image->fmask.alignment);
image->size = image->fmask.offset + image->fmask.size;
@@ -643,22 +643,22 @@ radv_image_create(VkDevice _device,
image->exclusive = pCreateInfo->sharingMode ==
VK_SHARING_MODE_EXCLUSIVE;
if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount;
++i)
image->queue_family_mask |= 1u <<
pCreateInfo->pQueueFamilyIndices[i];
}
radv_init_surface(device, &image->surface, create_info);
device->ws->surface_init(device->ws, &image->info, &image->surface);
- image->size = image->surface.bo_size;
- image->alignment = image->surface.bo_alignment;
+ image->size = image->surface.surf_size;
+ image->alignment = image->surface.surf_alignment;
if (image->exclusive || image->queue_family_mask == 1)
can_cmask_dcc = true;
if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
image->surface.dcc_size && can_cmask_dcc)
radv_image_alloc_dcc(device, image);
else
image->surface.dcc_size = 0;
diff --git a/src/amd/vulkan/radv_radeon_winsys.h
b/src/amd/vulkan/radv_radeon_winsys.h
index 660bea5..1d68629 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -181,22 +181,20 @@ struct radeon_surf {
uint32_t blk_h;
uint32_t bpe;
uint32_t flags;
unsigned num_dcc_levels:4;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
- uint64_t bo_size;
- uint64_t bo_alignment;
/* This applies to EG and later. */
uint32_t bankw;
uint32_t bankh;
uint32_t mtilea;
uint32_t tile_split;
uint32_t stencil_tile_split;
uint64_t stencil_offset;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
@@ -207,20 +205,23 @@ struct radeon_surf {
uint32_t micro_tile_mode; /* displayable, thin,
depth, rotated */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
bool depth_adjusted;
bool stencil_adjusted;
+ uint64_t surf_size;
+ uint64_t surf_alignment;
+
uint64_t dcc_size;
uint64_t dcc_alignment;
uint64_t htile_size;
uint64_t htile_slice_size;
uint64_t htile_alignment;
};
enum radeon_bo_layout {
RADEON_LAYOUT_LINEAR = 0,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 44b1c8f..eb9c11c 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -194,21 +194,21 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
AddrSurfInfoIn->basePitch *= surf->blk_w;
}
ret = AddrComputeSurfaceInfo(addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK)
return ret;
surf_level = is_stencil ? &surf->stencil_level[level] :
&surf->level[level];
- surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
+ surf_level->offset = align64(surf->surf_size,
AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
break;
case ADDR_TM_1D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_1D;
@@ -218,21 +218,21 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
break;
default:
assert(0);
}
if (is_stencil)
surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
else
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
- surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+ surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
surf_level->dcc_offset = 0;
/* The previous level's flag tells us if we can use DCC for this level.
*/
if (AddrSurfInfoIn->flags.dccCompatible &&
(level == 0 || AddrDccOut->subLvlCompressible)) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
@@ -463,36 +463,36 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
}
} else {
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
AddrSurfInfoIn.tileIndex = 10; /* 2D
displayable */
else
AddrSurfInfoIn.tileIndex = 14; /* 2D
non-displayable */
AddrSurfInfoOut.macroModeIndex =
cik_get_macro_tile_index(surf);
}
}
- surf->bo_size = 0;
+ surf->surf_size = 0;
surf->num_dcc_levels = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = surf->htile_slice_size = 0;
surf->htile_alignment = 1;
/* Calculate texture layout information. */
for (level = 0; level <= last_level; level++) {
r = radv_compute_level(ws->addrlib, surf_info, surf, false,
level, type, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut);
if (r)
break;
if (level == 0) {
- surf->bo_alignment = AddrSurfInfoOut.baseAlign;
+ surf->surf_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
radv_set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1)
{
surf->bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
surf->bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
surf->mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->num_banks =
AddrSurfInfoOut.pTileInfo->banks;
--
2.9.3
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