From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/amd/common/ac_surface.c | 27 ++++++++++++++++++--------
src/amd/common/ac_surface.h | 12 ++++--------
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 5 +----
3 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index a751660..f0138b5 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -351,24 +351,24 @@ static unsigned cik_get_macro_tile_index(struct
radeon_surf *surf)
assert(index < 16);
return index;
}
/**
* Fill in the tiling information in \p surf based on the given surface config.
*
* The following fields of \p surf must be initialized by the caller:
* blk_w, blk_h, bpe, flags.
*/
-int gfx6_compute_surface(ADDR_HANDLE addrlib,
- const struct ac_surf_config *config,
- enum radeon_surf_mode mode,
- struct radeon_surf *surf)
+static int gfx6_compute_surface(ADDR_HANDLE addrlib,
+ const struct ac_surf_config *config,
+ enum radeon_surf_mode mode,
+ struct radeon_surf *surf)
{
unsigned level;
bool compressed;
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
ADDR_TILEINFO AddrTileInfoIn = {0};
@@ -836,24 +836,24 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
surf->u.gfx9.cmask.rb_aligned =
cin.cMaskFlags.rbAligned;
surf->u.gfx9.cmask.pipe_aligned =
cin.cMaskFlags.pipeAligned;
surf->u.gfx9.cmask_size = cout.cmaskBytes;
surf->u.gfx9.cmask_alignment = cout.baseAlign;
}
}
return 0;
}
-int gfx9_compute_surface(ADDR_HANDLE addrlib,
- const struct ac_surf_config *config,
- enum radeon_surf_mode mode,
- struct radeon_surf *surf)
+static int gfx9_compute_surface(ADDR_HANDLE addrlib,
+ const struct ac_surf_config *config,
+ enum radeon_surf_mode mode,
+ struct radeon_surf *surf)
{
bool compressed;
ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
int r;
assert(!(surf->flags & RADEON_SURF_FMASK));
AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
compressed = surf->blk_w == 4 && surf->blk_h == 4;
@@ -999,10 +999,21 @@ int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_VAR_Z_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
break;
default:
assert(0);
}
return 0;
}
+
+int ac_compute_surface(ADDR_HANDLE addrlib,
+ const struct ac_surf_config *config,
+ enum radeon_surf_mode mode,
+ struct radeon_surf *surf)
+{
+ if (config->chip_class >= GFX9)
+ return gfx9_compute_surface(addrlib, config, mode, surf);
+ else
+ return gfx6_compute_surface(addrlib, config, mode, surf);
+}
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 9a9697b..73649c7 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -197,20 +197,16 @@ struct ac_surf_config {
unsigned is_cube : 1;
enum chip_class chip_class : 4;
unsigned num_tile_pipes;
unsigned pipe_interleave_bytes;
const struct amdgpu_gpu_info *amdinfo;
};
ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
const struct amdgpu_gpu_info *info);
-int gfx6_compute_surface(ADDR_HANDLE addrlib,
- const struct ac_surf_config *config,
- enum radeon_surf_mode mode,
- struct radeon_surf *surf);
-int gfx9_compute_surface(ADDR_HANDLE addrlib,
- const struct ac_surf_config *config,
- enum radeon_surf_mode mode,
- struct radeon_surf *surf);
+int ac_compute_surface(ADDR_HANDLE addrlib,
+ const struct ac_surf_config * config,
+ enum radeon_surf_mode mode,
+ struct radeon_surf *surf);
#endif /* AC_SURFACE_H */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 76596e8..ca391e0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -106,20 +106,17 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.info.array_size = tex->array_size;
config.info.samples = tex->nr_samples;
config.info.levels = tex->last_level + 1;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
config.chip_class = ws->info.chip_class;
config.num_tile_pipes = ws->info.num_tile_pipes;
config.pipe_interleave_bytes = ws->info.pipe_interleave_bytes;
config.amdinfo = &ws->amdinfo;
- if (ws->info.chip_class >= GFX9)
- return gfx9_compute_surface(ws->addrlib, &config, mode, surf);
- else
- return gfx6_compute_surface(ws->addrlib, &config, mode, surf);
+ return ac_compute_surface(ws->addrlib, &config, mode, surf);
}
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
{
ws->base.surface_init = amdgpu_surface_init;
}
--
2.9.3
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