Scott Wood <scottw...@freescale.com> wrote on 2010/12/10 18:56:39: > > On Fri, 10 Dec 2010 13:39:01 +0100 > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > Scott Wood <scottw...@freescale.com> wrote on 2010/12/08 23:25:59: > > > > > > On Wed, 8 Dec 2010 17:02:45 -0500 > > > Mark Mason <ma...@postdiluvian.org> wrote: > > > > > > > I don't think that using a software NAND controller instead of the LBC > > > > FCM mode is all that bad. Again, I haven't actually done it, so check > > > > the MTD docs, but I'm pretty sure the software is meant to do that, so > > > > it doesn't even really constitute a "fix". Assuming that it is > > > > supported then I doubt that configuring the NAND layer to use your > > > > setup would be any harder than configuring the FCM. > > > > > > The MTD layer supports some really simple NAND controllers, but what do > > > you mean by not having a controller at all? Hooking everything up to > > > GPIO? Using UPM? > > > > > > There is already a UPM NAND driver, BTW. > > > > > > You would lose hardware ECC and the ability to be interrupt-driven (the > > > latter should be possible with SW changes, using GPIO interrupts). > > > > hmm, you think it would be possible to use one of the IRQ pins instead? > > GPIO should be fine, software just needs to be changed to use the > interrupt functionality. > > An external IRQ line would let you limit interrupts to rising edges > rather than all edges, though you'd lose the ability to directly read > the line status.
oh, one cannot read the IRQ line? didn't know that. Also I not sure all Freescale CPUs can do rising edge. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
