On Wed, 8 Dec 2010 21:11:08 +0100 Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote:
> Scott Wood <scottw...@freescale.com> wrote on 2010/12/08 20:59:28: > > > > On Wed, 8 Dec 2010 20:57:03 +0100 > > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > > > Can you think of any workaround such as not connecting the BUSY pin at > > > all? > > > > Maybe connect the busy pin to a gpio? > > Is BUSY required for sane operation or it an optimization? You could probably get away without it by inserting delays if you know the chip specs well enough. > Is there any risk that the NAND device will drive the LB and corrupt > the bus for other devices? I think the only thing the NAND chip should be driving is the busy pin, until nCE and nRE are lowered. -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
