On Thursday, June 13, 2024 at 12:56:09 PM PDT, Christian Kennedy via cctalk <cctalk@classiccmp.org> wrote:
[[ ...compiler, or human writing assembler, responsible for avoiding hazards in MIPS delay slots.... ]] MIPS is of course (allegedly) an acronym for "Microprocessor without Interlocked Pipeline Stages". No interlocking between pipeline stages mean no hardware avoidance (delays, pipeline bubbles) of hazards. So hardly surprising that authors of MIPS assembly-level code are/were responsible for scheduling that code to avoid what would otherwise be pipeline hazards.
