> On Jun 13, 2024, at 7:31 PM, ben via cctalk <cctalk@classiccmp.org> wrote:
>
> On 2024-06-13 11:32 a.m., Paul Koning via cctalk wrote:
> e up an entire chassis, 750-ish logic modules.
>>
>>> You never see a gate level delays on a spec sheet.
>>> Our pipeline is X delays + N delays for a latch.
>> Gate level delays are not interesting for the machine user to know. What is
>> interesting is the detailed properties of the pipelines, including whether
>> they can accept a new operation every cycle or just every N cycles (say, a
>> multiplier that accepts operands every 2 cycles); how many cycles is the
>> delay from input to output; and whether there are "bypass" data paths to
>> reduce the delays from input or output conflicts. Often these details are
>> hard to pry out of the manufacturer; often they are not documented in the
>> standard data sheets or processor user manuals. But they are critical if
>> you want to do work such as pipeline models to drive compiler optimizers.
>
> But I want to know, how to compare machines if you can't compare the logic.
You compare machines by what they deliver. The purpose of computers is not to
deliver logic circuits but to deliver computation, so comparing computational
ability (speed and size) is meaningful, along with cost. How it's implemented
under the covers is not. Yes, the implementation details affect the user's
figures of merit, but those figures and not the logic choices made by the
designers matter.
paul
