On Thu, 13 Jun 2024, Jonathan Stone via cctalk wrote: > MIPS is of course (allegedly) an acronym for "Microprocessor without > Interlocked Pipeline Stages". > > No interlocking between pipeline stages mean no hardware avoidance > (delays, pipeline bubbles) of hazards. So hardly surprising that authors > of MIPS assembly-level code are/were responsible for scheduling that > code to avoid what would otherwise be pipeline hazards.
The architecture designers cheated however even in the original ISA in that moves from the MD accumulator did interlock. I guess they figured people (either doing it by hand or by writing a compiler) wouldn't get that right anyway. ;) Maciej
