On Thursday, June 13, 2024 at 03:00:22 PM PDT, Maciej W. Rozycki via cctalk <cctalk@classiccmp.org> wrote:
> The architecture designers cheated however even in the original ISA in > that moves from the MD accumulator did interlock. I guess they figured > people (either doing it by hand or by writing a compiler) wouldn't get >that right anyway. ;) I always assumed that was because the latency of multiply, let alone divide, was far too many cycles for anyone to plausibly schedule "useful" instructions into. Wasn't r4000 divide latency over 60 cycles? Wasn't r4000 divide latency more than 60 cycles?
