On 6/12/24 01:02, Peter Corlett via cctalk wrote: > Fun factoid: despite modern x86 being clocked ~1000x faster than ye olde > 6502, there's not much in it between them when it comes to interrupt > response time. If all goes well, x86 takes "only" a hundred-ish cycles to do > its book-keeping and jump to the ISR, but if SMM is active (spoiler: it > always is and you can't turn it off) then it introduces a massive amount of > extra jitter and all bets are off.
Which accounts for some members of the NEC V-series having up to 8 alternate sets of registers for fast context switching. I have no idea why Intel didn't follow suit with its 80186 variants. --Chuck
