True, if 1 cycle per second or minute is an acceptable emulation speed🙂.
For that kind of emulation to work the emulator needs to be fed the same tasks in the same order and for the same core. This is even more true when the CPU is waiting on internal or external resources. If you can emulate all of the cores, all 3 (or more) levels of cache, all possible branch prediction, all possible out of order execution and all possible external influences then yes you can emulation anything. But that would be like using one of today's petaflop hyper computers to emulate an ARM 9 running at the speed of a Z-80 or even slower.
On 4/22/2024 2:57 PM, Paul Koning wrote:
On Apr 22, 2024, at 3:45 PM, Mike Katz <bit...@12bitsbest.com> wrote: Cycle accurate emulation becomes impossible in the following circumstances: • Branch prediction and pipelining can cause out of order execution and the execution path become data dependent. ...I disagree. Clearly a logic model will do cycle accurate simulation. So an abstraction of that which still preserves the details of out of order execution, data dependency, etc., will also be cycle accurate. It certainly is true that modern high performance processors with all those complexities are hard to simulate, but not impossible. paul
