> On Apr 22, 2024, at 4:24 PM, Mike Katz via cctalk <cctalk@classiccmp.org> > wrote: > >> Again, not impossible, but very likely not feasable. > > Well not possible with the hardware available at the time. > > If one cycle per minute or less is acceptable then I guess it was possible. > > That is why we used in circuit emulators to do cycle accurate counting on > more complex machines. This machines were clunky and unreliable but they > worked for the most part. Well, the SB-1 is a multi-core pipelined machine with multiple caches and all sorts of other complications. And the company certainly had a cycle accurate simulator. They were reluctant to let it out to customers, but we leaned hard enough. It was slow, indeed. Certainly not a cycle per minute; I'm pretty sure it was a whole lot more than a cycle per second. Given that the code I was debugging was only a few hundred instructions long, it was quite acceptable. Speaking of slow emulation: a CDC 6600 gate level model, in VHDL, is indeed slow. Now we're indeed talking about a cycle per second. I'm thinking I could translate the VHDL to C and have it go faster (by omitting irrelevant detail that VHDL carees about but the simulation doesn't). paul
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