Again, not impossible, but very likely not feasable.
Well not possible with the hardware available at the time.
If one cycle per minute or less is acceptable then I guess it was possible.
That is why we used in circuit emulators to do cycle accurate counting
on more complex machines. This machines were clunky and unreliable but
they worked for the most part.
On 4/22/2024 3:12 PM, Fred Cisin via cctalk wrote:
On Mon, 22 Apr 2024, Mike Katz via cctalk wrote:
Cycle accurate emulation becomes impossible in the following
circumstances:
* Branch prediction and pipelining can cause out of order execution
and the execution path become data dependent.
* Cache memory. It can be very difficult to predict a cache flush or
cache miss or cache look aside buffer hit
* Memory management can inject wait states and cause other cycle
counting issues
* Peripherals can inject unpredictable wait states
* Multi-core processors because you don't necessarily know what core
is doing what and possibly one core waiting on another core.
* DMA can cause some CPUs to pause because the bus is busy doing DMA
transfers (not all processors have this as an issue).
* Some CPUs shut down clocks and peripherals if they are not used and
they take time to re-start.
* Any code that waits for some kind of external input.
Ridiculously impractical, but not impossible.
All of those things could be calculated, and worked around.
Admittedly, we might not have a machine fast enough to do so.
Whereas, emulation that doesn't need to do those can be done with
systems not extremely faster than the one being emulated.
When I was working for a 6800 C compiler company we could simulate
all 68000 CPUs before the 68020. The 68020 with it's pipelining and
branch prediction made it impossible to do cycle accurate timing.
Again, not impossible, but very likely not feasable.
--
Grumpy Ol' Fred ci...@xenosoft.com
