[USRP-users] Re: Timed Commands Not Working

[Dustin Widmann]

"Hopefully, someone can try the uhd "test_timed_commands" example in 4.1 to..."

Figure I ought to be about as good as the next somebody.

test_timed_commands output with UHD 4.1.0 and an X310


Creating the usrp device with: ...

[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 8000 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
Using Device: Single USRP:
  Device: X-Series Device
  Mboard 0: X310
  RX Channel: 0
    RX DSP: 0
    RX Dboard: A
    RX Subdev: UBX RX
  RX Channel: 1
    RX DSP: 1
    RX Dboard: B
    RX Subdev: UBX RX
  TX Channel: 0
    TX DSP: 0
    TX Dboard: A
    TX Subdev: UBX TX
  TX Channel: 1
    TX DSP: 1
    TX Dboard: B
    TX Subdev: UBX TX


Testing support for timed commands on this hardware... pass

Perform fast readback of registers:
 Difference between paired reads: 1079.015300 us

Testing control timed command:
 Span      : 100000.000000 us
 Now       : 253256.340000 us
 Response 1: 254437.230000 us
 Response 2: 255676.840000 us
 Difference of response time 1: -98819.110000 us
 Difference of response time 2: -197579.500000 us
 Difference between actual and expected time delta: -98760.390000 us

About to start streaming using timed command:
 Received packet: 100 samples, 0 full secs, 0.365935 frac secs
 Stream time was: 0 full secs, 0.365935 frac secs
 Difference between stream time and first packet: 0.000000 us

Done!

-Dustin

On 2/3/22 08:02, Jim Palladino wrote:

[INFO] [UHD] linux; GNU C++ version 11.2.0; Boost_107800; UHD_4.1.0.HEAD-0-g6bd0be9c

Thanks, Rob. I always appreciate when you "chime in". Hopefully, someone can try the uhd "test_timed_commands" example in 4.1 to help confirm whether or not it's a problem with something on my end or with UHD. Marcus already confirmed its working for him with an N310 and UHD 3.15.

Thanks,
Jim

------------------------------------------------------------------------
*From:* Rob Kossler <rkoss...@nd.edu>
*Sent:* Wednesday, February 2, 2022 3:26 PM
*To:* Jim Palladino <j...@gardettoengineering.com>

*Subject:* Re: [USRP-users] Re: Timed Commands Not Working
Hi Jim,

Rob



    Just to add one more data point, I just ran test_timed_commands on
    a different computer connected to an X310 -- still UHD 4.1. I have
    the same problem with that device where it looks like timed
    commands are not working right.

    Thanks,
    Jim

    ------------------------------------------------------------------------
    *From:* Jim Palladino <j...@gardettoengineering.com>
    *Sent:* Wednesday, February 2, 2022 10:44 AM
    *To:* Marcus D. Leech <patchvonbr...@gmail.com>;
    usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
    *Subject:* Re: [USRP-users] Re: Timed Commands Not Working
    Correct -- I am using the stock FPGA image for the E320 and the N320.

    Thanks,
    Jim

    ------------------------------------------------------------------------
    *From:* Marcus D. Leech <patchvonbr...@gmail.com>
    *Sent:* Wednesday, February 2, 2022 10:39 AM
    *To:* Jim Palladino <j...@gardettoengineering.com>;
    usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
    *Subject:* Re: [USRP-users] Re: Timed Commands Not Working
    On 2022-02-02 10:21, Jim Palladino wrote:

*Cc:* Marcus D. Leech <patchvonbr...@gmail.com>; usrp-users@lists.ettus.com <usrp-users@lists.ettus.com> This sounds like a pretty big issue. I haven't chimed in because I couldn't say for sure if timed commands were working for me or not in UHD 4.1. I am using N321s with shared LO, so the normal commands I use for setting frequency aren't critical (from a timed command perspective) except for how the DDC/DUC might be handling them. In any case, once you find out the issue, could you please share the solution here. If I get a chance, I will try this on some of my devices. On Wed, Feb 2, 2022 at 12:22 PM Jim Palladino <j...@gardettoengineering.com> wrote:

    Thanks Marcus. Please let me know if R&D comes back with
    anything. I'm at a bit of a loss . . .

    Thanks,
    Jim

    ------------------------------------------------------------------------

    Just to clarify--this is with the stock FPGA image, correct?


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