This is what I obtain from the two commands. In the image loader command, if I do not specify the image it takes automatically the XG, which is the same I used to program the FPGA with Vivado (2x10G).
``` abusso@ttclabsdr:~$ uhd_usrp_probe ``` ``` linux; GNU C++ version 7.3.0; Boost_106501; UHD_003.010.003.000-0-unknown ``` ``` -- X300 initialization sequence... ``` ``` -- Determining maximum frame size... 8000 bytes. ``` ``` -- Setup basic communication... ``` ``` -- Loading values from EEPROM... ``` ``` -- Setup RF frontend clocking... ``` ``` -- Radio 1x clock:200 ``` ``` -- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1302.6MB/s) ``` ``` -- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1304.5MB/s) ``` ``` -- [RFNoC Radio] Performing register loopback test... pass ``` ``` -- [RFNoC Radio] Performing register loopback test... pass ``` ``` -- [RFNoC Radio] Performing register loopback test... pass ``` ``` -- [RFNoC Radio] Performing register loopback test... pass ``` ``` -- Performing timer loopback test... pass ``` ``` -- Performing timer loopback test... pass ``` ``` _____________________________________________________ ``` ``` / ``` ``` | Device: X-Series Device ``` ``` | _____________________________________________________ ``` ``` | / ``` ``` | | Mboard: X310 ``` ``` | | revision: 11 ``` ``` | | revision_compat: 7 ``` ``` | | product: 30818 ``` ``` | | mac-addr0: 00:80:2f:30:8e:01 ``` ``` | | mac-addr1: 00:80:2f:30:8e:02 ``` ``` | | gateway: 192.168.10.1 ``` ``` | | ip-addr0: 192.168.10.2 ``` ``` | | subnet0: 255.255.255.0 ``` ``` | | ip-addr1: 192.168.20.2 ``` ``` | | subnet1: 255.255.255.0 ``` ``` | | ip-addr2: 192.168.30.2 ``` ``` | | subnet2: 255.255.255.0 ``` ``` | | ip-addr3: 192.168.40.2 ``` ``` | | subnet3: 255.255.255.0 ``` ``` | | serial: 31D7872 ``` ``` | | name: TTC_X310 ``` ``` | | FW Version: 5.1 ``` ``` | | FPGA Version: 33.0 ``` ``` | | RFNoC capable: Yes ``` ``` | | ``` ``` | | Time sources: internal, external, gpsdo ``` ``` | | Clock sources: internal, external, gpsdo ``` ``` | | Sensors: ref_locked ``` ``` | | _____________________________________________________ ``` ``` | | / ``` ``` | | | RX Dboard: A ``` ``` | | | ID: UBX-160 v2 (0x007e) ``` ``` | | | Serial: 31D5853 ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | RX Frontend: 0 ``` ``` | | | | Name: UBX RX ``` ``` | | | | Antennas: TX/RX, RX2, CAL ``` ``` | | | | Sensors: lo_locked ``` ``` | | | | Freq range: 10.000 to 6000.000 MHz ``` ``` | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB ``` ``` | | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz ``` ``` | | | | Connection Type: IQ ``` ``` | | | | Uses LO offset: No ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | RX Codec: A ``` ``` | | | | Name: ads62p48 ``` ``` | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB ``` ``` | | _____________________________________________________ ``` ``` | | / ``` ``` | | | RX Dboard: B ``` ``` | | | ID: UBX-160 v2 (0x007e) ``` ``` | | | Serial: 31D5807 ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | RX Frontend: 0 ``` ``` | | | | Name: UBX RX ``` ``` | | | | Antennas: TX/RX, RX2, CAL ``` ``` | | | | Sensors: lo_locked ``` ``` | | | | Freq range: 10.000 to 6000.000 MHz ``` ``` | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB ``` ``` | | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz ``` ``` | | | | Connection Type: IQ ``` ``` | | | | Uses LO offset: No ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | RX Codec: B ``` ``` | | | | Name: ads62p48 ``` ``` | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB ``` ``` | | _____________________________________________________ ``` ``` | | / ``` ``` | | | TX Dboard: A ``` ``` | | | ID: UBX-160 v2 (0x007d) ``` ``` | | | Serial: 31D5853 ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | TX Frontend: 0 ``` ``` | | | | Name: UBX TX ``` ``` | | | | Antennas: TX/RX, CAL ``` ``` | | | | Sensors: lo_locked ``` ``` | | | | Freq range: 10.000 to 6000.000 MHz ``` ``` | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB ``` ``` | | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz ``` ``` | | | | Connection Type: QI ``` ``` | | | | Uses LO offset: No ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | TX Codec: A ``` ``` | | | | Name: ad9146 ``` ``` | | | | Gain Elements: None ``` ``` | | _____________________________________________________ ``` ``` | | / ``` ``` | | | TX Dboard: B ``` ``` | | | ID: UBX-160 v2 (0x007d) ``` ``` | | | Serial: 31D5807 ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | TX Frontend: 0 ``` ``` | | | | Name: UBX TX ``` ``` | | | | Antennas: TX/RX, CAL ``` ``` | | | | Sensors: lo_locked ``` ``` | | | | Freq range: 10.000 to 6000.000 MHz ``` ``` | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB ``` ``` | | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz ``` ``` | | | | Connection Type: QI ``` ``` | | | | Uses LO offset: No ``` ``` | | | _____________________________________________________ ``` ``` | | | / ``` ``` | | | | TX Codec: B ``` ``` | | | | Name: ad9146 ``` ``` | | | | Gain Elements: None ``` ``` | | _____________________________________________________ ``` ``` | | / ``` ``` | | | RFNoC blocks on this device: ``` ``` | | | ``` ``` | | | * DmaFIFO_0 ``` ``` | | | * Radio_0 ``` ``` | | | * Radio_1 ``` ``` | | | * DDC_0 ``` ``` | | | * DDC_1 ``` ``` | | | * DUC_0 ``` ``` | | | * DUC_1 ``` ``` abusso@ttclabsdr:~$ uhd_image_loader --args "type=x300,addr=192.168.30.2" ``` ``` linux; GNU C++ version 7.3.0; Boost_106501; UHD_003.010.003.000-0-unknown ``` ``` Unit: USRP X310 (31D7872, 192.168.30.2) ``` ``` FPGA Image: /usr/share/uhd/images/usrp_x310_fpga_XG.bit ``` ``` failed. ``` ``` Error: RuntimeError: Device reported an error during initialization. ``` ``` abusso@ttclabsdr:~$ ```
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