Thank you all for your help. I have been going through both the FPGA and
host-side driver code for the B200mini and, in my still very limited
understanding of SDRs in general, have come up with the following DDC chain:
1. multiplex 12-bit I and Q into 24-bit value
2. phase align with the NCO
3. use the CORDIC functionality to perform the down-shifting math to some IF
or possibly baseband
4. apply the CIC algorithm to FIR filter and decimate
5. apply up to two half band filters, further decimating
6. clip I and Q by one bit due to the potential, maximum gain in the
previous algorithms
I discovered the following:
* using an even (or unit) decimation prevents CIC rolloff
* two half band filters (abbreviated hb0 and hb1 in the Verilog and C++
code) are available, and each one decimates by a factor of two
* (half band filters are used as LPFs, when the signal is shifted all the
way down to baseband)
* the only data being poked into the USRP interface are { hb0 enabled, hb1
enabled, remaining decimation }
I'm sure you have spotted several misunderstandings in the above. I'm still
fuzzy on why the decimation is being set the way that it is. It feels like the
host-side driver code independently calculates all the filter and decimation
properties that will be reflected on the FPGA side. Please feel free to
clarify for me the down-shifting and the inherent decimation when using half
band filters (and anything I am completely oblivious to).
Thanks again for your help and guidance.
________________________________
From: USRP-users [usrp-users-boun...@lists.ettus.com] on behalf of Marcus D.
Leech via USRP-users [usrp-users@lists.ettus.com]
Sent: Monday, February 26, 2018 1:20 PM
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] USRP-users help needed
On 02/26/2018 12:07 PM, Stern, Joseph via USRP-users wrote:
Dear USRP users:
We have been trying to understand the low-level details of the USRP
architecture (namely, for the B200mini); there seems very little explicit
insight provided on the Ettus web site into how decimation is performed in the
FPGA (and commanded from the driver side). I also cannot locate the
open-source and freely available FPGA code. Could someone assist me in gaining
this insight?
Thank you very much!
Joe Stern
Ettus don't provide detailed design documents, but the source-code, as you say,
is freely available:
Get the source from here:
https://github.com/EttusResearch/uhd<https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_EttusResearch_uhd&d=DwMD-g&c=jF7FvYH6t0RX1HrEjVCgHQ&r=vWXAR8xWvtwGs07AdS9mJQ&m=rGbmCfzeF6q-zoIHxVGrc8mvjs23uG5B16LEwyZB024&s=lntqkIycEmI8ldUxVtPbN4bbNpPOaKDnF-4kYb40sqk&e=>
The do a "git submodule init"
The source bits of source code are somewhat separate, the the FPGA source code
being a GIT sub-module.
In terms of "how is decimation commanded", that's the host-side driver in
setting sample rates. The job is divided between the capabilities of the
AD9361 chip, and the FPGA. In many cases, almost the entirety of
decimation/filtering is done inside the AD9361 chip, since it effectively has
an internal
ADC that samples at 750Msps (can't remember the precise number), and the
sample rate offered on its data interface is relatively to that, so in many
cases, there is NO decimation performed within the FPGA. This is all in the
source code a shown above.
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