Dear Joe, All the FPGA Verilog code is available in the Github Repo: https://github.com/EttusResearch/fpga I believe the B200mini falls within the USRP3 category.
And about the decimation itself, after a quick search through the repo folders I found a DSP block that seems to indicate decimation is done using a CIC filter. Regards, Leo On Mon, Feb 26, 2018 at 2:59 PM Stern, Joseph via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear USRP users: > > > > We have been trying to understand the low-level details of the USRP > architecture (namely, for the B200mini); there seems very little explicit > insight provided on the Ettus web site into how decimation is performed in > the FPGA (and commanded from the driver side). I also cannot locate the > open-source and freely available FPGA code. Could someone assist me in > gaining this insight? > > > > Thank you very much! > > > > Joe Stern > This message and any enclosures are intended only for the addressee. > Please > notify the sender by email if you are not the intended recipient. If you > are > not the intended recipient, you may not use, copy, disclose, or distribute > this > message or its contents or enclosures to any other person and any such > actions > may be unlawful. Ball reserves the right to monitor and review all > messages > and enclosures sent to or from this email address. > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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