Adding macros for more configurable lowlevel_init code. Also cleanup of some typos. --- arch/arm/include/asm/arch-ks8695/platform.h | 55 ++++++++----- arch/arm/include/asm/arch-ks8695/regvalues.h | 112 ++++++++++++++++++++++++++ 2 files changed, 149 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h index de20015..0ed0ecb 100644 --- a/arch/arm/include/asm/arch-ks8695/platform.h +++ b/arch/arm/include/asm/arch-ks8695/platform.h @@ -13,8 +13,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __address_h -#define __address_h 1 +#ifndef __ASM_ARM_ARCH_PLATFORM_H__ +#define __ASM_ARM_ARCH_PLATFORM_H__ #define KS8695_SDRAM_START 0x00000000 #define KS8695_SDRAM_SIZE 0x01000000 @@ -27,19 +27,19 @@ #define KS8695_IO_BASE 0x03FF0000 #define KS8695_IO_SIZE 0x00010000 -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 +#define KS8695_SYSTEM_CONFIG 0x00 +#define KS8695_SYSTEM_BUS_CLOCK 0x04 #define KS8695_FLASH_START 0x02800000 #define KS8695_FLASH_SIZE 0x00400000 -/*i/o control registers offset difinitions*/ +/*i/o control register offset definitions*/ #define KS8695_IO_CTRL0 0x4000 #define KS8695_IO_CTRL1 0x4004 #define KS8695_IO_CTRL2 0x4008 #define KS8695_IO_CTRL3 0x400C -/*memory control registers offset difinitions*/ +/*memory control register offset definitions*/ #define KS8695_MEM_CTRL0 0x4010 #define KS8695_MEM_CTRL1 0x4014 #define KS8695_MEM_CTRL2 0x4018 @@ -51,7 +51,7 @@ #define KS8695_SDRAM_BUFFER 0x403C #define KS8695_SDRAM_REFRESH 0x4040 -/*WAN control registers offset difinitions*/ +/*WAN control register offset definitions*/ #define KS8695_WAN_DMA_TX 0x6000 #define KS8695_WAN_DMA_RX 0x6004 #define KS8695_WAN_DMA_TX_START 0x6008 @@ -63,7 +63,7 @@ #define KS8695_WAN_MAC_ELOW 0x6080 #define KS8695_WAN_MAC_EHIGH 0x6084 -/*LAN control registers offset difinitions*/ +/*LAN control register offset definitions*/ #define KS8695_LAN_DMA_TX 0x8000 #define KS8695_LAN_DMA_RX 0x8004 #define KS8695_LAN_DMA_TX_START 0x8008 @@ -75,7 +75,7 @@ #define KS8695_LAN_MAC_ELOW 0X8080 #define KS8695_LAN_MAC_EHIGH 0X8084 -/*HPNA control registers offset difinitions*/ +/*HPNA control register offset definitions*/ #define KS8695_HPNA_DMA_TX 0xA000 #define KS8695_HPNA_DMA_RX 0xA004 #define KS8695_HPNA_DMA_TX_START 0xA008 @@ -87,7 +87,7 @@ #define KS8695_HPNA_MAC_ELOW 0xA080 #define KS8695_HPNA_MAC_EHIGH 0xA084 -/*UART control registers offset difinitions*/ +/*UART control register offset definitions*/ #define KS8695_UART_RX_BUFFER 0xE000 #define KS8695_UART_TX_HOLDING 0xE004 @@ -133,7 +133,7 @@ #define KS8695_UART_DIVISOR 0xE01C #define KS8695_UART_STATUS 0xE020 -/*Interrupt controlller registers offset difinitions*/ +/*Interrupt controller register offset definitions*/ #define KS8695_INT_CONTL 0xE200 #define KS8695_INT_ENABLE 0xE204 #define KS8695_INT_ENABLE_MODEM 0x0800 @@ -154,19 +154,19 @@ #define KS8695_FIQ_PEND_PRIORITY 0xE230 #define KS8695_IRQ_PEND_PRIORITY 0xE234 -/*timer registers offset difinitions*/ +/*timer register offset definitions*/ #define KS8695_TIMER_CTRL 0xE400 #define KS8695_TIMER1 0xE404 #define KS8695_TIMER0 0xE408 #define KS8695_TIMER1_PCOUNT 0xE40C #define KS8695_TIMER0_PCOUNT 0xE410 -/*GPIO registers offset difinitions*/ +/*GPIO register offset definitions*/ #define KS8695_GPIO_MODE 0xE600 #define KS8695_GPIO_CTRL 0xE604 #define KS8695_GPIO_DATA 0xE608 -/*SWITCH registers offset difinitions*/ +/*SWITCH register offset definitions*/ #define KS8695_SWITCH_CTRL0 0xE800 #define KS8695_SWITCH_CTRL1 0xE804 #define KS8695_SWITCH_PORT1 0xE808 @@ -184,13 +184,13 @@ #define KS8695_SWITCH_LPPM12 0xE874 #define KS8695_SWITCH_LPPM34 0xE878 -/*host communication registers difinitions*/ +/*host communication register definitions*/ #define KS8695_DSCP_HIGH 0xE834 #define KS8695_DSCP_LOW 0xE838 #define KS8695_SWITCH_MAC_HIGH 0xE83C #define KS8695_SWITCH_MAC_LOW 0xE840 -/*miscellaneours registers difinitions*/ +/*miscellaneous register definitions*/ #define KS8695_MANAGE_COUNTER 0xE844 #define KS8695_MANAGE_DATA 0xE848 #define KS8695_LAN12_POWERMAGR 0xE84C @@ -205,7 +205,7 @@ #define KS8695_WAN_PHY_CONTROL 0xEA14 #define KS8695_WAN_PHY_STATUS 0xEA18 -/* bus clock definitions*/ +/* bus clock definitions for KS8695_SYSTEM_BUS_CLOCK */ #define KS8695_BUS_CLOCK_125MHZ 0x0 #define KS8695_BUS_CLOCK_100MHZ 0x1 #define KS8695_BUS_CLOCK_62MHZ 0x2 @@ -215,8 +215,27 @@ #define KS8695_BUS_CLOCK_31MHZ 0x6 #define KS8695_BUS_CLOCK_25MHZ 0x7 +/* bus width definitions for KS8695_MEM_GENERAL and SDRAM_CTRL */ +#define KS8695_BUS_WIDTH_OFF 0 +#define KS8695_BUS_WIDTH_8 1 +#define KS8695_BUS_WIDTH_16 2 +#define KS8695_BUS_WIDTH_32 3 + +/* register value definitions for memory controller */ +#define KS8695_SDCON_D_OFF (KS8695_BUS_WIDTH_OFF<<1) +#define KS8695_SDCON_D_8 (KS8695_BUS_WIDTH_8<<1) +#define KS8695_SDCON_D_16 (KS8695_BUS_WIDTH_16<<1) +#define KS8695_SDCON_D_32 (KS8695_BUS_WIDTH_32<<1) +#define KS8695_SDCON_2BANK 0x000 +#define KS8695_SDCON_4BANK 0x008 +#define KS8695_SDCON_CA_8BIT 0x000 +#define KS8695_SDCON_CA_9BIT 0x100 +#define KS8695_SDCON_CA_10BIT 0x200 +#define KS8695_SDCON_CA_11BIT 0x300 +#define KS8695_MEM_RANGE(BASE,SIZE) (((BASE)&0x03ff0000)>>(16-12) | (((BASE)+(SIZE)-1)&0x03ff0000)<<(22-16)) + /* ------------------------------------------------------------------------------- - * definations for IRQ + * definitions for IRQ * -------------------------------------------------------------------------------*/ #define KS8695_INT_EXT_INT0 2 diff --git a/arch/arm/include/asm/arch-ks8695/regvalues.h b/arch/arm/include/asm/arch-ks8695/regvalues.h new file mode 100644 index 0000000..7d29bbf --- /dev/null +++ b/arch/arm/include/asm/arch-ks8695/regvalues.h @@ -0,0 +1,112 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_REGVALUES_H__ +#define __ASM_ARM_ARCH_REGVALUES_H__ + +/* This file calculates register values set by low level initialization code + from configuration macros */ + +#define CONFIG_SYS_SDCS0_BASE CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_SDCS0_SIZE CONFIG_SYS_SDRAM_SIZE + +#ifndef CONFIG_SYS_RCS0_SPEED +/* access cycle time 5tmult+6, normal ROM (no pages) */ +# define CONFIG_SYS_RCS0_SPEED 0x040 +#endif +#ifndef CONFIG_SYS_RCS0_WIDTH +# define CONFIG_SYS_RCS0_WIDTH KS8695_BUS_WIDTH_8 +#endif + +#ifdef CONFIG_SYS_RCS1_BASE +# ifndef CONFIG_SYS_RCS1_WIDTH +# define CONFIG_SYS_RCS1_WIDTH CONFIG_SYS_RCS0_WIDTH +# endif +# ifndef CONFIG_SYS_RCS1_SPEED +# define CONFIG_SYS_RCS1_SPEED CONFIG_SYS_RCS0_SPEED +# endif +#else +# define CONFIG_SYS_RCS1_WIDTH KS8695_BUS_WIDTH_OFF +#endif + +#ifndef CONFIG_SYS_ECS0_WIDTH +# define CONFIG_SYS_ECS0_WIDTH KS8695_BUS_WIDTH_OFF +#endif +#ifndef CONFIG_SYS_ECS1_WIDTH +# define CONFIG_SYS_ECS1_WIDTH KS8695_BUS_WIDTH_OFF +#endif +#ifndef CONFIG_SYS_ECS2_WIDTH +# define CONFIG_SYS_ECS2_WIDTH KS8695_BUS_WIDTH_OFF +#endif + +#ifndef CONFIG_KS8695_TMULT +# define CONFIG_KS8695_TMULT 3 +#endif + +#if CONFIG_SYS_SDCS0_PARAMS +# ifndef CONFIG_SYS_SDCS0_BASE +# define CONFIG_SYS_SDCS0_BASE CONFIG_SYS_SDRAM_BASE +# define CONFIG_SYS_SDCS0_SIZE CONFIG_SYS_SDRAM_SIZE +# endif +#endif + +#define CONFIG_KS8695_ROMCON0_VALUE \ + (CONFIG_SYS_RCS0_SPEED | \ + KS8695_MEM_RANGE(CONFIG_SYS_RCS0_BASE,CONFIG_SYS_RCS0_SIZE)) +#define CONFIG_KS8695_ROMCON1_VALUE \ + (CONFIG_SYS_RCS1_SPEED | \ + KS8695_MEM_RANGE(CONFIG_SYS_RCS1_BASE,CONFIG_SYS_RCS1_SIZE)) +#define CONFIG_KS8695_EXTACON0_VALUE \ + (CONFIG_SYS_ECS0_SPEED | \ + KS8695_MEM_RANGE(CONFIG_SYS_ECS0_BASE,CONFIG_SYS_ECS0_SIZE)) +#define CONFIG_KS8695_EXTACON1_VALUE \ + (CONFIG_SYS_ECS1_SPEED | \ + KS8695_MEM_RANGE(CONFIG_SYS_ECS1_BASE,CONFIG_SYS_ECS1_SIZE)) +#define CONFIG_KS8695_EXTACON2_VALUE \ + (CONFIG_SYS_ECS2_SPEED | \ + KS8695_MEM_RANGE(CONFIG_SYS_ECS2_BASE,CONFIG_SYS_ECS2_SIZE)) + +#define CONFIG_KS8695_SDCON0_VALUE \ + (CONFIG_SYS_SDCS0_PARAMS | \ + KS8695_MEM_RANGE(CONFIG_SYS_SDCS0_BASE,CONFIG_SYS_SDCS0_SIZE)) +#define CONFIG_KS8695_SDCON1_VALUE \ + (CONFIG_SYS_SDCS1_PARAMS | \ + KS8695_MEM_RANGE(CONFIG_SYS_SDCS1_BASE,CONFIG_SYS_SDCS1_SIZE)) + +#if CONFIG_SYS_SDRAM_RAS_CAS_DELAY<1 || CONFIG_SYS_SDRAM_RAS_CAS_DELAY>4 +#error Unsupported SDRAM timing: RAS to CAS delay +#endif +#ifndef CONFIG_SYS_SDRAM_CAS_LATENCY +#define CONFIG_SYS_SDRAM_CAS_LATENCY ((CONFIG_SYS_SDRAM_MODE>>4)&7) +#endif +#if CONFIG_SYS_SDRAM_CAS_LATENCY<1 || CONFIG_SYS_SDRAM_CAS_LATENCY>4 +#error Unsupported SDRAM timing: CAS latency +#endif +#define CONFIG_KS8695_SDGCON_VALUE \ + ((CONFIG_SYS_SDRAM_RAS_CAS_DELAY-1)<<2 | \ + (CONFIG_SYS_SDRAM_CAS_LATENCY-1)) +#ifndef CONFIG_SYS_SDRAM_REFRESH_RATE +#define CONFIG_SYS_SDRAM_REFRESH_RATE 0x0190 +#endif + + +#define CONFIG_KS8695_ERGCON_VALUE (CONFIG_KS8695_TMULT<<28 | \ + CONFIG_SYS_ECS2_WIDTH<<20 | \ + CONFIG_SYS_ECS1_WIDTH<<18 | \ + CONFIG_SYS_ECS0_WIDTH<<16 | \ + CONFIG_SYS_RCS1_WIDTH<<2 | \ + CONFIG_SYS_RCS0_WIDTH) + +#endif -- 1.7.10.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
