On 04/09/24 09:55, Kumar, Udit wrote:
On 9/3/2024 5:13 PM, Neha Malcom Francis wrote:
Add bootph-pre-ram as well as the clocks and power-domains for
MAIN_R5_2_x. This ensures that LPSC sets the appropriate power and clock
and allows for BIST to turn the cores on and off for running the
self-test at R5 SPL stage.
Signed-off-by: Neha Malcom Francis <n-fran...@ti.com>
---
dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
index 5d9b0b6b59d..42dbf3083e1 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
@@ -1897,6 +1897,7 @@
ranges = <0x5900000 0x00 0x5900000 0x20000>,
<0x5a00000 0x00 0x5a00000 0x20000>;
power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
+ bootph-pre-ram;
main_r5fss2_core0: r5f@5900000 {
compatible = "ti,j721s2-r5f";
@@ -1911,6 +1912,10 @@
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
+ clocks = <&k3_clks 343 0>;
+ power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 343 0>;
+ bootph-pre-ram;
};
main_r5fss2_core1: r5f@5a00000 {
@@ -1926,6 +1931,10 @@
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
+ clocks = <&k3_clks 344 0>;
+ power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 344 0>;
+ bootph-pre-ram;
Only leaf nodes should be ok with bootph-pre-ram
Will change this, thanks!
};
};
--
Thanking You
Neha Malcom Francis
